[llvm-branch-commits] [llvm-branch] r329641 - Merging r327651:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Mon Apr  9 16:19:44 2018
New Revision: 329641

URL: http://llvm.org/viewvc/llvm-project?rev=329641&view=rev
Log:
Merging r327651:

------------------------------------------------------------------------
r327651 | carrot | 2018-03-15 10:49:12 -0700 (Thu, 15 Mar 2018) | 9 lines

[PPC] Avoid non-simple MVT in STBRX optimization

PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.

This patch detects the non-simple MVT and returns early.

Differential Revision: https://reviews.llvm.org/D44500

------------------------------------------------------------------------

Added:
    llvm/branches/release_60/test/CodeGen/PowerPC/pr35402.ll
Modified:
    llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp?rev=329641&r1=329640&r2=329641&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr  9 16:19:44 2018
@@ -12264,6 +12264,11 @@ SDValue PPCTargetLowering::PerformDAGCom
          N->getOperand(1).getValueType() == MVT::i16 ||
          (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
           N->getOperand(1).getValueType() == MVT::i64))) {
+      // STBRX can only handle simple types.
+      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
+      if (mVT.isExtended())
+        break;
+
       SDValue BSwapOp = N->getOperand(1).getOperand(0);
       // Do an any-extend to 32-bits if this is a half-word input.
       if (BSwapOp.getValueType() == MVT::i16)
@@ -12271,7 +12276,6 @@ SDValue PPCTargetLowering::PerformDAGCom
 
       // If the type of BSWAP operand is wider than stored memory width
       // it need to be shifted to the right side before STBRX.
-      EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
       if (Op1VT.bitsGT(mVT)) {
         int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
         BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,

Added: llvm/branches/release_60/test/CodeGen/PowerPC/pr35402.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/PowerPC/pr35402.ll?rev=329641&view=auto
==============================================================================
--- llvm/branches/release_60/test/CodeGen/PowerPC/pr35402.ll (added)
+++ llvm/branches/release_60/test/CodeGen/PowerPC/pr35402.ll Mon Apr  9 16:19:44 2018
@@ -0,0 +1,18 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+define void @test(i8* %p, i64 %data) {
+entry:
+  %0 = tail call i64 @llvm.bswap.i64(i64 %data)
+  %ptr = bitcast i8* %p to i48*
+  %val = trunc i64 %0 to i48
+  store i48 %val, i48* %ptr, align 1
+  ret void
+
+; CHECK:     sth
+; CHECK:     stw
+; CHECK-NOT: stdbrx
+
+}
+
+declare i64 @llvm.bswap.i64(i64)