[llvm-branch-commits] [llvm-branch] r329487 - Merging r328341:
Tom Stellard via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Apr 6 22:52:39 PDT 2018
Author: tstellar
Date: Fri Apr 6 22:52:39 2018
New Revision: 329487
URL: http://llvm.org/viewvc/llvm-project?rev=329487&view=rev
Log:
Merging r328341:
------------------------------------------------------------------------
r328341 | apazos | 2018-03-23 10:53:27 -0700 (Fri, 23 Mar 2018) | 16 lines
[ARM] Fix "Constant pool entry out of range!" in Thumb1 mode
This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode.
In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode,
adjustBBOffsetsAfter() is not calculating postOffset correctly by
properly accounting for the padding that is required for the constant pool
that immediately follows the jump table branch instruction.
Reviewers: t.p.northover, eli.friedman
Reviewed By: t.p.northover
Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44709
------------------------------------------------------------------------
Added:
llvm/branches/release_60/test/CodeGen/Thumb/PR36658.mir
Modified:
llvm/branches/release_60/lib/Target/ARM/ARMComputeBlockSize.cpp
Modified: llvm/branches/release_60/lib/Target/ARM/ARMComputeBlockSize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/ARM/ARMComputeBlockSize.cpp?rev=329487&r1=329486&r2=329487&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/ARM/ARMComputeBlockSize.cpp (original)
+++ llvm/branches/release_60/lib/Target/ARM/ARMComputeBlockSize.cpp Fri Apr 6 22:52:39 2018
@@ -35,6 +35,7 @@ mayOptimizeThumb2Instruction(const Machi
case ARM::tBcc:
// optimizeThumb2JumpTables.
case ARM::t2BR_JT:
+ case ARM::tBR_JTr:
return true;
}
return false;
Added: llvm/branches/release_60/test/CodeGen/Thumb/PR36658.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/Thumb/PR36658.mir?rev=329487&view=auto
==============================================================================
--- llvm/branches/release_60/test/CodeGen/Thumb/PR36658.mir (added)
+++ llvm/branches/release_60/test/CodeGen/Thumb/PR36658.mir Fri Apr 6 22:52:39 2018
@@ -0,0 +1,359 @@
+# REQUIRES: asserts
+# RUN: llc -run-pass arm-cp-islands %s -o - | FileCheck %s
+#
+# This is a reduced test made to expose a bug in
+# ARMConstantIslandPass in Thumb1 mode, see PR36658.
+
+# Verify optimized JT code uses TBB instructions.
+# CHECK-LABEL: bb.7.entry:
+# CHECK: tTBB_JT %pc, killed %r2, %jump-table.1, 0
+# CHECK-LABEL: bb.8:
+# CHECK: JUMPTABLE_TBB 0, %jump-table.1, 44
+
+# CHECK-LABEL: bb.11.entry:
+# CHECK: %r1 = tMOVSr %r0, implicit-def dead %cpsr
+# CHECK: tTBB_JT %pc, killed %r2, %jump-table.0, 1
+# CHECK-LABEL: bb.12:
+# CHECK: JUMPTABLE_TBB 1, %jump-table.0, 44
+
+--- |
+ ; ModuleID = 'PR36658.ll'
+ source_filename = "PR36658.ll"
+ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv5e-none-linux-gnueabi"
+
+ declare i32 @foo1(...)
+
+ declare i32 @foo2(i32)
+
+ declare i32 @foo3(i32*)
+
+ ; Function Attrs: nounwind optsize
+ define internal fastcc i32 @foo4(i32* nocapture %ignore_ptr) #0 {
+ entry:
+ %call = tail call i32 @foo3(i32* undef)
+ switch i32 %call, label %sw.epilog [
+ i32 120, label %sw.bb
+ i32 48, label %sw.bb73
+ i32 49, label %sw.bb73
+ i32 50, label %sw.bb73
+ i32 51, label %sw.bb73
+ i32 52, label %sw.bb73
+ i32 53, label %sw.bb73
+ i32 54, label %sw.bb73
+ i32 55, label %sw.bb73
+ i32 92, label %cleanup
+ i32 39, label %cleanup
+ i32 34, label %cleanup
+ i32 10, label %sw.bb91
+ i32 110, label %sw.bb93
+ i32 116, label %sw.bb94
+ i32 114, label %sw.bb95
+ i32 102, label %sw.bb96
+ i32 98, label %sw.bb97
+ i32 97, label %sw.bb98
+ i32 118, label %sw.bb106
+ i32 101, label %sw.bb107
+ i32 69, label %sw.bb107
+ i32 63, label %cleanup
+ ]
+
+ sw.bb: ; preds = %entry
+ br label %while.cond
+
+ while.cond: ; preds = %while.cond, %sw.bb
+ %call5 = tail call i32 @foo3(i32* null)
+ br label %while.cond
+
+ sw.bb73: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
+ %0 = and i32 %call, -8
+ %1 = icmp eq i32 %0, 48
+ br i1 %1, label %while.body83.preheader, label %while.end88
+
+ while.body83.preheader: ; preds = %sw.bb73
+ br label %while.body83
+
+ while.body83: ; preds = %while.body83.preheader, %while.body83
+ %call87 = tail call i32 @foo3(i32* null)
+ br label %while.body83
+
+ while.end88: ; preds = %sw.bb73
+ %call89 = tail call i32 @foo2(i32 %call)
+ unreachable
+
+ sw.bb91: ; preds = %entry
+ store i32 1, i32* %ignore_ptr, align 4
+ br label %cleanup
+
+ sw.bb93: ; preds = %entry
+ br label %cleanup
+
+ sw.bb94: ; preds = %entry
+ br label %cleanup
+
+ sw.bb95: ; preds = %entry
+ br label %cleanup
+
+ sw.bb96: ; preds = %entry
+ br label %cleanup
+
+ sw.bb97: ; preds = %entry
+ br label %cleanup
+
+ sw.bb98: ; preds = %entry
+ br label %cleanup
+
+ sw.bb106: ; preds = %entry
+ br label %cleanup
+
+ sw.bb107: ; preds = %entry, %entry
+ br i1 undef, label %cleanup, label %if.then109
+
+ if.then109: ; preds = %sw.bb107
+ %call110 = tail call i32 bitcast (i32 (...)* @foo1 to i32 (i8*, i32)*)(i8* undef, i32 %call)
+ unreachable
+
+ sw.epilog: ; preds = %entry
+ %call.off = add i32 %call, -32
+ unreachable
+
+ cleanup: ; preds = %sw.bb107, %sw.bb106, %sw.bb98, %sw.bb97, %sw.bb96, %sw.bb95, %sw.bb94, %sw.bb93, %sw.bb91, %entry, %entry, %entry, %entry
+ %retval.0 = phi i32 [ 11, %sw.bb106 ], [ 7, %sw.bb98 ], [ 8, %sw.bb97 ], [ 12, %sw.bb96 ], [ 13, %sw.bb95 ], [ 9, %sw.bb94 ], [ 10, %sw.bb93 ], [ 0, %sw.bb91 ], [ %call, %entry ], [ %call, %entry ], [ %call, %entry ], [ 27, %sw.bb107 ], [ %call, %entry ]
+ ret i32 %retval.0
+ }
+
+ ; Function Attrs: nounwind
+ declare void @llvm.stackprotector(i8*, i8**) #1
+
+ attributes #0 = { nounwind optsize }
+ attributes #1 = { nounwind }
+
+...
+---
+name: foo4
+alignment: 1
+tracksRegLiveness: true
+liveins:
+ - { reg: '%r0' }
+frameInfo:
+ stackSize: 8
+ maxAlignment: 4
+ adjustsStack: true
+ hasCalls: true
+ maxCallFrameSize: 0
+stack:
+ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: 0,
+ callee-saved-register: '%lr', callee-saved-restored: false }
+ - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: 0,
+ callee-saved-register: '%r4' }
+jumpTable:
+ kind: inline
+ entries:
+ - id: 0
+ blocks: [ '%bb.28', '%bb.26', '%bb.26', '%bb.26', '%bb.26',
+ '%bb.24', '%bb.23', '%bb.26', '%bb.26', '%bb.12',
+ '%bb.22' ]
+ - id: 1
+ blocks: [ '%bb.19', '%bb.26', '%bb.26', '%bb.26', '%bb.21',
+ '%bb.26', '%bb.20', '%bb.26', '%bb.25', '%bb.26',
+ '%bb.15' ]
+body: |
+ bb.0.entry:
+ successors: %bb.1(0x42c8590b), %bb.9(0x3d37a6f5)
+ liveins: %r0, %r4, %lr
+
+ frame-setup tPUSH 14, %noreg, killed %r4, killed %lr, implicit-def %sp, implicit %sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset %lr, -4
+ frame-setup CFI_INSTRUCTION offset %r4, -8
+ %r4 = tMOVSr %r0, implicit-def dead %cpsr
+ tBL 14, %noreg, @foo3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit undef %r0, implicit-def %sp, implicit-def %r0
+ %r1 = tMOVSr %r0, implicit-def dead %cpsr
+ tCMPi8 %r0, 68, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.9, 12, killed %cpsr
+
+ bb.1.entry:
+ successors: %bb.2(0x20000000), %bb.7(0x60000000)
+ liveins: %r0, %r1, %r4
+
+ tCMPi8 renamable %r1, 47, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.2, 13, killed %cpsr
+
+ bb.7.entry:
+ successors: %bb.16(0x71c71c72), %bb.8(0x0e38e38e)
+ liveins: %r0, %r1
+
+ %r2 = tMOVSr %r1, implicit-def dead %cpsr
+ renamable %r2, dead %cpsr = tSUBi8 killed renamable %r2, 48, 14, %noreg
+ tCMPi8 killed renamable %r2, 8, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.8, 2, killed %cpsr
+
+ bb.16.sw.bb73:
+ successors: %bb.17(0x7fffffff), %bb.18(0x00000001)
+ liveins: %r0, %r1
+
+ renamable %r2, dead %cpsr = tMOVi8 7, 14, %noreg
+ renamable %r1, dead %cpsr = tBIC killed renamable %r1, killed renamable %r2, 14, %noreg
+ tCMPi8 killed renamable %r1, 48, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.18, 1, killed %cpsr
+
+ bb.17.while.body83:
+ renamable %r0, dead %cpsr = tMOVi8 0, 14, %noreg
+ tBL 14, %noreg, @foo3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp, implicit-def dead %r0
+ tB %bb.17, 14, %noreg
+
+ bb.9.entry:
+ successors: %bb.10(0x45d1745d), %bb.29(0x3a2e8ba3)
+ liveins: %r0, %r1
+
+ %r2 = tMOVSr %r1, implicit-def dead %cpsr
+ renamable %r2, dead %cpsr = tSUBi8 killed renamable %r2, 92, 14, %noreg
+ tCMPi8 renamable %r2, 10, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.29, 9, killed %cpsr
+
+ bb.10.entry:
+ successors: %bb.11(0x15555555), %bb.14(0x6aaaaaab)
+ liveins: %r0, %r1
+
+ %r2 = tMOVSr %r1, implicit-def dead %cpsr
+ renamable %r2, dead %cpsr = tSUBi8 killed renamable %r2, 110, 14, %noreg
+ tCMPi8 renamable %r2, 10, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.11, 8, killed %cpsr
+
+ bb.14.entry:
+ successors: %bb.19(0x1999999a), %bb.26(0x00000000), %bb.21(0x1999999a), %bb.20(0x1999999a), %bb.25(0x1999999a), %bb.15(0x1999999a)
+ liveins: %r2
+
+ renamable %r0, dead %cpsr = tLSLri killed renamable %r2, 2, 14, %noreg
+ renamable %r1 = tLEApcrelJT %jump-table.1, 14, %noreg
+ renamable %r0 = tLDRr killed renamable %r1, killed renamable %r0, 14, %noreg :: (load 4 from jump-table)
+ tBR_JTr killed renamable %r0, %jump-table.1
+
+ bb.19.sw.bb93:
+ renamable %r1, dead %cpsr = tMOVi8 10, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.15.while.cond:
+ renamable %r0, dead %cpsr = tMOVi8 0, 14, %noreg
+ tBL 14, %noreg, @foo3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp, implicit-def dead %r0
+ tB %bb.15, 14, %noreg
+
+ bb.29.entry:
+ successors: %bb.28(0x1999999a), %bb.26(0x00000000), %bb.24(0x1999999a), %bb.23(0x1999999a), %bb.12(0x1999999a), %bb.22(0x1999999a)
+ liveins: %r0, %r2
+
+ renamable %r1, dead %cpsr = tLSLri killed renamable %r2, 2, 14, %noreg
+ renamable %r2 = tLEApcrelJT %jump-table.0, 14, %noreg
+ renamable %r2 = tLDRr killed renamable %r2, killed renamable %r1, 14, %noreg :: (load 4 from jump-table)
+ %r1 = tMOVSr %r0, implicit-def dead %cpsr
+ tBR_JTr killed renamable %r2, %jump-table.0
+
+ bb.24.sw.bb98:
+ renamable %r1, dead %cpsr = tMOVi8 7, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.2.entry:
+ successors: %bb.27(0x2aaaaaab), %bb.3(0x55555555)
+ liveins: %r0, %r1, %r4
+
+ tCMPi8 renamable %r1, 10, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.27, 0, killed %cpsr
+
+ bb.3.entry:
+ successors: %bb.4, %bb.5
+ liveins: %r0, %r1
+
+ tCMPi8 renamable %r1, 34, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.5, 1, killed %cpsr
+
+ bb.4:
+ liveins: %r0
+
+ %r1 = tMOVSr killed %r0, implicit-def dead %cpsr
+ tB %bb.28, 14, %noreg
+
+ bb.25.sw.bb106:
+ renamable %r1, dead %cpsr = tMOVi8 11, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.23.sw.bb97:
+ renamable %r1, dead %cpsr = tMOVi8 8, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.27.sw.bb91:
+ liveins: %r4
+
+ renamable %r0, dead %cpsr = tMOVi8 1, 14, %noreg
+ tSTRi killed renamable %r0, killed renamable %r4, 0, 14, %noreg :: (store 4 into %ir.ignore_ptr)
+ renamable %r1, dead %cpsr = tMOVi8 0, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.21.sw.bb95:
+ renamable %r1, dead %cpsr = tMOVi8 13, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.20.sw.bb94:
+ renamable %r1, dead %cpsr = tMOVi8 9, 14, %noreg
+ tB %bb.28, 14, %noreg
+
+ bb.5.entry:
+ liveins: %r0, %r1
+
+ tCMPi8 killed renamable %r1, 39, 14, %noreg, implicit-def %cpsr
+ tB %bb.6, 14, %noreg
+
+ bb.11.entry:
+ successors: %bb.12(0x80000000), %bb.26(0x00000000)
+ liveins: %r0, %r1
+
+ tCMPi8 killed renamable %r1, 69, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.26, 1, killed %cpsr
+
+ bb.12.sw.bb107:
+ successors: %bb.28(0x7fffffff), %bb.13(0x00000001)
+ liveins: %r0
+
+ renamable %r1, dead %cpsr = tMOVi8 27, 14, %noreg
+ renamable %r2, dead %cpsr = tMOVi8 0, 14, %noreg
+ tCMPi8 killed renamable %r2, 0, 14, %noreg, implicit-def %cpsr
+ tBcc %bb.28, 1, killed %cpsr
+
+ bb.13.if.then109:
+ successors:
+ liveins: %r0
+
+ %r1 = tMOVSr killed %r0, implicit-def dead %cpsr
+ tBL 14, %noreg, @foo1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit undef %r0, implicit %r1, implicit-def %sp, implicit-def dead %r0
+
+ bb.8.entry:
+ liveins: %r0, %r1
+
+ tCMPi8 killed renamable %r1, 63, 14, %noreg, implicit-def %cpsr
+
+ bb.6.entry:
+ successors: %bb.28(0x80000000), %bb.26(0x00000000)
+ liveins: %cpsr, %r0
+
+ tPUSH 14, %noreg, killed %r0, implicit-def %sp, implicit %sp
+ tPOP 14, %noreg, def %r1, implicit-def %sp, implicit %sp
+ tBcc %bb.28, 0, killed %cpsr
+
+ bb.26.sw.epilog:
+ successors:
+
+
+ bb.22.sw.bb96:
+ renamable %r1, dead %cpsr = tMOVi8 12, 14, %noreg
+
+ bb.28.cleanup:
+ liveins: %r1
+
+ %r0 = tMOVSr killed %r1, implicit-def dead %cpsr
+ tPOP_RET 14, %noreg, def %r4, def %pc, implicit-def %sp, implicit %sp, implicit %r0
+
+ bb.18.while.end88:
+ liveins: %r0
+
+ tBL 14, %noreg, @foo2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp, implicit-def dead %r0
+
+...
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