[llvm-branch-commits] [llvm-branch] r309171 - Merging r308808, r308813 and r308906:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jul 26 13:34:36 PDT 2017
Author: hans
Date: Wed Jul 26 13:34:36 2017
New Revision: 309171
URL: http://llvm.org/viewvc/llvm-project?rev=309171&view=rev
Log:
Merging r308808, r308813 and r308906:
------------------------------------------------------------------------
r308808 | arsenm | 2017-07-21 16:56:13 -0700 (Fri, 21 Jul 2017) | 6 lines
RA: Remove assert on empty live intervals
This is possible if there is an undef use when
splitting the vreg during spilling.
Fixes bug 33620.
------------------------------------------------------------------------
------------------------------------------------------------------------
r308813 | arsenm | 2017-07-21 17:24:01 -0700 (Fri, 21 Jul 2017) | 6 lines
RA: Remove another assert on empty intervals
This case is similar to the one fixed in r308808,
except when rematerializing.
Fixes bug 33884.
------------------------------------------------------------------------
------------------------------------------------------------------------
r308906 | arsenm | 2017-07-24 11:07:55 -0700 (Mon, 24 Jul 2017) | 6 lines
RA: Replace asserts related to empty live intervals
These don't exactly assert the same thing anymore, and
allow empty live intervals with non-empty uses.
Removed in r308808 and r308813.
------------------------------------------------------------------------
Added:
llvm/branches/release_50/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
- copied, changed from r308808, llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
Modified:
llvm/branches/release_50/ (props changed)
llvm/branches/release_50/lib/CodeGen/InlineSpiller.cpp
llvm/branches/release_50/lib/CodeGen/RegAllocBase.cpp
Propchange: llvm/branches/release_50/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 26 13:34:36 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308891,308950,308963,308986
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308986
Modified: llvm/branches/release_50/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/CodeGen/InlineSpiller.cpp?rev=309171&r1=309170&r2=309171&view=diff
==============================================================================
--- llvm/branches/release_50/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/branches/release_50/lib/CodeGen/InlineSpiller.cpp Wed Jul 26 13:34:36 2017
@@ -643,8 +643,11 @@ void InlineSpiller::reMaterializeAll() {
Edit->eraseVirtReg(Reg);
continue;
}
- assert((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) &&
- "Reg with empty interval has reference");
+
+ assert(LIS.hasInterval(Reg) &&
+ (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
+ "Empty and not used live-range?!");
+
RegsToSpill[ResultPos++] = Reg;
}
RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
Modified: llvm/branches/release_50/lib/CodeGen/RegAllocBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/CodeGen/RegAllocBase.cpp?rev=309171&r1=309170&r2=309171&view=diff
==============================================================================
--- llvm/branches/release_50/lib/CodeGen/RegAllocBase.cpp (original)
+++ llvm/branches/release_50/lib/CodeGen/RegAllocBase.cpp Wed Jul 26 13:34:36 2017
@@ -133,18 +133,19 @@ void RegAllocBase::allocatePhysRegs() {
if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
- for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
- I != E; ++I) {
- LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
+ for (unsigned Reg : SplitVRegs) {
+ assert(LIS->hasInterval(Reg));
+
+ LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
+ assert(SplitVirtReg->empty() && "Non-empty but used interval");
DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
aboutToRemoveInterval(*SplitVirtReg);
LIS->removeInterval(SplitVirtReg->reg);
continue;
}
DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
- assert(!SplitVirtReg->empty() && "expecting non-empty interval");
assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
"expect split value in virtual register");
enqueue(SplitVirtReg);
Copied: llvm/branches/release_50/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (from r308808, llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AMDGPU/spill-empty-live-interval.mir?p2=llvm/branches/release_50/test/CodeGen/AMDGPU/spill-empty-live-interval.mir&p1=llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir&r1=308808&r2=309171&rev=309171&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/spill-empty-live-interval.mir (original)
+++ llvm/branches/release_50/test/CodeGen/AMDGPU/spill-empty-live-interval.mir Wed Jul 26 13:34:36 2017
@@ -38,3 +38,37 @@ body: |
S_ENDPGM
...
+
+# Similar assert which happens when trying to rematerialize.
+# https://bugs.llvm.org/show_bug.cgi?id=33884
+---
+# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
+
+# CHECK-NOT: MOV
+# CHECK: undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+# CHECK: bb.1:
+# CHECK-NEXT: S_NOP 0, implicit %3.sub2
+# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
+# CHECK-NEXT: undef %4.sub2 = V_MOV_B32_e32 0, implicit %exec
+# CHECK-NEXT: S_NOP 0, implicit %4.sub2
+name: rematerialize_empty_interval_has_reference
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: vreg_128, preferred-register: '' }
+ - { id: 1, class: vgpr_32, preferred-register: '' }
+ - { id: 2, class: vgpr_32, preferred-register: '' }
+ - { id: 3, class: vreg_128, preferred-register: '' }
+body: |
+ bb.0:
+ successors: %bb.1
+
+ undef %0.sub2 = V_MOV_B32_e32 0, implicit %exec
+ undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+
+ bb.1:
+ S_NOP 0, implicit %3.sub2
+ S_NOP 0, implicit undef %0.sub0
+ S_NOP 0, implicit %0.sub2
+
+...
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