[llvm-branch-commits] [llvm-branch] r309157 - Merging rr308903:

[Matt Arsenault via llvm-branch-commits]

Author: arsenm
Date: Wed Jul 26 11:59:42 2017
New Revision: 309157

URL: http://llvm.org/viewvc/llvm-project?rev=309157&view=rev
Log:
Merging rr308903:
------------------------------------------------------------------------
r308903 | arsenm | 2017-07-24 11:06:15 -0700 (Mon, 24 Jul 2017) | 5 lines

AMDGPU: Fix allocating pseudo-registers

There's no need for these to be part of a class since
they are immediately replaced. New unreachable hit in
existing tests.'
------------------------------------------------------------------------

Modified:
    llvm/branches/release_50/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
    llvm/branches/release_50/lib/Target/AMDGPU/SIRegisterInfo.td

Modified: llvm/branches/release_50/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=309157&r1=309156&r2=309157&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/branches/release_50/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Wed Jul 26 11:59:42 2017
@@ -297,6 +297,11 @@ void AMDGPUInstPrinter::printRegOperand(
   case AMDGPU::FLAT_SCR_HI:
     O << "flat_scratch_hi";
     return;
+  case AMDGPU::FP_REG:
+  case AMDGPU::SP_REG:
+  case AMDGPU::SCRATCH_WAVE_OFFSET_REG:
+  case AMDGPU::PRIVATE_RSRC_REG:
+    llvm_unreachable("pseudo-register should not ever be emitted");
   default:
     break;
   }

Modified: llvm/branches/release_50/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AMDGPU/SIRegisterInfo.td?rev=309157&r1=309156&r2=309157&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AMDGPU/SIRegisterInfo.td Wed Jul 26 11:59:42 2017
@@ -274,8 +274,7 @@ def VGPR_512 : RegisterTuples<[sub0, sub
 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
   (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
    TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
-   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT,
-   FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
+   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
   let AllocationPriority = 7;
 }