[llvm-branch-commits] [llvm-branch] r293805 - Merging r293673:

Hans Wennborg via llvm-branch-commits llvm-branch-commits at lists.llvm.org
Wed Feb 1 11:41:46 PST 2017


Author: hans
Date: Wed Feb  1 13:41:46 2017
New Revision: 293805

URL: http://llvm.org/viewvc/llvm-project?rev=293805&view=rev
Log:
Merging r293673:
------------------------------------------------------------------------
r293673 | matze | 2017-01-31 10:37:53 -0800 (Tue, 31 Jan 2017) | 6 lines

InterleaveAccessPass: Avoid constructing invalid shuffle masks

Fix a bug where we would construct shufflevector instructions addressing
invalid elements.

Differential Revision: https://reviews.llvm.org/D29313
------------------------------------------------------------------------

Modified:
    llvm/branches/release_40/   (props changed)
    llvm/branches/release_40/lib/CodeGen/InterleavedAccessPass.cpp
    llvm/branches/release_40/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
    llvm/branches/release_40/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll

Propchange: llvm/branches/release_40/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Feb  1 13:41:46 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292117,292133,292242,292254-292255,292280,292323,292444,292467,292516,292583,292624-292625,292641,292651,292667,292711-292713,292758,293021,293025,293230,293259,293291,293293,293309,293417,293522,293629,293658,293727
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292117,292133,292242,292254-292255,292280,292323,292444,292467,292516,292583,292624-292625,292641,292651,292667,292711-292713,292758,293021,293025,293230,293259,293291,293293,293309,293417,293522,293629,293658,293673,293727

Modified: llvm/branches/release_40/lib/CodeGen/InterleavedAccessPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/InterleavedAccessPass.cpp?rev=293805&r1=293804&r2=293805&view=diff
==============================================================================
--- llvm/branches/release_40/lib/CodeGen/InterleavedAccessPass.cpp (original)
+++ llvm/branches/release_40/lib/CodeGen/InterleavedAccessPass.cpp Wed Feb  1 13:41:46 2017
@@ -174,7 +174,7 @@ static bool isDeInterleaveMask(ArrayRef<
 /// I.e. <0, LaneLen, ... , LaneLen*(Factor - 1), 1, LaneLen + 1, ...>
 /// E.g. For a Factor of 2 (LaneLen=4): <0, 4, 1, 5, 2, 6, 3, 7>
 static bool isReInterleaveMask(ArrayRef<int> Mask, unsigned &Factor,
-                               unsigned MaxFactor) {
+                               unsigned MaxFactor, unsigned OpNumElts) {
   unsigned NumElts = Mask.size();
   if (NumElts < 4)
     return false;
@@ -246,6 +246,9 @@ static bool isReInterleaveMask(ArrayRef<
 
       if (StartMask < 0)
         break;
+      // We must stay within the vectors; This case can happen with undefs.
+      if (StartMask + LaneLen > OpNumElts*2)
+        break;
     }
 
     // Found an interleaved mask of current factor.
@@ -406,7 +409,8 @@ bool InterleavedAccess::lowerInterleaved
 
   // Check if the shufflevector is RE-interleave shuffle.
   unsigned Factor;
-  if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor))
+  unsigned OpNumElts = SVI->getOperand(0)->getType()->getVectorNumElements();
+  if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts))
     return false;
 
   DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n");

Modified: llvm/branches/release_40/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll?rev=293805&r1=293804&r2=293805&view=diff
==============================================================================
--- llvm/branches/release_40/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll (original)
+++ llvm/branches/release_40/test/Transforms/InterleavedAccess/AArch64/interleaved-accesses.ll Wed Feb  1 13:41:46 2017
@@ -547,3 +547,21 @@ define void @store_general_mask_factor3_
   store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
   ret void
 }
+
+ at g = external global <4 x float>
+
+; The following does not give a valid interleaved store
+; NEON-LABEL: define void @no_interleave
+; NEON-NOT: call void @llvm.aarch64.neon.st2
+; NEON: shufflevector
+; NEON: store
+; NEON: ret void
+; NO_NEON-LABEL: define void @no_interleave
+; NO_NEON: shufflevector
+; NO_NEON: store
+; NO_NEON: ret void
+define void @no_interleave(<4 x float> %a0) {
+  %v0 = shufflevector <4 x float> %a0, <4 x float> %a0, <4 x i32> <i32 0, i32 3, i32 7, i32 undef>
+  store <4 x float> %v0, <4 x float>* @g, align 16
+  ret void
+}

Modified: llvm/branches/release_40/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll?rev=293805&r1=293804&r2=293805&view=diff
==============================================================================
--- llvm/branches/release_40/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll (original)
+++ llvm/branches/release_40/test/Transforms/InterleavedAccess/ARM/interleaved-accesses.ll Wed Feb  1 13:41:46 2017
@@ -626,3 +626,21 @@ define void @store_general_mask_factor3_
   store <12 x i32> %interleaved.vec, <12 x i32>* %ptr, align 4
   ret void
 }
+
+ at g = external global <4 x float>
+
+; The following does not give a valid interleaved store
+; NEON-LABEL: define void @no_interleave
+; NEON-NOT: call void @llvm.arm.neon.vst2
+; NEON: shufflevector
+; NEON: store
+; NEON: ret void
+; NO_NEON-LABEL: define void @no_interleave
+; NO_NEON: shufflevector
+; NO_NEON: store
+; NO_NEON: ret void
+define void @no_interleave(<4 x float> %a0) {
+  %v0 = shufflevector <4 x float> %a0, <4 x float> %a0, <4 x i32> <i32 0, i32 7, i32 1, i32 undef>
+  store <4 x float> %v0, <4 x float>* @g, align 16
+  ret void
+}




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