[llvm-branch-commits] [llvm-branch] r235340 - Merging r228190:

[Tom Stellard]

Author: tstellar
Date: Mon Apr 20 15:05:00 2015
New Revision: 235340

URL: http://llvm.org/viewvc/llvm-project?rev=235340&view=rev
Log:
Merging r228190:

------------------------------------------------------------------------
r228190 | thomas.stellard | 2015-02-04 15:49:52 -0500 (Wed, 04 Feb 2015) | 2 lines

R600/SI: Expand misaligned 16-bit memory accesses

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp
    llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll

Modified: llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp?rev=235340&r1=235339&r2=235340&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp Mon Apr 20 15:05:00 2015
@@ -323,6 +323,11 @@ bool SITargetLowering::allowsMisalignedM
     return Align % 4 == 0;
   }
 
+  // Smaller than dword value must be aligned.
+  // FIXME: This should be allowed on CI+
+  if (VT.bitsLT(MVT::i32))
+    return false;
+
   // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
   // byte-address are ignored, thus forcing Dword alignment.
   // This applies to private, global, and constant memory.

Modified: llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll?rev=235340&r1=235339&r2=235340&view=diff
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll (original)
+++ llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll Mon Apr 20 15:05:00 2015
@@ -1,6 +1,30 @@
 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
 
+; SI-LABEL: {{^}}unaligned_load_store_i16_local:
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: s_endpgm
+define void @unaligned_load_store_i16_local(i16 addrspace(3)* %p, i16 addrspace(3)* %r) nounwind {
+  %v = load i16 addrspace(3)* %p, align 1
+  store i16 %v, i16 addrspace(3)* %r, align 1
+  ret void
+}
+
+; SI-LABEL: {{^}}unaligned_load_store_i16_global:
+; SI: buffer_load_ubyte
+; SI: buffer_load_ubyte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: s_endpgm
+define void @unaligned_load_store_i16_global(i16 addrspace(1)* %p, i16 addrspace(1)* %r) nounwind {
+  %v = load i16 addrspace(1)* %p, align 1
+  store i16 %v, i16 addrspace(1)* %r, align 1
+  ret void
+}
+
 ; SI-LABEL: {{^}}unaligned_load_store_i32_local:
 ; SI: ds_read_u8
 ; SI: ds_read_u8