[llvm-branch-commits] [llvm-branch] r235339 - Merging r228189:

Tom Stellard thomas.stellard at amd.com
Mon Apr 20 13:04:59 PDT 2015 

Author: tstellar
Date: Mon Apr 20 15:04:59 2015
New Revision: 235339

URL: http://llvm.org/viewvc/llvm-project?rev=235339&view=rev
Log:
Merging r228189:

------------------------------------------------------------------------
r228189 | thomas.stellard | 2015-02-04 15:49:51 -0500 (Wed, 04 Feb 2015) | 9 lines

R600/SI: Make more store operations legal

v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces.  We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.

This enables lowering of misaligned stores of these types in the
DAGLegalizer.

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp
    llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp
    llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll

Modified: llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp?rev=235339&r1=235338&r2=235339&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/AMDGPUISelLowering.cpp Mon Apr 20 15:04:59 2015
@@ -159,9 +159,6 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
   // Custom lowering of vector stores is required for local address space
   // stores.
   setOperationAction(ISD::STORE, MVT::v4i32, Custom);
-  // XXX: Native v2i32 local address space stores are possible, but not
-  // currently implemented.
-  setOperationAction(ISD::STORE, MVT::v2i32, Custom);
 
   setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
   setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);

Modified: llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp?rev=235339&r1=235338&r2=235339&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIISelLowering.cpp Mon Apr 20 15:04:59 2015
@@ -89,8 +89,6 @@ SITargetLowering::SITargetLowering(Targe
   setOperationAction(ISD::STORE, MVT::v16i32, Custom);
 
   setOperationAction(ISD::STORE, MVT::i1, Custom);
-  setOperationAction(ISD::STORE, MVT::i32, Custom);
-  setOperationAction(ISD::STORE, MVT::v2i32, Custom);
   setOperationAction(ISD::STORE, MVT::v4i32, Custom);
 
   setOperationAction(ISD::SELECT, MVT::i64, Custom);
@@ -158,8 +156,6 @@ SITargetLowering::SITargetLowering(Targe
   for (MVT VT : MVT::fp_valuetypes())
     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
 
-  setTruncStoreAction(MVT::i32, MVT::i8, Custom);
-  setTruncStoreAction(MVT::i32, MVT::i16, Custom);
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
   setTruncStoreAction(MVT::i64, MVT::i32, Expand);
   setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
@@ -1125,11 +1121,6 @@ SDValue SITargetLowering::LowerSTORE(SDV
   EVT VT = Store->getMemoryVT();
 
   // These stores are legal.
-  if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
-      VT.isVector() && VT.getVectorNumElements() == 2 &&
-      VT.getVectorElementType() == MVT::i32)
-    return SDValue();
-
   if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
     if (VT.isVector() && VT.getVectorNumElements() > 4)
       return ScalarizeVectorStore(Op, DAG);

Modified: llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll?rev=235339&r1=235338&r2=235339&view=diff
==============================================================================
--- llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll (original)
+++ llvm/branches/release_36/test/CodeGen/R600/unaligned-load-store.ll Mon Apr 20 15:04:59 2015
@@ -6,7 +6,10 @@
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 ; SI: ds_read_u8
-; SI: ds_write_b32
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
   %v = load i32 addrspace(3)* %p, align 1
@@ -19,7 +22,10 @@ define void @unaligned_load_store_i32_lo
 ; SI: buffer_load_ubyte
 ; SI: buffer_load_ubyte
 ; SI: buffer_load_ubyte
-; SI: buffer_store_dword
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
 define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace(1)* %r) nounwind {
   %v = load i32 addrspace(1)* %p, align 1
   store i32 %v, i32 addrspace(1)* %r, align 1
@@ -35,8 +41,14 @@ define void @unaligned_load_store_i32_gl
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 ; SI: ds_read_u8
-; SI: ds_write_b32
-; SI: ds_write_b32
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(3)* %r) {
   %v = load i64 addrspace(3)* %p, align 1
@@ -53,8 +65,14 @@ define void @unaligned_load_store_i64_lo
 ; SI: buffer_load_ubyte
 ; SI: buffer_load_ubyte
 ; SI: buffer_load_ubyte
-; SI: buffer_store_dword
-; SI: buffer_store_dword
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
 define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace(1)* %r) {
   %v = load i64 addrspace(1)* %p, align 1
   store i64 %v, i64 addrspace(1)* %r, align 1
@@ -82,10 +100,25 @@ define void @unaligned_load_store_i64_gl
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 
-; SI: ds_write_b32
-; SI: ds_write_b32
-; SI: ds_write_b32
-; SI: ds_write_b32
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: ds_write_b8
 ; SI: s_endpgm
 define void @unaligned_load_store_v4i32_local(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
   %v = load <4 x i32> addrspace(3)* %p, align 1
@@ -149,12 +182,23 @@ define void @load_lds_i64_align_4_with_s
   ret void
 }
 
-; FIXME: Need to fix this case.
-; define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
-;   %val = load i64 addrspace(3)* %in, align 1
-;   store i64 %val, i64 addrspace(1)* %out, align 8
-;   ret void
-; }
+; SI-LABEL: {{^}}load_lds_i64_align_1:
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: buffer_store_dwordx2
+; SI: s_endpgm
+
+define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
+  %val = load i64 addrspace(3)* %in, align 1
+  store i64 %val, i64 addrspace(1)* %out, align 8
+  ret void
+}
 
 ; SI-LABEL: {{^}}store_lds_i64_align_4:
 ; SI: ds_write2_b32

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