[llvm-branch-commits] [llvm-branch] r204636 - Merging r200195:

[Tom Stellard]

Author: tstellar
Date: Mon Mar 24 13:21:21 2014
New Revision: 204636

URL: http://llvm.org/viewvc/llvm-project?rev=204636&view=rev
Log:
Merging r200195:

------------------------------------------------------------------------
r200195 | michel.daenzer | 2014-01-26 23:20:44 -0800 (Sun, 26 Jan 2014) | 4 lines

R600/SI: Add intrinsic for S_SENDMSG instruction

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

Added:
    llvm/branches/release_34/test/CodeGen/R600/llvm.SI.sendmsg.ll
Modified:
    llvm/branches/release_34/lib/Target/R600/SIInsertWaits.cpp
    llvm/branches/release_34/lib/Target/R600/SIInstructions.td
    llvm/branches/release_34/lib/Target/R600/SIIntrinsics.td

Modified: llvm/branches/release_34/lib/Target/R600/SIInsertWaits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/SIInsertWaits.cpp?rev=204636&r1=204635&r2=204636&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/SIInsertWaits.cpp (original)
+++ llvm/branches/release_34/lib/Target/R600/SIInsertWaits.cpp Mon Mar 24 13:21:21 2014
@@ -314,6 +314,12 @@ Counters SIInsertWaits::handleOperands(M
 
   Counters Result = ZeroCounts;
 
+  // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
+  // but we also want to wait for any other outstanding transfers before
+  // signalling other hardware blocks
+  if (MI.getOpcode() == AMDGPU::S_SENDMSG)
+    return LastIssued;
+
   // For each register affected by this
   // instruction increase the result sequence
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {

Modified: llvm/branches/release_34/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/SIInstructions.td?rev=204636&r1=204635&r2=204636&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/SIInstructions.td (original)
+++ llvm/branches/release_34/lib/Target/R600/SIInstructions.td Mon Mar 24 13:21:21 2014
@@ -22,6 +22,8 @@ def InterpSlot : Operand<i32> {
   let PrintMethod = "printInterpSlot";
 }
 
+def SendMsgImm : Operand<i32>;
+
 def isSI : Predicate<"Subtarget.getGeneration() "
                       ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
 
@@ -826,17 +828,25 @@ def S_BARRIER : SOPP <0x0000000a, (ins),
 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
   []
 >;
-} // End hasSideEffects
 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
-//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
+
+let Uses = [EXEC] in {
+  def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
+      [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
+  > {
+    let DisableEncoding = "$m0";
+  }
+} // End Uses = [EXEC]
+
 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
+} // End hasSideEffects
 
 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
   (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),

Modified: llvm/branches/release_34/lib/Target/R600/SIIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/R600/SIIntrinsics.td?rev=204636&r1=204635&r2=204636&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/R600/SIIntrinsics.td (original)
+++ llvm/branches/release_34/lib/Target/R600/SIIntrinsics.td Mon Mar 24 13:21:21 2014
@@ -38,6 +38,8 @@ let TargetPrefix = "SI", isTarget = 1 in
      llvm_i32_ty],   // tfe(imm)
     []>;
 
+  def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+
   class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 
   def int_SI_sample : Sample;

Added: llvm/branches/release_34/test/CodeGen/R600/llvm.SI.sendmsg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/R600/llvm.SI.sendmsg.ll?rev=204636&view=auto
==============================================================================
--- llvm/branches/release_34/test/CodeGen/R600/llvm.SI.sendmsg.ll (added)
+++ llvm/branches/release_34/test/CodeGen/R600/llvm.SI.sendmsg.ll Mon Mar 24 13:21:21 2014
@@ -0,0 +1,21 @@
+;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: @main
+; CHECK: S_SENDMSG 34
+; CHECK: S_SENDMSG 274
+; CHECK: S_SENDMSG 562
+; CHECK: S_SENDMSG 3
+
+define void @main() {
+main_body:
+  call void @llvm.SI.sendmsg(i32 34, i32 0);
+  call void @llvm.SI.sendmsg(i32 274, i32 0);
+  call void @llvm.SI.sendmsg(i32 562, i32 0);
+  call void @llvm.SI.sendmsg(i32 3, i32 0);
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.SI.sendmsg(i32, i32) #0
+
+attributes #0 = { nounwind }