[llvm-branch-commits] [llvm-branch] r213911 - Merge r213826

[Filipe Cabecinhas]

Author: filcab
Date: Thu Jul 24 19:00:11 2014
New Revision: 213911

URL: http://llvm.org/viewvc/llvm-project?rev=213911&view=rev
Log:
Merge r213826

------------------------------------------------------------------------
r213826 | filcab | 2014-07-23 18:28:21 -0700 (Wed, 23 Jul 2014) | 7 lines

Fixed PR20411 - bug in getINSERTPS()

When we had a vector_shuffle where we had an input from each vector, we
could miscompile it because we were assuming the input from V2 wouldn't
be moved from where it was on the vector.

Added a test case.


Modified:
    llvm/branches/release_35/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_35/test/CodeGen/X86/sse41.ll

Modified: llvm/branches/release_35/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/X86/X86ISelLowering.cpp?rev=213911&r1=213910&r2=213911&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_35/lib/Target/X86/X86ISelLowering.cpp Thu Jul 24 19:00:11 2014
@@ -9054,6 +9054,18 @@ static SDValue getINSERTPS(ShuffleVector
     To = V2;
     DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
                 Mask.begin();
+
+    // If we have 1 element from each vector, we have to check if we're
+    // changing V1's element's place. If so, we're done. Otherwise, we
+    // should assume we're changing V2's element's place and behave
+    // accordingly.
+    int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
+    if (FromV1 == FromV2 && DestIndex == Mask[DestIndex] % 4) {
+      From = V2;
+      To = V1;
+      DestIndex =
+          std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
+    }
   } else {
     assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
            "More than one element from V1 and from V2, or no elements from one "
@@ -9065,6 +9077,8 @@ static SDValue getINSERTPS(ShuffleVector
         std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
   }
 
+  // Get an index into the source vector in the range [0,4) (the mask is
+  // in the range [0,8) because it can address V1 and V2)
   unsigned SrcIndex = Mask[DestIndex] % 4;
   if (MayFoldLoad(From)) {
     // Trivial case, when From comes from a load and is only used by the

Modified: llvm/branches/release_35/test/CodeGen/X86/sse41.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/X86/sse41.ll?rev=213911&r1=213910&r2=213911&view=diff
==============================================================================
--- llvm/branches/release_35/test/CodeGen/X86/sse41.ll (original)
+++ llvm/branches/release_35/test/CodeGen/X86/sse41.ll Thu Jul 24 19:00:11 2014
@@ -714,3 +714,21 @@ define <4 x float> @pr20087(<4 x float>
   %ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
   ret <4 x float> %ret
 }
+
+; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
+define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
+; CHECK-LABEL: insertps_pr20411:
+; CHECK: movaps  {{[^,]*}}, %[[REG1:xmm.]]
+; CHECK: pshufd  {{.*}} ## [[REG2:xmm.]] = mem[3,0,0,0]
+; CHECK: insertps  {{.*}} ## xmm1 = [[REG2]][0],[[REG1]][3]{{.*}}
+
+  %gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>  ; 4 5 6 7
+
+  %shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
+  %shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
+
+  %ptrcast = bitcast i32* %RET to <4 x i32>*
+  store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4
+  ret void
+}