[llvm-branch-commits] [llvm-branch] r223746 - Merging r223318:

[Hal Finkel]

Author: hfinkel
Date: Mon Dec  8 20:36:22 2014
New Revision: 223746

URL: http://llvm.org/viewvc/llvm-project?rev=223746&view=rev
Log:
Merging r223318:
------------------------------------------------------------------------
r223318 | hfinkel | 2014-12-03 23:40:13 +0000 (Wed, 03 Dec 2014) | 12 lines

[PowerPC] Fix inline asm memory operands not to use r0

On PowerPC, inline asm memory operands might be expanded as 0($r), where $r is
a register containing the address. As a result, this register cannot be r0, and
we need to enforce this register subclass constraint to prevent miscompiling
the code (we'd get this constraint for free with the usual instruction
definitions, but that scheme has no knowledge of how we end up printing inline
asm memory operands, and so here we need to do it 'by hand'). We can accomplish
this within the current address-mode selection framework by introducing an
explicit COPY_TO_REGCLASS node.

Fixes PR21443.
------------------------------------------------------------------------

Added:
    llvm/branches/release_35/test/CodeGen/PowerPC/ia-mem-r0.ll
      - copied unchanged from r223318, llvm/trunk/test/CodeGen/PowerPC/ia-mem-r0.ll
Modified:
    llvm/branches/release_35/   (props changed)
    llvm/branches/release_35/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Propchange: llvm/branches/release_35/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Dec  8 20:36:22 2014
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,213653,213665,213726,213749,213773,213793,213798-213799,213815,213847,213880,213883-213884,213894-213896,213899,213915,213960,213966,213999,214060,214129,214180,214287,214331,214423,214429,214517,214519,214670,214674,214679,215685,215711,215793,215795,215806,216064,216262,216531,216891,216917,216920,217102,217115,217257,217993,218745,219441,220959,221009,221318,221408,221453,221501,221703,222338,222376,222500,222672,222996,223163,223170-223171,223220,223500
+/llvm/trunk:155241,213653,213665,213726,213749,213773,213793,213798-213799,213815,213847,213880,213883-213884,213894-213896,213899,213915,213960,213966,213999,214060,214129,214180,214287,214331,214423,214429,214517,214519,214670,214674,214679,215685,215711,215793,215795,215806,216064,216262,216531,216891,216917,216920,217102,217115,217257,217993,218745,219441,220959,221009,221318,221408,221453,221501,221703,222338,222376,222500,222672,222996,223163,223170-223171,223220,223318,223500

Modified: llvm/branches/release_35/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=223746&r1=223745&r2=223746&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/release_35/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Dec  8 20:36:22 2014
@@ -172,10 +172,20 @@ namespace {
     /// a register.  The case of adding a (possibly relocatable) constant to a
     /// register can be improved, but it is wrong to substitute Reg+Reg for
     /// Reg in an asm, because the load or store opcode would have to change.
-   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+    bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                       char ConstraintCode,
                                       std::vector<SDValue> &OutOps) override {
-      OutOps.push_back(Op);
+      // We need to make sure that this one operand does not end up in r0
+      // (because we might end up lowering this as 0(%op)).
+      const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
+      const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
+      SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
+      SDValue NewOp =
+        SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
+                                       SDLoc(Op), Op.getValueType(),
+                                       Op, RC), 0);
+
+      OutOps.push_back(NewOp);
       return false;
     }