[llvm-branch-commits] [cfe-branch] r223004 - Merged from r220566:
Daniel Sanders
daniel.sanders at imgtec.com
Mon Dec 1 02:32:00 PST 2014
Author: dsanders
Date: Mon Dec 1 04:32:00 2014
New Revision: 223004
URL: http://llvm.org/viewvc/llvm-project?rev=223004&view=rev
Log:
Merged from r220566:
[mips] Mark aggregate arguments passed in registers with the inreg attribute
Summary:
This allows us to easily identify them in the backend which in turn allows us
to handle them correctly for big-endian targets (where they must be shifted
into the upper bits of the register).
Depends on D5961
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: cfe-commits, theraven
Differential Revision: http://reviews.llvm.org/D5962
Modified:
cfe/branches/release_35/lib/CodeGen/TargetInfo.cpp
cfe/branches/release_35/test/CodeGen/mips-byval-arg.c
cfe/branches/release_35/test/CodeGen/mips-vector-arg.c
cfe/branches/release_35/test/CodeGen/mips64-class-return.cpp
cfe/branches/release_35/test/CodeGen/mips64-padding-arg.c
Modified: cfe/branches/release_35/lib/CodeGen/TargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_35/lib/CodeGen/TargetInfo.cpp?rev=223004&r1=223003&r2=223004&view=diff
==============================================================================
--- cfe/branches/release_35/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/branches/release_35/lib/CodeGen/TargetInfo.cpp Mon Dec 1 04:32:00 2014
@@ -5446,8 +5446,11 @@ MipsABIInfo::classifyArgumentType(QualTy
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
- return ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
- getPaddingType(OrigOffset, CurrOffset));
+ ABIArgInfo ArgInfo =
+ ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
+ getPaddingType(OrigOffset, CurrOffset));
+ ArgInfo.setInReg(true);
+ return ArgInfo;
}
// Treat an enum type as its underlying type.
Modified: cfe/branches/release_35/test/CodeGen/mips-byval-arg.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_35/test/CodeGen/mips-byval-arg.c?rev=223004&r1=223003&r2=223004&view=diff
==============================================================================
--- cfe/branches/release_35/test/CodeGen/mips-byval-arg.c (original)
+++ cfe/branches/release_35/test/CodeGen/mips-byval-arg.c Mon Dec 1 04:32:00 2014
@@ -7,8 +7,8 @@ typedef struct {
extern void foo2(S0);
-// O32-LABEL: define void @foo1(i32 %a0.coerce0, i32 %a0.coerce1, i32 %a0.coerce2)
-// N64-LABEL: define void @foo1(i64 %a0.coerce0, i32 %a0.coerce1)
+// O32-LABEL: define void @foo1(i32 inreg %a0.coerce0, i32 inreg %a0.coerce1, i32 inreg %a0.coerce2)
+// N64-LABEL: define void @foo1(i64 inreg %a0.coerce0, i32 inreg %a0.coerce1)
void foo1(S0 a0) {
foo2(a0);
Modified: cfe/branches/release_35/test/CodeGen/mips-vector-arg.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_35/test/CodeGen/mips-vector-arg.c?rev=223004&r1=223003&r2=223004&view=diff
==============================================================================
--- cfe/branches/release_35/test/CodeGen/mips-vector-arg.c (original)
+++ cfe/branches/release_35/test/CodeGen/mips-vector-arg.c Mon Dec 1 04:32:00 2014
@@ -8,19 +8,19 @@
typedef float v4sf __attribute__ ((__vector_size__ (16)));
typedef int v4i32 __attribute__ ((__vector_size__ (16)));
-// O32: define void @test_v4sf(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 signext %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW:#[0-9]+]]
-// O32: declare i32 @test_v4sf_2(i32, i32, i32, i32, i32 signext, i32, i32, i32, i32, i32)
-// N64: define void @test_v4sf(i64 %a1.coerce0, i64 %a1.coerce1, i32 signext %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW:#[0-9]+]]
-// N64: declare i32 @test_v4sf_2(i64, i64, i32 signext, i64, i64, i64)
+// O32: define void @test_v4sf(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) [[NUW:#[0-9]+]]
+// O32: declare i32 @test_v4sf_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
+// N64: define void @test_v4sf(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) [[NUW:#[0-9]+]]
+// N64: declare i32 @test_v4sf_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg)
extern test_v4sf_2(v4sf, int, v4sf);
void test_v4sf(v4sf a1, int a2, v4sf a3) {
test_v4sf_2(a3, a2, a1);
}
-// O32: define void @test_v4i32(i32 %a1.coerce0, i32 %a1.coerce1, i32 %a1.coerce2, i32 %a1.coerce3, i32 signext %a2, i32, i32 %a3.coerce0, i32 %a3.coerce1, i32 %a3.coerce2, i32 %a3.coerce3) [[NUW]]
-// O32: declare i32 @test_v4i32_2(i32, i32, i32, i32, i32 signext, i32, i32, i32, i32, i32)
-// N64: define void @test_v4i32(i64 %a1.coerce0, i64 %a1.coerce1, i32 signext %a2, i64, i64 %a3.coerce0, i64 %a3.coerce1) [[NUW]]
-// N64: declare i32 @test_v4i32_2(i64, i64, i32 signext, i64, i64, i64)
+// O32: define void @test_v4i32(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1, i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg %a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg %a3.coerce3) [[NUW]]
+// O32: declare i32 @test_v4i32_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
+// N64: define void @test_v4i32(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1, i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1) [[NUW]]
+// N64: declare i32 @test_v4i32_2(i64 inreg, i64 inreg, i32 signext, i64, i64 inreg, i64 inreg)
extern test_v4i32_2(v4i32, int, v4i32);
void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
test_v4i32_2(a3, a2, a1);
Modified: cfe/branches/release_35/test/CodeGen/mips64-class-return.cpp
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_35/test/CodeGen/mips64-class-return.cpp?rev=223004&r1=223003&r2=223004&view=diff
==============================================================================
--- cfe/branches/release_35/test/CodeGen/mips64-class-return.cpp (original)
+++ cfe/branches/release_35/test/CodeGen/mips64-class-return.cpp Mon Dec 1 04:32:00 2014
@@ -34,12 +34,12 @@ D1 foo2(void) {
return gd1;
}
-// CHECK-LABEL: define void @_Z4foo32D2(i64 %a0.coerce0, double %a0.coerce1)
+// CHECK-LABEL: define void @_Z4foo32D2(i64 inreg %a0.coerce0, double inreg %a0.coerce1)
void foo3(D2 a0) {
gd2 = a0;
}
-// CHECK-LABEL: define void @_Z4foo42D0(i64 %a0.coerce0, i64 %a0.coerce1)
+// CHECK-LABEL: define void @_Z4foo42D0(i64 inreg %a0.coerce0, i64 inreg %a0.coerce1)
void foo4(D0 a0) {
gd0 = a0;
}
Modified: cfe/branches/release_35/test/CodeGen/mips64-padding-arg.c
URL: http://llvm.org/viewvc/llvm-project/cfe/branches/release_35/test/CodeGen/mips64-padding-arg.c?rev=223004&r1=223003&r2=223004&view=diff
==============================================================================
--- cfe/branches/release_35/test/CodeGen/mips64-padding-arg.c (original)
+++ cfe/branches/release_35/test/CodeGen/mips64-padding-arg.c Mon Dec 1 04:32:00 2014
@@ -9,9 +9,9 @@ typedef struct {
// Insert padding to ensure arguments of type S0 are aligned to 16-byte boundaries.
-// N64-LABEL: define void @foo1(i32 signext %a0, i64, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 signext %b, i64, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
-// N64: tail call void @foo2(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, double %a1.coerce0, i64 %a1.coerce1, i64 %a1.coerce2, i64 %a1.coerce3, double %a2.coerce0, i64 %a2.coerce1, i64 %a2.coerce2, i64 %a2.coerce3, i32 signext 3, i64 undef, double %a3.coerce0, i64 %a3.coerce1, i64 %a3.coerce2, i64 %a3.coerce3)
-// N64: declare void @foo2(i32 signext, i32 signext, i32 signext, i64, double, i64, i64, i64, double, i64, i64, i64, i32 signext, i64, double, i64, i64, i64)
+// N64-LABEL: define void @foo1(i32 signext %a0, i64, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext %b, i64, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3)
+// N64: tail call void @foo2(i32 signext 1, i32 signext 2, i32 signext %a0, i64 undef, double inreg %a1.coerce0, i64 inreg %a1.coerce1, i64 inreg %a1.coerce2, i64 inreg %a1.coerce3, double inreg %a2.coerce0, i64 inreg %a2.coerce1, i64 inreg %a2.coerce2, i64 inreg %a2.coerce3, i32 signext 3, i64 undef, double inreg %a3.coerce0, i64 inreg %a3.coerce1, i64 inreg %a3.coerce2, i64 inreg %a3.coerce3)
+// N64: declare void @foo2(i32 signext, i32 signext, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg, double inreg, i64 inreg, i64 inreg, i64 inreg, i32 signext, i64, double inreg, i64 inreg, i64 inreg, i64 inreg)
extern void foo2(int, int, int, S0, S0, int, S0);
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