[llvm-branch-commits] [llvm-branch] r195741 - Merging r195364:

[Bill Wendling]

Author: void
Date: Tue Nov 26 05:16:34 2013
New Revision: 195741

URL: http://llvm.org/viewvc/llvm-project?rev=195741&view=rev
Log:
Merging r195364:
------------------------------------------------------------------------
r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines

[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.

Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.

In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.


------------------------------------------------------------------------

Added:
    llvm/branches/release_34/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
      - copied unchanged from r195364, llvm/trunk/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
Modified:
    llvm/branches/release_34/   (props changed)
    llvm/branches/release_34/lib/Target/Mips/MipsSEISelLowering.cpp

Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Nov 26 05:16:34 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195379,195397-195399,195421,195423,195432,195439,195476-195477,195479,195491-195493,195514,195528,195547,195567,195591,195599,195632,195635-195636,195670,195679,195716
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195421,195423,195432,195439,195476-195477,195479,195491-195493,195514,195528,195547,195567,195591,195599,195632,195635-195636,195670,195679,195716

Modified: llvm/branches/release_34/lib/Target/Mips/MipsSEISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/Mips/MipsSEISelLowering.cpp?rev=195741&r1=195740&r2=195741&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/Mips/MipsSEISelLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/Mips/MipsSEISelLowering.cpp Tue Nov 26 05:16:34 2013
@@ -594,9 +594,11 @@ static SDValue performORCombine(SDNode *
       Cond = Op0Op0;
       IfSet = Op0Op1;
 
-      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
+      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
+          Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
         IfClr = Op1Op1;
-      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
+      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
+               Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
         IfClr = Op1Op0;
 
       IsConstantMask = true;
@@ -609,9 +611,11 @@ static SDValue performORCombine(SDNode *
       Cond = Op0Op1;
       IfSet = Op0Op0;
 
-      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && Mask == ~InvMask)
+      if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
+          Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
         IfClr = Op1Op1;
-      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && Mask == ~InvMask)
+      else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
+               Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
         IfClr = Op1Op0;
 
       IsConstantMask = true;