[llvm-branch-commits] [llvm-branch] r182413 - Merging r182364:

[Bill Wendling]

Author: void
Date: Tue May 21 15:13:22 2013
New Revision: 182413

URL: http://llvm.org/viewvc/llvm-project?rev=182413&view=rev
Log:
Merging r182364:
------------------------------------------------------------------------
r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines

X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.

Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_33/   (props changed)
    llvm/branches/release_33/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_33/test/CodeGen/X86/vec_compare.ll

Propchange: llvm/branches/release_33/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue May 21 15:13:22 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,181286,181296,181313,181397,181423,181450,181524,181529,181540,181576-181580,181586,181600,181678,181706,181792,181800,181842,181864,182072,182113,182344
+/llvm/trunk:155241,181286,181296,181313,181397,181423,181450,181524,181529,181540,181576-181580,181586,181600,181678,181706,181792,181800,181842,181864,182072,182113,182344,182364

Modified: llvm/branches/release_33/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/lib/Target/X86/X86ISelLowering.cpp?rev=182413&r1=182412&r2=182413&view=diff
==============================================================================
--- llvm/branches/release_33/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_33/lib/Target/X86/X86ISelLowering.cpp Tue May 21 15:13:22 2013
@@ -9336,29 +9336,24 @@ static SDValue LowerVSETCC(SDValue Op, c
   if (Swap)
     std::swap(Op0, Op1);
 
-  // Since SSE has no unsigned integer comparisons, we need to flip  the sign
-  // bits of the inputs before performing those operations.
-  if (FlipSigns) {
-    EVT EltVT = VT.getVectorElementType();
-    SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
-                                      EltVT);
-    std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
-    SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
-                                    SignBits.size());
-    Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
-    Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
-  }
-
   // Check that the operation in question is available (most are plain SSE2,
   // but PCMPGTQ and PCMPEQQ have different requirements).
   if (VT == MVT::v2i64) {
     if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
       assert(Subtarget->hasSSE2() && "Don't know how to lower!");
 
-      // First cast everything to the right type,
+      // First cast everything to the right type.
       Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
       Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
 
+      // Since SSE has no unsigned integer comparisons, we need to flip the sign
+      // bits of the inputs before performing those operations.
+      if (FlipSigns) {
+        SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32);
+        Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
+        Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
+      }
+
       // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
       SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
       SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
@@ -9384,7 +9379,7 @@ static SDValue LowerVSETCC(SDValue Op, c
       // pcmpeqd + pshufd + pand.
       assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
 
-      // First cast everything to the right type,
+      // First cast everything to the right type.
       Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
       Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
 
@@ -9403,6 +9398,15 @@ static SDValue LowerVSETCC(SDValue Op, c
     }
   }
 
+  // Since SSE has no unsigned integer comparisons, we need to flip the sign
+  // bits of the inputs before performing those operations.
+  if (FlipSigns) {
+    EVT EltVT = VT.getVectorElementType();
+    SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
+    Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
+    Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
+  }
+
   SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
 
   // If the logical-not of the result is required, perform that now.

Modified: llvm/branches/release_33/test/CodeGen/X86/vec_compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_33/test/CodeGen/X86/vec_compare.ll?rev=182413&r1=182412&r2=182413&view=diff
==============================================================================
--- llvm/branches/release_33/test/CodeGen/X86/vec_compare.ll (original)
+++ llvm/branches/release_33/test/CodeGen/X86/vec_compare.ll Tue May 21 15:13:22 2013
@@ -131,9 +131,15 @@ define <2 x i64> @test10(<2 x i64> %A, <
 }
 
 define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
+; CHECK: [[CONSTSEG:[A-Z0-9_]*]]:
+; CHECK:      .long	2147483648
+; CHECK-NEXT: .long	2147483648
+; CHECK-NEXT: .long	2147483648
+; CHECK-NEXT: .long	2147483648
 ; CHECK: test11:
-; CHECK: pxor
-; CHECK: pxor
+; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
+; CHECK: pxor [[CONSTREG]]
+; CHECK: pxor [[CONSTREG]]
 ; CHECK: pcmpgtd %xmm1
 ; CHECK: pshufd $-96
 ; CHECK: pcmpeqd