[llvm-branch-commits] [llvm-branch] r196700 - Merging r196456:

[Bill Wendling]

Author: void
Date: Sat Dec  7 18:07:48 2013
New Revision: 196700

URL: http://llvm.org/viewvc/llvm-project?rev=196700&view=rev
Log:
Merging r196456:
------------------------------------------------------------------------
r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines

For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.

------------------------------------------------------------------------

Added:
    llvm/branches/release_34/test/CodeGen/AArch64/neon-simd-ldst.ll
      - copied unchanged from r196456, llvm/trunk/test/CodeGen/AArch64/neon-simd-ldst.ll
Modified:
    llvm/branches/release_34/   (props changed)
    llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.h

Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Dec  7 18:07:48 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196362,196369,196391,196508,196532,196538,196611,196638,196658
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196508,196532,196538,196611,196638,196658

Modified: llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=196700&r1=196699&r2=196700&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.cpp Sat Dec  7 18:07:48 2013
@@ -66,7 +66,7 @@ AArch64TargetLowering::AArch64TargetLowe
     addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
     addRegisterClass(MVT::v1f32, &AArch64::FPR32RegClass);
     addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
-    addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
+    addRegisterClass(MVT::v8i8,  &AArch64::FPR64RegClass);
     addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
     addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
     addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
@@ -403,6 +403,29 @@ static void getExclusiveOperation(unsign
   StrOpc = StoreOps[Log2_32(Size)];
 }
 
+// FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
+// have value type mapped, and they are both being defined as MVT::untyped.
+// Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
+// would fail to figure out the register pressure correctly.
+std::pair<const TargetRegisterClass*, uint8_t>
+AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
+  const TargetRegisterClass *RRC = 0;
+  uint8_t Cost = 1;
+  switch (VT.SimpleTy) {
+  default:
+    return TargetLowering::findRepresentativeClass(VT);
+  case MVT::v4i64:
+    RRC = &AArch64::QPairRegClass;
+    Cost = 2;
+    break;
+  case MVT::v8i64:
+    RRC = &AArch64::QQuadRegClass;
+    Cost = 4;
+    break;
+  }
+  return std::make_pair(RRC, Cost);
+}
+
 MachineBasicBlock *
 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
                                         unsigned Size,

Modified: llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.h?rev=196700&r1=196699&r2=196700&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.h (original)
+++ llvm/branches/release_34/lib/Target/AArch64/AArch64ISelLowering.h Sat Dec  7 18:07:48 2013
@@ -343,6 +343,10 @@ public:
   virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                                   unsigned Intrinsic) const LLVM_OVERRIDE;
 
+protected:
+  std::pair<const TargetRegisterClass*, uint8_t>
+  findRepresentativeClass(MVT VT) const;
+
 private:
   const InstrItineraryData *Itins;