[llvm-branch-commits] [llvm-branch] r196699 - Merging r196362:
Bill Wendling
isanbard at gmail.com
Sat Dec 7 16:07:31 PST 2013
Author: void
Date: Sat Dec 7 18:07:30 2013
New Revision: 196699
URL: http://llvm.org/viewvc/llvm-project?rev=196699&view=rev
Log:
Merging r196362:
------------------------------------------------------------------------
r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line
[AArch64 Neon] Add ACLE intrinsic vceqz_f64.
------------------------------------------------------------------------
Modified:
llvm/branches/release_34/ (props changed)
llvm/branches/release_34/lib/Target/AArch64/AArch64InstrNEON.td
llvm/branches/release_34/test/CodeGen/AArch64/neon-scalar-fp-compare.ll
Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Dec 7 18:07:30 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196361,196369,196391,196508,196532,196538,196611,196638,196658
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196151,196153,196189-196192,196198-196199,196208-196209,196211,196261,196267,196269,196294,196359-196362,196369,196391,196508,196532,196538,196611,196638,196658
Modified: llvm/branches/release_34/lib/Target/AArch64/AArch64InstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/AArch64/AArch64InstrNEON.td?rev=196699&r1=196698&r2=196699&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/AArch64/AArch64InstrNEON.td (original)
+++ llvm/branches/release_34/lib/Target/AArch64/AArch64InstrNEON.td Sat Dec 7 18:07:30 2013
@@ -4328,7 +4328,7 @@ multiclass NeonI_Scalar2SameMisc_cmpz_SD
[],
NoItinerary>;
def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
- (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
+ (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
!strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
[],
NoItinerary>;
@@ -4350,11 +4350,11 @@ multiclass Neon_Scalar2SameMisc_cmpz_SD_
Instruction INSTS,
Instruction INSTD> {
def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
- (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
- (INSTS FPR32:$Rn, fpimm:$FPImm)>;
+ (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
+ (INSTS FPR32:$Rn, fpz32:$FPImm)>;
def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
- (v1f64 (bitconvert (v8i8 Neon_AllZero))))),
- (INSTD FPR64:$Rn, 0)>;
+ (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
+ (INSTD FPR64:$Rn, fpz32:$FPImm)>;
}
multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
@@ -5067,6 +5067,8 @@ def : Neon_Scalar3Same_cmp_V1_D_size_pat
defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
FCMEQZssi, FCMEQZddi>;
+def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
+ (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
// Scalar Floating-point Compare Mask Greater Than Or Equal
defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
Modified: llvm/branches/release_34/test/CodeGen/AArch64/neon-scalar-fp-compare.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/AArch64/neon-scalar-fp-compare.ll?rev=196699&r1=196698&r2=196699&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/AArch64/neon-scalar-fp-compare.ll (original)
+++ llvm/branches/release_34/test/CodeGen/AArch64/neon-scalar-fp-compare.ll Sat Dec 7 18:07:30 2013
@@ -24,6 +24,15 @@ entry:
ret i64 %0
}
+define <1 x i64> @test_vceqz_f64(<1 x double> %a) #0 {
+; CHECK: test_vceqz_f64
+; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0
+entry:
+ %0 = fcmp oeq <1 x double> %a, zeroinitializer
+ %vceqz.i = zext <1 x i1> %0 to <1 x i64>
+ ret <1 x i64> %vceqz.i
+}
+
define i32 @test_vceqzs_f32(float %a) {
; CHECK: test_vceqzs_f32
; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
@@ -39,7 +48,7 @@ define i64 @test_vceqzd_f64(double %a) {
; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
entry:
%vceq.i = insertelement <1 x double> undef, double %a, i32 0
- %vceq1.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> zeroinitializer)
+ %vceq1.i = tail call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double> %vceq.i, <1 x float> zeroinitializer) #5
%0 = extractelement <1 x i64> %vceq1.i, i32 0
ret i64 %0
}
@@ -81,7 +90,7 @@ define i64 @test_vcgezd_f64(double %a) {
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
entry:
%vcge.i = insertelement <1 x double> undef, double %a, i32 0
- %vcge1.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> zeroinitializer)
+ %vcge1.i = tail call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double> %vcge.i, <1 x float> zeroinitializer) #5
%0 = extractelement <1 x i64> %vcge1.i, i32 0
ret i64 %0
}
@@ -123,7 +132,7 @@ define i64 @test_vcgtzd_f64(double %a) {
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
entry:
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0
- %vcgt1.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> zeroinitializer)
+ %vcgt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double> %vcgt.i, <1 x float> zeroinitializer) #5
%0 = extractelement <1 x i64> %vcgt1.i, i32 0
ret i64 %0
}
@@ -165,7 +174,7 @@ define i64 @test_vclezd_f64(double %a) {
; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
entry:
%vcle.i = insertelement <1 x double> undef, double %a, i32 0
- %vcle1.i = call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double> %vcle.i, <1 x double> zeroinitializer)
+ %vcle1.i = tail call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double> %vcle.i, <1 x float> zeroinitializer) #5
%0 = extractelement <1 x i64> %vcle1.i, i32 0
ret i64 %0
}
@@ -207,7 +216,7 @@ define i64 @test_vcltzd_f64(double %a) {
; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
entry:
%vclt.i = insertelement <1 x double> undef, double %a, i32 0
- %vclt1.i = call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double> %vclt.i, <1 x double> zeroinitializer)
+ %vclt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double> %vclt.i, <1 x float> zeroinitializer) #5
%0 = extractelement <1 x i64> %vclt1.i, i32 0
ret i64 %0
}
@@ -301,15 +310,18 @@ entry:
}
declare <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
+declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
declare <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
+declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
declare <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
-declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
+declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
declare <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
+declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
declare <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
-declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
+declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
declare <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
declare <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
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