[llvm-branch-commits] [llvm-branch] r164606 - in /llvm/branches/AMDILBackend: CMakeLists.txt configure

[Micah Villmow]

Author: mvillmow
Date: Tue Sep 25 11:08:16 2012
New Revision: 164606

URL: http://llvm.org/viewvc/llvm-project?rev=164606&view=rev
Log:
Add the AMDIL target to the list of possible targets.

Modified:
    llvm/branches/AMDILBackend/CMakeLists.txt
    llvm/branches/AMDILBackend/configure

Modified: llvm/branches/AMDILBackend/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/CMakeLists.txt?rev=164606&r1=164605&r2=164606&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/CMakeLists.txt (original)
+++ llvm/branches/AMDILBackend/CMakeLists.txt Tue Sep 25 11:08:16 2012
@@ -86,6 +86,7 @@
   Sparc
   X86
   XCore
+  AMDIL
   )
 
 # List of targets with JIT support:

Modified: llvm/branches/AMDILBackend/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/AMDILBackend/configure?rev=164606&r1=164605&r2=164606&view=diff
==============================================================================
--- llvm/branches/AMDILBackend/configure (original)
+++ llvm/branches/AMDILBackend/configure Tue Sep 25 11:08:16 2012
@@ -1424,7 +1424,7 @@
   --enable-targets        Build specific host targets: all or
                           target1,target2,... Valid targets are: host, x86,
                           x86_64, sparc, powerpc, arm, mips, spu, hexagon,
-                          xcore, msp430, nvptx, and cpp (default=all)
+                          xcore, msp430, nvptx, amdil and cpp (default=all)
   --enable-experimental-targets
                           Build experimental host targets: disable or
                           target1,target2,... (default=disable)
@@ -3909,6 +3909,7 @@
   hexagon-*)              llvm_cv_target_arch="Hexagon" ;;
   mblaze-*)               llvm_cv_target_arch="MBlaze" ;;
   nvptx-*)                llvm_cv_target_arch="NVPTX" ;;
+  amdil-*)                llvm_cv_target_arch="AMDIL" ;;
   *)                      llvm_cv_target_arch="Unknown" ;;
 esac
 fi
@@ -5193,6 +5194,8 @@
  ;;
     NVPTX)       TARGET_HAS_JIT=0
  ;;
+    AMDIL)       TARGET_HAS_JIT=0
+ ;;
     *)           TARGET_HAS_JIT=0
  ;;
   esac
@@ -5377,7 +5380,7 @@
   enableval=host
 fi
 case "$enableval" in
-  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+  all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX AMDIL Hexagon" ;;
   *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
       case "$a_target" in
         x86)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5394,6 +5397,7 @@
         hexagon)  TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
         mblaze)   TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
         nvptx)    TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+        amdil)    TARGETS_TO_BUILD="AMDIL $TARGETS_TO_BUILD" ;;
         host) case "$llvm_cv_target_arch" in
             x86)         TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
             x86_64)      TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5407,6 +5411,7 @@
             MSP430)      TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
             Hexagon)     TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
             NVPTX)       TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;
+            AMDIL)       TARGETS_TO_BUILD="AMDIL $TARGETS_TO_BUILD" ;;
             *)       { { echo "$as_me:$LINENO: error: Can not set target to build" >&5
 echo "$as_me: error: Can not set target to build" >&2;}
    { (exit 1); exit 1; }; } ;;