[llvm-branch-commits] [llvm-branch] r168353 - in /llvm/branches/release_32: ./ docs/ReleaseNotes.html

Hal Finkel hfinkel at anl.gov
Mon Nov 19 20:22:44 PST 2012

Author: hfinkel
Date: Mon Nov 19 22:22:44 2012
New Revision: 168353

URL: http://llvm.org/viewvc/llvm-project?rev=168353&view=rev
Merge in PPC release notes: r168189 and r168352.

    llvm/branches/release_32/   (props changed)

Propchange: llvm/branches/release_32/
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Nov 19 22:22:44 2012
@@ -1,3 +1,3 @@

Modified: llvm/branches/release_32/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_32/docs/ReleaseNotes.html?rev=168353&r1=168352&r2=168353&view=diff
--- llvm/branches/release_32/docs/ReleaseNotes.html (original)
+++ llvm/branches/release_32/docs/ReleaseNotes.html Mon Nov 19 22:22:44 2012
@@ -647,6 +647,46 @@
+<a name="PowerPC">PowerPC Target Improvements</a>
+<p>Many fixes and changes across LLVM (and Clang) for better compliance with
+   the 64-bit PowerPC ELF Application Binary Interface, interoperability with
+   GCC, and overall 64-bit PowerPC support.   Some highlights include:</p>
+  <li>  MCJIT support added.</li>
+  <li>  PPC64 relocation support and (small code model) TOC handling
+        added.</li>
+  <li>  Parameter passing and return value fixes (alignment issues,
+        padding, varargs support, proper register usage, odd-sized
+        structure support, float support, extension of return values
+        for i32 return values).</li>
+  <li>  Fixes in spill and reload code for vector registers.</li>
+  <li>  C++ exception handling enabled.</li>
+  <li>  Changes to remediate double-rounding compatibility issues with
+        respect to GCC behavior.</li>
+  <li>  Refactoring to disentangle ppc64-elf-linux ABI from Darwin
+        ppc64 ABI support.</li>
+  <li>  Assorted new test cases and test case fixes (endian and word
+        size issues).</li>
+  <li>  Fixes for big-endian codegen bugs, instruction encodings, and
+        instruction constraints.</li>
+  <li>  Implemented -integrated-as support.</li>
+  <li>  Additional support for Altivec compare operations.</li>
+  <li>  IBM long double support.</li>
+<p>There have also been code generation improvements for both 32- and 64-bit
+   code. Instruction scheduling support for the Freescale e500mc and e5500
+   cores has been added.</p>
 <a name="OtherTS">Other Target Specific Improvements</a>

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