[llvm-branch-commits] [llvm-branch] r168336 - in /llvm/branches/release_32: ./ lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2010-01-08-Atomic64Bug.ll test/CodeGen/X86/pr14314.ll

[Pawel Wodnicki]

Author: pawel
Date: Mon Nov 19 16:31:55 2012
New Revision: 168336

URL: http://llvm.org/viewvc/llvm-project?rev=168336&view=rev
Log:
Merging r167718 into 3.2 release branch

Fix PR14314

- Fix operand order for atomic sub, where the minuend is the value
  loaded from memory and the subtrahend is the parameter specified.


Added:
    llvm/branches/release_32/test/CodeGen/X86/pr14314.ll
      - copied unchanged from r167718, llvm/trunk/test/CodeGen/X86/pr14314.ll
Modified:
    llvm/branches/release_32/   (props changed)
    llvm/branches/release_32/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_32/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll

Propchange: llvm/branches/release_32/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Nov 19 16:31:55 2012
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,167719,167731,167743,167750,167784,167811,167817,167855,167942,167948,167966,168198
+/llvm/trunk:155241,167718-167719,167731,167743,167750,167784,167811,167817,167855,167942,167948,167966,168198

Modified: llvm/branches/release_32/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_32/lib/Target/X86/X86ISelLowering.cpp?rev=168336&r1=168335&r2=168336&view=diff
==============================================================================
--- llvm/branches/release_32/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_32/lib/Target/X86/X86ISelLowering.cpp Mon Nov 19 16:31:55 2012
@@ -12729,8 +12729,8 @@
   case X86::ATOMSUB6432: {
     unsigned HiOpc;
     unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
-    BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg).addReg(LoReg);
-    BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg).addReg(HiReg);
+    BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
+    BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
     break;
   }
   case X86::ATOMNAND6432: {

Modified: llvm/branches/release_32/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_32/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll?rev=168336&r1=168335&r2=168336&view=diff
==============================================================================
--- llvm/branches/release_32/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll (original)
+++ llvm/branches/release_32/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll Mon Nov 19 16:31:55 2012
@@ -10,10 +10,10 @@
 ; CHECK: movl ([[REG:%[a-z]+]]), %eax
 ; CHECK: movl 4([[REG]]), %edx
 ; CHECK: LBB0_1:
-; CHECK: movl $1
-; CHECK: addl
-; CHECK: movl $0
-; CHECK: adcl
+; CHECK: movl %eax, %ebx
+; CHECK: addl {{%[a-z]+}}, %ebx
+; CHECK: movl %edx, %ecx
+; CHECK: adcl {{%[a-z]+}}, %ecx
 ; CHECK: lock
 ; CHECK-NEXT: cmpxchg8b ([[REG]])
 ; CHECK-NEXT: jne