[llvm-branch-commits] [llvm-branch] r167843 - in /llvm/branches/R600/lib/Target/AMDGPU: AMDGPU.h AMDGPUTargetMachine.cpp SIFixSGPRLiveness.cpp SILowerControlFlow.cpp SILowerFlowControl.cpp
Tom Stellard
thomas.stellard at amd.com
Tue Nov 13 07:22:14 PST 2012
Author: tstellar
Date: Tue Nov 13 09:22:13 2012
New Revision: 167843
URL: http://llvm.org/viewvc/llvm-project?rev=167843&view=rev
Log:
SI: s/flow control/control flow/g .
Patch by: Michel Dänzer
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Added:
llvm/branches/R600/lib/Target/AMDGPU/SILowerControlFlow.cpp
- copied, changed from r167842, llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp
Removed:
llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp
Modified:
llvm/branches/R600/lib/Target/AMDGPU/AMDGPU.h
llvm/branches/R600/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/branches/R600/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp
Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPU.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPU.h?rev=167843&r1=167842&r2=167843&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPU.h (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPU.h Tue Nov 13 09:22:13 2012
@@ -25,7 +25,7 @@
// SI Passes
FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
-FunctionPass *createSILowerFlowControlPass(TargetMachine &tm);
+FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
FunctionPass *createSILowerLiteralConstantsPass(TargetMachine &tm);
FunctionPass *createSIFixSGPRLivenessPass(TargetMachine &tm);
Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=167843&r1=167842&r2=167843&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Tue Nov 13 09:22:13 2012
@@ -137,7 +137,7 @@
addPass(&FinalizeMachineBundlesID);
} else {
addPass(createSILowerLiteralConstantsPass(*TM));
- addPass(createSILowerFlowControlPass(*TM));
+ addPass(createSILowerControlFlowPass(*TM));
}
return false;
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp?rev=167843&r1=167842&r2=167843&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIFixSGPRLiveness.cpp Tue Nov 13 09:22:13 2012
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// SGPRs are not affected by flow control. This pass adjust SGPR liveness in
+// SGPRs are not affected by control flow. This pass adjust SGPR liveness in
// so that the register allocator can still correctly allocate them.
//
//===----------------------------------------------------------------------===//
Copied: llvm/branches/R600/lib/Target/AMDGPU/SILowerControlFlow.cpp (from r167842, llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SILowerControlFlow.cpp?p2=llvm/branches/R600/lib/Target/AMDGPU/SILowerControlFlow.cpp&p1=llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp&r1=167842&r2=167843&rev=167843&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SILowerControlFlow.cpp Tue Nov 13 09:22:13 2012
@@ -1,4 +1,4 @@
-//===-- SILowerFlowControl.cpp - Use predicates for flow control ----------===//
+//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,10 +7,10 @@
//
//===----------------------------------------------------------------------===//
//
-// This pass lowers the pseudo flow control instructions (SI_IF_NZ, ELSE, ENDIF)
+// This pass lowers the pseudo control flow instructions (SI_IF_NZ, ELSE, ENDIF)
// to predicated instructions.
//
-// All flow control (except loops) is handled using predicated instructions and
+// All control flow (except loops) is handled using predicated instructions and
// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
// by writting to the 64-bit EXEC register (each bit corresponds to a
@@ -61,7 +61,7 @@
namespace {
-class SILowerFlowControlPass : public MachineFunctionPass {
+class SILowerControlFlowPass : public MachineFunctionPass {
private:
static char ID;
@@ -73,26 +73,26 @@
void popExecMask(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
public:
- SILowerFlowControlPass(TargetMachine &tm) :
+ SILowerControlFlowPass(TargetMachine &tm) :
MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
const char *getPassName() const {
- return "SI Lower flow control instructions";
+ return "SI Lower control flow instructions";
}
};
} // End anonymous namespace
-char SILowerFlowControlPass::ID = 0;
+char SILowerControlFlowPass::ID = 0;
-FunctionPass *llvm::createSILowerFlowControlPass(TargetMachine &tm) {
- return new SILowerFlowControlPass(tm);
+FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
+ return new SILowerControlFlowPass(tm);
}
-bool SILowerFlowControlPass::runOnMachineFunction(MachineFunction &MF) {
+bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
// Find all the unused registers that can be used for the predicate stack.
for (TargetRegisterClass::iterator I = AMDGPU::SReg_64RegClass.begin(),
@@ -169,7 +169,7 @@
return false;
}
-void SILowerFlowControlPass::pushExecMask(MachineBasicBlock &MBB,
+void SILowerControlFlowPass::pushExecMask(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) {
assert(!UnusedRegisters.empty() && "Ran out of registers for predicate stack");
@@ -181,7 +181,7 @@
.addReg(AMDGPU::EXEC);
}
-void SILowerFlowControlPass::popExecMask(MachineBasicBlock &MBB,
+void SILowerControlFlowPass::popExecMask(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) {
unsigned StackReg = PredicateStack.back();
PredicateStack.pop_back();
Removed: llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp?rev=167842&view=auto
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SILowerFlowControl.cpp (removed)
@@ -1,193 +0,0 @@
-//===-- SILowerFlowControl.cpp - Use predicates for flow control ----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass lowers the pseudo flow control instructions (SI_IF_NZ, ELSE, ENDIF)
-// to predicated instructions.
-//
-// All flow control (except loops) is handled using predicated instructions and
-// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
-// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
-// by writting to the 64-bit EXEC register (each bit corresponds to a
-// single vector ALU). Typically, for predicates, a vector ALU will write
-// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
-// Vector ALU) and then the ScalarALU will AND the VCC register with the
-// EXEC to update the predicates.
-//
-// For example:
-// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
-// SI_IF_NZ %VCC
-// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
-// ELSE
-// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
-// ENDIF
-//
-// becomes:
-//
-// %SGPR0 = S_MOV_B64 %EXEC // Save the current exec mask
-// %EXEC = S_AND_B64 %VCC, %EXEC // Update the exec mask
-// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
-// S_CBRANCH_EXECZ label0 // This instruction is an
-// // optimization which allows us to
-// // branch if all the bits of
-// // EXEC are zero.
-// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
-//
-// label0:
-// %SGPR2 = S_MOV_B64 %EXEC // Save the current exec mask
-// %EXEC = S_MOV_B64 %SGPR0 // Restore the exec mask for the Then block
-// %SGPR0 = S_MOV_B64 %SGPR2 // Save the exec mask from the If block
-// S_BRANCH_EXECZ label1 // Use our branch optimization
-// // instruction again.
-// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
-// label1:
-// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
-//===----------------------------------------------------------------------===//
-
-#include "AMDGPU.h"
-#include "SIInstrInfo.h"
-#include "SIMachineFunctionInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-namespace {
-
-class SILowerFlowControlPass : public MachineFunctionPass {
-
-private:
- static char ID;
- const TargetInstrInfo *TII;
- std::vector<unsigned> PredicateStack;
- std::vector<unsigned> UnusedRegisters;
-
- void pushExecMask(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
- void popExecMask(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
-
-public:
- SILowerFlowControlPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
- const char *getPassName() const {
- return "SI Lower flow control instructions";
- }
-
-};
-
-} // End anonymous namespace
-
-char SILowerFlowControlPass::ID = 0;
-
-FunctionPass *llvm::createSILowerFlowControlPass(TargetMachine &tm) {
- return new SILowerFlowControlPass(tm);
-}
-
-bool SILowerFlowControlPass::runOnMachineFunction(MachineFunction &MF) {
-
- // Find all the unused registers that can be used for the predicate stack.
- for (TargetRegisterClass::iterator I = AMDGPU::SReg_64RegClass.begin(),
- S = AMDGPU::SReg_64RegClass.end();
- I != S; ++I) {
- unsigned Reg = *I;
- if (!MF.getRegInfo().isPhysRegUsed(Reg)) {
- UnusedRegisters.insert(UnusedRegisters.begin(), Reg);
- }
- }
-
- for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
- BB != BB_E; ++BB) {
- MachineBasicBlock &MBB = *BB;
- for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
- I != MBB.end(); I = Next) {
- Next = llvm::next(I);
- MachineInstr &MI = *I;
- switch (MI.getOpcode()) {
- default: break;
- case AMDGPU::SI_IF_NZ:
- pushExecMask(MBB, I);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_AND_B64),
- AMDGPU::EXEC)
- .addOperand(MI.getOperand(0)) // VCC
- .addReg(AMDGPU::EXEC);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_XOR_B64),
- PredicateStack.back())
- .addReg(PredicateStack.back())
- .addReg(AMDGPU::EXEC);
- MI.eraseFromParent();
- break;
- case AMDGPU::ELSE:
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B64),
- UnusedRegisters.back())
- .addReg(AMDGPU::EXEC);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B64),
- AMDGPU::EXEC)
- .addReg(PredicateStack.back());
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B64),
- PredicateStack.back())
- .addReg(UnusedRegisters.back());
- MI.eraseFromParent();
- break;
- case AMDGPU::ENDIF:
- popExecMask(MBB, I);
- if (MF.getInfo<SIMachineFunctionInfo>()->ShaderType == ShaderType::PIXEL &&
- PredicateStack.empty()) {
- // If the exec mask is non-zero, skip the next two instructions
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_CBRANCH_EXECNZ))
- .addImm(3)
- .addReg(AMDGPU::EXEC);
-
- // Exec mask is zero: Export to NULL target...
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::EXP))
- .addImm(0)
- .addImm(0x09) // V_008DFC_SQ_EXP_NULL
- .addImm(0)
- .addImm(1)
- .addImm(1)
- .addReg(AMDGPU::SREG_LIT_0)
- .addReg(AMDGPU::SREG_LIT_0)
- .addReg(AMDGPU::SREG_LIT_0)
- .addReg(AMDGPU::SREG_LIT_0);
-
- // ... and terminate wavefront
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_ENDPGM));
- }
- MI.eraseFromParent();
- break;
- }
- }
- }
- return false;
-}
-
-void SILowerFlowControlPass::pushExecMask(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) {
-
- assert(!UnusedRegisters.empty() && "Ran out of registers for predicate stack");
- unsigned StackReg = UnusedRegisters.back();
- UnusedRegisters.pop_back();
- PredicateStack.push_back(StackReg);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B64),
- StackReg)
- .addReg(AMDGPU::EXEC);
-}
-
-void SILowerFlowControlPass::popExecMask(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) {
- unsigned StackReg = PredicateStack.back();
- PredicateStack.pop_back();
- UnusedRegisters.push_back(StackReg);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::S_OR_B64),
- AMDGPU::EXEC)
- .addReg(AMDGPU::EXEC)
- .addReg(StackReg);
-}
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