[llvm-branch-commits] [llvm-branch] r117007 - in /llvm/branches/ggreif/peephole-infrastructure: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/and-tst-reg-peephole.ll

[Gabor Greif]

Author: ggreif
Date: Thu Oct 21 07:21:26 2010
New Revision: 117007

URL: http://llvm.org/viewvc/llvm-project?rev=117007&view=rev
Log:
also elide ARM TSTrr

Modified:
    llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll

Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117007&r1=117006&r2=117007&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Oct 21 07:21:26 2010
@@ -1344,7 +1344,7 @@
       return true;
     }
 
-    // Otherwise, pull as much of the immedidate into this ADDri/SUBri
+    // Otherwise, pull as much of the immediate into this ADDri/SUBri
     // as possible.
     unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
     unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
@@ -1470,33 +1470,33 @@
       optimizeWith<MaskRegOpportunity, &MaskRegOpportunity::FindCorrespondingAnd>();
   }
 
-    static bool IsAnd(int opcode) {
-        switch (opcode) {
-            case ARM::ANDrr:
-            case ARM::tAND:
-                return true;
-            default:
-                return false;
-        }
+  static MachineInstr *IsAnd(MachineInstr *MI) {
+    switch (MI->getOpcode()) {
+      case ARM::ANDrr:
+      case ARM::tAND:
+        return MI;
+      default:
+        return 0;
     }
+  }
 
-    template <unsigned MAX>
-    MachineInstr *findPrior(MachineInstr *CmpInstr) const {
-        MachineBasicBlock::iterator I(CmpInstr);
-        MachineBasicBlock::iterator BS = CmpInstr->getParent()->begin();
-        if (BS == I)
-            return 0;
-
-        unsigned iterations = MAX;
-        for (I = prior(I); iterations; --I, --iterations) {
-            if (MachineInstr *found = IsAnd(I->getOpcode()) ? I : 0) {
-                return found;
-            }
+  template <unsigned MAX>
+  MachineInstr *findPrior(MachineInstr *CmpInstr) const {
+    MachineBasicBlock::iterator I = CmpInstr;
+    MachineBasicBlock::iterator BS = CmpInstr->getParent()->begin();
+    if (I == BS)
+      return 0;
+
+    unsigned iterations = MAX;
+    for (I = prior(I); iterations; --I, --iterations) {
+      if (MachineInstr *found = IsAnd(I)) {
+        return found;
+      }
 
-            if (I == BS) break;
-        }
-        return 0;
+      if (I == BS) break;
     }
+    return 0;
+  }
 
   // Find an 'and' in close proximity.
   bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
@@ -1541,7 +1541,7 @@
     case ARM::t2ANDri:
       if (CmpMask != MI->getOperand(2).getImm())
         return false;
-      if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
+      if (SrcReg == MI->getOperand(CommonUse).getReg())
         return true;
       break;
     case ARM::COPY: {
@@ -1643,6 +1643,8 @@
   case ARM::ADDri:
   case ARM::ANDri:
   case ARM::t2ANDri:
+  case ARM::ANDrr:
+  case ARM::t2ANDrr:
   case ARM::SUBri:
   case ARM::t2ADDri:
   case ARM::t2SUBri:
@@ -1665,10 +1667,10 @@
                      MachineBasicBlock::iterator &MII) const {
 
     if (MachineInstr *AND = findPrior<5>(TST)) {
-        unsigned opNr1 = AND->getOpcode() == ARM::tAND ? 2 : 1;
+        unsigned op1Nr = AND->getOpcode() == ARM::tAND ? 2 : 1;
         // Check the case where both AND and TST use the same registers.
-        if (TST->getOperand(0).getReg() == AND->getOperand(opNr1).getReg() &&
-            TST->getOperand(1).getReg() == AND->getOperand(opNr1 + 1).getReg()){
+        if (TST->getOperand(0).getReg() == AND->getOperand(op1Nr).getReg() &&
+            TST->getOperand(1).getReg() == AND->getOperand(op1Nr + 1).getReg()){
             // Let the 'ANDrr' supply the condition codes.
             return Elide(TST, AND, MII);
         }

Modified: llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll?rev=117007&r1=117006&r2=117007&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll (original)
+++ llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll Thu Oct 21 07:21:26 2010
@@ -9,10 +9,12 @@
   %ptr = getelementptr %struct.Foo* %this, i32 0, i32 0
 	%my = load i32* %ptr
 
-; CHECK:      tst r0, r1
-; CHECK-NEXT: andne r0, r0, r1
+; CHECK:      ldr r0
+; CHECK-NEXT: ands r0, r0, r1
+; CHECK-NEXT: moveq r0, #255
 
-; THUMB:      ands r0, r1
+; THUMB:      ldr r0
+; THUMB-NEXT: ands r0, r1
 ; THUMB-NEXT: bne
 
 ; T2:      tst r0, r1