[llvm-branch-commits] [llvm-branch] r117006 - in /llvm/branches/ggreif/peephole-infrastructure: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/and-tst-reg-peephole.ll test/CodeGen/ARM/arm-and-tst-peephole.ll

[Gabor Greif]

Author: ggreif
Date: Thu Oct 21 06:42:06 2010
New Revision: 117006

URL: http://llvm.org/viewvc/llvm-project?rev=117006&view=rev
Log:
implement Thumb TST elim and (untested) (t2)TSTrr elim

Modified:
    llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll
    llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/arm-and-tst-peephole.ll

Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=117006&r1=117005&r2=117006&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Oct 21 06:42:06 2010
@@ -1439,8 +1439,12 @@
 }
 
 
+/// temporarily forward declare here (to avoid merge conflicts)
 bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
                      MachineBasicBlock::iterator &MII); //FIXME
+bool Elide(MachineInstr *CmpInstr, MachineInstr *MI,
+           MachineBasicBlock::iterator &MII);           //FIXME
+
 struct ImmCmpOpportunity : CmpOpportunity {
   int CmpValue;
   ImmCmpOpportunity(unsigned SrcReg) : CmpOpportunity(SrcReg), CmpValue(0) {
@@ -1459,6 +1463,47 @@
                             MachineBasicBlock::iterator &MII) const;
 };
 
+struct MaskRegOpportunity : CmpOpportunity {
+  int MaskReg;
+  MaskRegOpportunity(unsigned SrcReg, int MaskReg)
+    : CmpOpportunity(SrcReg), MaskReg(MaskReg) {
+      optimizeWith<MaskRegOpportunity, &MaskRegOpportunity::FindCorrespondingAnd>();
+  }
+
+    static bool IsAnd(int opcode) {
+        switch (opcode) {
+            case ARM::ANDrr:
+            case ARM::tAND:
+                return true;
+            default:
+                return false;
+        }
+    }
+
+    template <unsigned MAX>
+    MachineInstr *findPrior(MachineInstr *CmpInstr) const {
+        MachineBasicBlock::iterator I(CmpInstr);
+        MachineBasicBlock::iterator BS = CmpInstr->getParent()->begin();
+        if (BS == I)
+            return 0;
+
+        unsigned iterations = MAX;
+        for (I = prior(I); iterations; --I, --iterations) {
+            if (MachineInstr *found = IsAnd(I->getOpcode()) ? I : 0) {
+                return found;
+            }
+
+            if (I == BS) break;
+        }
+        return 0;
+    }
+
+  // Find an 'and' in close proximity.
+  bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
+                            const MachineRegisterInfo &MRI,
+                            MachineBasicBlock::iterator &MII) const;
+};
+
 bool ARMBaseInstrInfo::
 AnalyzeCompare(const MachineInstr *MI, CmpOpportunity& Opp) const {
   switch (MI->getOpcode()) {
@@ -1475,6 +1520,11 @@
   case ARM::t2TSTri:
     return new(Opp) MaskOpportunity(MI->getOperand(0).getReg(),
                                     MI->getOperand(1).getImm());
+  case ARM::TSTrr:
+  case ARM::tTST:
+  case ARM::t2TSTrr:
+    return new(Opp) MaskRegOpportunity(MI->getOperand(0).getReg(),
+                                       MI->getOperand(1).getReg());
   }
 
   return false;
@@ -1581,6 +1631,12 @@
       return false;
   }
 
+  return Elide(CmpInstr, MI, MII);
+}
+
+
+bool Elide(MachineInstr *CmpInstr, MachineInstr *MI,
+           MachineBasicBlock::iterator &MII) {
   // Set the "zero" bit in CPSR.
   switch (MI->getOpcode()) {
   default: break;
@@ -1593,6 +1649,8 @@
     MI->RemoveOperand(5);
     MachineInstrBuilder(MI)
       .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
+    // fall through
+  case ARM::tAND:
     MII = llvm::next(MachineBasicBlock::iterator(CmpInstr));
     CmpInstr->eraseFromParent();
     return true;
@@ -1601,6 +1659,26 @@
   return false;
 }
 
+bool MaskRegOpportunity::
+FindCorrespondingAnd(MachineInstr *TST, MachineInstr *MI,
+                     const MachineRegisterInfo&,
+                     MachineBasicBlock::iterator &MII) const {
+
+    if (MachineInstr *AND = findPrior<5>(TST)) {
+        unsigned opNr1 = AND->getOpcode() == ARM::tAND ? 2 : 1;
+        // Check the case where both AND and TST use the same registers.
+        if (TST->getOperand(0).getReg() == AND->getOperand(opNr1).getReg() &&
+            TST->getOperand(1).getReg() == AND->getOperand(opNr1 + 1).getReg()){
+            // Let the 'ANDrr' supply the condition codes.
+            return Elide(TST, AND, MII);
+        }
+    }
+
+    return false;
+}
+
+
+
 unsigned
 ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI,
                                  const InstrItineraryData *ItinData) const {

Modified: llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll?rev=117006&r1=117005&r2=117006&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll (original)
+++ llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/and-tst-reg-peephole.ll Thu Oct 21 06:42:06 2010
@@ -13,7 +13,7 @@
 ; CHECK-NEXT: andne r0, r0, r1
 
 ; THUMB:      ands r0, r1
-; THUMB-NEXT: tst r2, r1
+; THUMB-NEXT: bne
 
 ; T2:      tst r0, r1
 ; T2-NEXT: bne

Modified: llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=117006&r1=117005&r2=117006&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/arm-and-tst-peephole.ll Thu Oct 21 06:42:06 2010
@@ -22,9 +22,7 @@
 ; CHECK-NEXT: beq
 
 ; THUMB:      movs r5, #3
-; THUMB-NEXT: mov r6, r4
-; THUMB-NEXT: ands r6, r5
-; THUMB-NEXT: tst r4, r5
+; THUMB-NEXT: ands r5, r4
 ; THUMB-NEXT: beq
 
 ; T2:      ands r12, r12, #3