[llvm-branch-commits] [llvm-branch] r116924 - in /llvm/branches/ggreif/peephole-infrastructure: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Gabor Greif
ggreif at gmail.com
Wed Oct 20 07:40:20 PDT 2010
Author: ggreif
Date: Wed Oct 20 09:40:20 2010
New Revision: 116924
URL: http://llvm.org/viewvc/llvm-project?rev=116924&view=rev
Log:
introduce Oppotunity subclass for CMP instructions
Modified:
llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp
llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h
Modified: llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h?rev=116924&r1=116923&r2=116924&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h Wed Oct 20 09:40:20 2010
@@ -35,23 +35,39 @@
template<class T> class SmallVectorImpl;
+/// Opportunity - Base for all peephole opportunity descriptors
struct Opportunity {
- typedef bool (*DispatchFun)(const Opportunity&,
- MachineInstr *CmpInstr, MachineInstr *MI,
- const MachineRegisterInfo &MRI,
- MachineBasicBlock::iterator &MII);
- DispatchFun Dispatch;
- unsigned SrcReg;
Opportunity() {}
- Opportunity(unsigned SrcReg) : SrcReg(SrcReg) {}
void *operator new(size_t, Opportunity&);
};
+/// MaxOpportunity - Space reserved for Opportunity subclasses on stack
+/// @detail The intention is that MaxOpportunity provides sufficient space
+/// as an automatic variable on the stack and
+/// 'Opportunity::operator new' allocates the object in-place.
struct MaxOpportunity : Opportunity {
enum { SomeSufficientNumber = sizeof(void*) * 10 };
- char payload[SomeSufficientNumber];
+ char Payload[SomeSufficientNumber];
+
+ /// as - obtain space as any subclass
+ template <class SUB>
+ SUB &as() {
+ Opportunity &self(*this);
+ return static_cast<SUB&>(self);
+ }
};
+/// CmpOpportunity - Decribing opportunities for CMP(-like) instructions
+struct CmpOpportunity : Opportunity {
+ typedef bool (*DispatchFun)(const CmpOpportunity&, MachineInstr *CmpInstr,
+ MachineInstr *MI, const MachineRegisterInfo &MRI,
+ MachineBasicBlock::iterator &MII);
+ DispatchFun Dispatch;
+ unsigned SrcReg;
+ CmpOpportunity(unsigned SrcReg) : SrcReg(SrcReg) {}
+};
+
+
//---------------------------------------------------------------------------
///
/// TargetInstrInfo - Interface to description of machine instruction set
@@ -606,7 +622,7 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const {
+ virtual bool AnalyzeCompare(const MachineInstr*, CmpOpportunity&) const {
return false;
}
@@ -614,10 +630,10 @@
/// into something more efficient. E.g., on ARM most instructions can set the
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
- virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
- const Opportunity&,
- const MachineRegisterInfo *MRI,
- MachineBasicBlock::iterator &) const {
+ virtual bool OptimizeCompareInstr(MachineInstr*,
+ const CmpOpportunity&,
+ const MachineRegisterInfo*,
+ MachineBasicBlock::iterator&) const {
return false;
}
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp?rev=116924&r1=116923&r2=116924&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp Wed Oct 20 09:40:20 2010
@@ -240,15 +240,15 @@
bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI,
MachineBasicBlock *MBB,
MachineBasicBlock::iterator &NextIter){
- // If this instruction is a comparison against zero and isn't comparing a
- // physical register, we can try to optimize it. FIXME!
+ // Try to obtain an optimization opportunity.
MaxOpportunity Space;
- if (!TII->AnalyzeCompare(MI, Space) ||
- TargetRegisterInfo::isPhysicalRegister(Space.SrcReg))
+ CmpOpportunity &Opp = Space.as<CmpOpportunity>();
+ if (!TII->AnalyzeCompare(MI, Opp) ||
+ TargetRegisterInfo::isPhysicalRegister(Opp.SrcReg))
return false;
// Attempt to optimize the comparison instruction.
- if (TII->OptimizeCompareInstr(MI, Space, MRI, NextIter)) {
+ if (TII->OptimizeCompareInstr(MI, Opp, MRI, NextIter)) {
++NumEliminated;
return true;
}
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116924&r1=116923&r2=116924&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 20 09:40:20 2010
@@ -1441,19 +1441,22 @@
bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
MachineBasicBlock::iterator &MII); //FIXME
-struct ImmCmpOpportunity : Opportunity {
+struct ImmCmpOpportunity : CmpOpportunity {
int CmpValue;
- ImmCmpOpportunity(unsigned SrcReg) : Opportunity(SrcReg), CmpValue(0) { Dispatch = dispatch; }
- static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ ImmCmpOpportunity(unsigned SrcReg) : CmpOpportunity(SrcReg), CmpValue(0) { Dispatch = dispatch; }
+ static bool dispatch(const CmpOpportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
const MachineRegisterInfo&, MachineBasicBlock::iterator &MII) {
return ConvertAndElide(CmpInstr, MI, MII);
}
};
-struct MaskOpportunity : Opportunity {
+struct MaskOpportunity : CmpOpportunity {
int CmpMask;
- MaskOpportunity(unsigned SrcReg, int CmpMask) : Opportunity(SrcReg), CmpMask(CmpMask) { Dispatch = static_cast<DispatchFun>(dispatch); }
- static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ MaskOpportunity(unsigned SrcReg, int CmpMask)
+ : CmpOpportunity(SrcReg), CmpMask(CmpMask) {
+ Dispatch = static_cast<DispatchFun>(dispatch);
+ }
+ static bool dispatch(const CmpOpportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
const MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
return static_cast<const MaskOpportunity&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
}
@@ -1462,7 +1465,7 @@
};
bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, Opportunity& Opp) const {
+AnalyzeCompare(const MachineInstr *MI, CmpOpportunity& Opp) const {
switch (MI->getOpcode()) {
default: break;
case ARM::CMPri:
@@ -1515,17 +1518,11 @@
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity& Opp,
+OptimizeCompareInstr(MachineInstr *CmpInstr, const CmpOpportunity& Opp,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const {
-//<<<<<<< .working
-// MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
-// if (llvm::next(DI) != MRI->def_end())
-//=======
-// MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
MachineRegisterInfo::def_iterator DI = MRI->def_begin(Opp.SrcReg);
if (llvm::next(DI) != MRI->def_end())
-//>>>>>>> .merge-right.r116852
// Only support one definition.
return false;
@@ -1539,22 +1536,20 @@
const MachineRegisterInfo &MRI,
MachineBasicBlock::iterator &MII) const {
// Masked compares sometimes use the same register as the corresponding 'and'.
- // if (CmpMask != ~0) {
- if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
- MI = 0;
- for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
- UE = MRI.use_end(); UI != UE; ++UI) {
- if (UI->getParent() != CmpInstr->getParent()) continue;
- MachineInstr *PotentialAND = &*UI;
- if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
- continue;
- MI = PotentialAND;
- break;
- }
- if (!MI) return false;
+ if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
+ MI = 0;
+ for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
+ UE = MRI.use_end(); UI != UE; ++UI) {
+ if (UI->getParent() != CmpInstr->getParent()) continue;
+ MachineInstr *PotentialAND = &*UI;
+ if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
+ continue;
+ MI = PotentialAND;
+ break;
}
- // }
- return ConvertAndElide(CmpInstr, MI, MII);
+ if (!MI) return false;
+ }
+ return ConvertAndElide(CmpInstr, MI, MII);
}
bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h?rev=116924&r1=116923&r2=116924&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h Wed Oct 20 09:40:20 2010
@@ -334,11 +334,11 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const;
+ virtual bool AnalyzeCompare(const MachineInstr*, CmpOpportunity&) const;
/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero".
- virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity&,
+ virtual bool OptimizeCompareInstr(MachineInstr*, const CmpOpportunity&,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const;
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