[llvm-branch-commits] [llvm-branch] r116923 - in /llvm/branches/ggreif/peephole-infrastructure: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h test/CodeGen/ARM/2010-10-12-duplicated-cmp.ll
Gabor Greif
ggreif at gmail.com
Wed Oct 20 04:33:41 PDT 2010
Author: ggreif
Date: Wed Oct 20 06:33:41 2010
New Revision: 116923
URL: http://llvm.org/viewvc/llvm-project?rev=116923&view=rev
Log:
merge some parts from switch-opts branch, updated with new developments from trunk
Added:
llvm/branches/ggreif/peephole-infrastructure/test/CodeGen/ARM/2010-10-12-duplicated-cmp.ll
- copied unchanged from r116852, llvm/branches/ggreif/switch-opts/test/CodeGen/ARM/2010-10-12-duplicated-cmp.ll
Modified:
llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp
llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h
Modified: llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h?rev=116923&r1=116922&r2=116923&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/peephole-infrastructure/include/llvm/Target/TargetInstrInfo.h Wed Oct 20 06:33:41 2010
@@ -35,6 +35,22 @@
template<class T> class SmallVectorImpl;
+struct Opportunity {
+ typedef bool (*DispatchFun)(const Opportunity&,
+ MachineInstr *CmpInstr, MachineInstr *MI,
+ const MachineRegisterInfo &MRI,
+ MachineBasicBlock::iterator &MII);
+ DispatchFun Dispatch;
+ unsigned SrcReg;
+ Opportunity() {}
+ Opportunity(unsigned SrcReg) : SrcReg(SrcReg) {}
+ void *operator new(size_t, Opportunity&);
+};
+
+struct MaxOpportunity : Opportunity {
+ enum { SomeSufficientNumber = sizeof(void*) * 10 };
+ char payload[SomeSufficientNumber];
+};
//---------------------------------------------------------------------------
///
@@ -590,8 +606,7 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI,
- unsigned &SrcReg, int &Mask, int &Value) const {
+ virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const {
return false;
}
@@ -600,7 +615,7 @@
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
- unsigned SrcReg, int Mask, int Value,
+ const Opportunity&,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &) const {
return false;
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp?rev=116923&r1=116922&r2=116923&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/CodeGen/PeepholeOptimizer.cpp Wed Oct 20 06:33:41 2010
@@ -241,15 +241,14 @@
MachineBasicBlock *MBB,
MachineBasicBlock::iterator &NextIter){
// If this instruction is a comparison against zero and isn't comparing a
- // physical register, we can try to optimize it.
- unsigned SrcReg;
- int CmpMask, CmpValue;
- if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
- TargetRegisterInfo::isPhysicalRegister(SrcReg))
+ // physical register, we can try to optimize it. FIXME!
+ MaxOpportunity Space;
+ if (!TII->AnalyzeCompare(MI, Space) ||
+ TargetRegisterInfo::isPhysicalRegister(Space.SrcReg))
return false;
// Attempt to optimize the comparison instruction.
- if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI, NextIter)) {
+ if (TII->OptimizeCompareInstr(MI, Space, MRI, NextIter)) {
++NumEliminated;
return true;
}
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=116923&r1=116922&r2=116923&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 20 06:33:41 2010
@@ -1432,25 +1432,51 @@
return Offset == 0;
}
+
+void *llvm::Opportunity::operator new(size_t need, Opportunity& space) {
+ assert(need <= sizeof(MaxOpportunity));
+ return &space;
+}
+
+
+bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineBasicBlock::iterator &MII); //FIXME
+struct ImmCmpOpportunity : Opportunity {
+ int CmpValue;
+ ImmCmpOpportunity(unsigned SrcReg) : Opportunity(SrcReg), CmpValue(0) { Dispatch = dispatch; }
+ static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ const MachineRegisterInfo&, MachineBasicBlock::iterator &MII) {
+ return ConvertAndElide(CmpInstr, MI, MII);
+ }
+};
+
+struct MaskOpportunity : Opportunity {
+ int CmpMask;
+ MaskOpportunity(unsigned SrcReg, int CmpMask) : Opportunity(SrcReg), CmpMask(CmpMask) { Dispatch = static_cast<DispatchFun>(dispatch); }
+ static bool dispatch(const Opportunity& self, MachineInstr *CmpInstr, MachineInstr *MI,
+ const MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) {
+ return static_cast<const MaskOpportunity&>(self).FindCorrespondingAnd(CmpInstr, MI, MRI, MII);
+ }
+ bool FindCorrespondingAnd(MachineInstr *CmpInstr, MachineInstr *MI,
+ const MachineRegisterInfo &MRI, MachineBasicBlock::iterator &MII) const;
+};
+
bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
- int &CmpValue) const {
+AnalyzeCompare(const MachineInstr *MI, Opportunity& Opp) const {
switch (MI->getOpcode()) {
default: break;
case ARM::CMPri:
case ARM::CMPzri:
case ARM::t2CMPri:
- case ARM::t2CMPzri:
- SrcReg = MI->getOperand(0).getReg();
- CmpMask = ~0;
- CmpValue = MI->getOperand(1).getImm();
- return true;
+ case ARM::t2CMPzri: {
+ int CmpValue = MI->getOperand(1).getImm();
+ return CmpValue == 0 &&
+ new(Opp) ImmCmpOpportunity(MI->getOperand(0).getReg());
+ }
case ARM::TSTri:
case ARM::t2TSTri:
- SrcReg = MI->getOperand(0).getReg();
- CmpMask = MI->getOperand(1).getImm();
- CmpValue = 0;
- return true;
+ return new(Opp) MaskOpportunity(MI->getOperand(0).getReg(),
+ MI->getOperand(1).getImm());
}
return false;
@@ -1489,25 +1515,35 @@
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
- int CmpValue, const MachineRegisterInfo *MRI,
+OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity& Opp,
+ const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const {
- if (CmpValue != 0)
- return false;
-
- MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
+//<<<<<<< .working
+// MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
+// if (llvm::next(DI) != MRI->def_end())
+//=======
+// MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo();
+ MachineRegisterInfo::def_iterator DI = MRI->def_begin(Opp.SrcReg);
if (llvm::next(DI) != MRI->def_end())
+//>>>>>>> .merge-right.r116852
// Only support one definition.
return false;
MachineInstr *MI = &*DI;
+ return Opp.Dispatch(Opp, CmpInstr, MI, *MRI, MII);
+}
+bool
+MaskOpportunity::FindCorrespondingAnd(MachineInstr *CmpInstr,
+ MachineInstr *MI,
+ const MachineRegisterInfo &MRI,
+ MachineBasicBlock::iterator &MII) const {
// Masked compares sometimes use the same register as the corresponding 'and'.
- if (CmpMask != ~0) {
+ // if (CmpMask != ~0) {
if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
MI = 0;
- for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
- UE = MRI->use_end(); UI != UE; ++UI) {
+ for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
+ UE = MRI.use_end(); UI != UE; ++UI) {
if (UI->getParent() != CmpInstr->getParent()) continue;
MachineInstr *PotentialAND = &*UI;
if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
@@ -1517,8 +1553,12 @@
}
if (!MI) return false;
}
- }
+ // }
+ return ConvertAndElide(CmpInstr, MI, MII);
+}
+bool ConvertAndElide(MachineInstr *CmpInstr, MachineInstr *MI,
+ MachineBasicBlock::iterator &MII) {
// Conservatively refuse to convert an instruction which isn't in the same BB
// as the comparison.
if (MI->getParent() != CmpInstr->getParent())
Modified: llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h?rev=116923&r1=116922&r2=116923&view=diff
==============================================================================
--- llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/peephole-infrastructure/lib/Target/ARM/ARMBaseInstrInfo.h Wed Oct 20 06:33:41 2010
@@ -334,13 +334,11 @@
/// AnalyzeCompare - For a comparison instruction, return the source register
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
- virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
- int &CmpMask, int &CmpValue) const;
+ virtual bool AnalyzeCompare(const MachineInstr *MI, Opportunity&) const;
/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero".
- virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
- int CmpMask, int CmpValue,
+ virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, const Opportunity&,
const MachineRegisterInfo *MRI,
MachineBasicBlock::iterator &MII) const;
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