[llvm-branch-commits] [llvm-branch] r109963 [1/2] - in /llvm/branches/wendling/eh: ./ autoconf/ docs/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter2/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ModuleMaker/ examples/ParallelJIT/ include/llvm-c/ include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/Comp...
Bill Wendling
isanbard at gmail.com
Sat Jul 31 17:59:05 PDT 2010
Author: void
Date: Sat Jul 31 19:59:02 2010
New Revision: 109963
URL: http://llvm.org/viewvc/llvm-project?rev=109963&view=rev
Log:
Update to ToT.
Added:
llvm/branches/wendling/eh/include/llvm/ADT/NullablePtr.h
- copied unchanged from r109962, llvm/trunk/include/llvm/ADT/NullablePtr.h
llvm/branches/wendling/eh/include/llvm/Analysis/RegionInfo.h
- copied unchanged from r109962, llvm/trunk/include/llvm/Analysis/RegionInfo.h
llvm/branches/wendling/eh/include/llvm/Analysis/RegionIterator.h
- copied unchanged from r109962, llvm/trunk/include/llvm/Analysis/RegionIterator.h
llvm/branches/wendling/eh/include/llvm/Analysis/RegionPrinter.h
- copied unchanged from r109962, llvm/trunk/include/llvm/Analysis/RegionPrinter.h
llvm/branches/wendling/eh/include/llvm/MC/MCDwarf.h
- copied unchanged from r109962, llvm/trunk/include/llvm/MC/MCDwarf.h
llvm/branches/wendling/eh/include/llvm/PassRegistry.h
- copied unchanged from r109962, llvm/trunk/include/llvm/PassRegistry.h
llvm/branches/wendling/eh/include/llvm/Support/CrashRecoveryContext.h
- copied unchanged from r109962, llvm/trunk/include/llvm/Support/CrashRecoveryContext.h
llvm/branches/wendling/eh/lib/Analysis/RegionInfo.cpp
- copied unchanged from r109962, llvm/trunk/lib/Analysis/RegionInfo.cpp
llvm/branches/wendling/eh/lib/Analysis/RegionPrinter.cpp
- copied unchanged from r109962, llvm/trunk/lib/Analysis/RegionPrinter.cpp
llvm/branches/wendling/eh/lib/CodeGen/RenderMachineFunction.cpp
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp
llvm/branches/wendling/eh/lib/CodeGen/RenderMachineFunction.h
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/RenderMachineFunction.h
llvm/branches/wendling/eh/lib/CodeGen/SplitKit.cpp
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/SplitKit.cpp
llvm/branches/wendling/eh/lib/CodeGen/SplitKit.h
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/SplitKit.h
llvm/branches/wendling/eh/lib/CodeGen/Splitter.cpp
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/Splitter.cpp
llvm/branches/wendling/eh/lib/CodeGen/Splitter.h
- copied unchanged from r109962, llvm/trunk/lib/CodeGen/Splitter.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/ (props changed)
- copied from r109962, llvm/trunk/lib/MC/MCDisassembler/
llvm/branches/wendling/eh/lib/MC/MCDisassembler/CMakeLists.txt
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDDisassembler.cpp
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDDisassembler.h
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDInfo.h
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDInfo.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDInst.cpp
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDInst.cpp
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDInst.h
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDInst.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDOperand.cpp
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDOperand.h
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDOperand.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDToken.cpp
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDToken.cpp
llvm/branches/wendling/eh/lib/MC/MCDisassembler/EDToken.h
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/EDToken.h
llvm/branches/wendling/eh/lib/MC/MCDisassembler/Makefile
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDisassembler/Makefile
llvm/branches/wendling/eh/lib/MC/MCDwarf.cpp
- copied unchanged from r109962, llvm/trunk/lib/MC/MCDwarf.cpp
llvm/branches/wendling/eh/lib/Support/CrashRecoveryContext.cpp
- copied unchanged from r109962, llvm/trunk/lib/Support/CrashRecoveryContext.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMAsmPrinter.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMFastISel.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMGlobalMerge.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMMCInstLower.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMMCInstLower.h
- copied unchanged from r109962, llvm/trunk/lib/Target/ARM/ARMMCInstLower.h
llvm/branches/wendling/eh/lib/Target/X86/X86AsmPrinter.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86AsmPrinter.h
- copied unchanged from r109962, llvm/trunk/lib/Target/X86/X86AsmPrinter.h
llvm/branches/wendling/eh/lib/Target/X86/X86InstrFMA.td
- copied unchanged from r109962, llvm/trunk/lib/Target/X86/X86InstrFMA.td
llvm/branches/wendling/eh/lib/Target/X86/X86MCInstLower.cpp
- copied unchanged from r109962, llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86MCInstLower.h
- copied unchanged from r109962, llvm/trunk/lib/Target/X86/X86MCInstLower.h
llvm/branches/wendling/eh/lib/VMCore/PassRegistry.cpp
- copied unchanged from r109962, llvm/trunk/lib/VMCore/PassRegistry.cpp
llvm/branches/wendling/eh/test/Analysis/RegionInfo/ (props changed)
- copied from r109962, llvm/trunk/test/Analysis/RegionInfo/
llvm/branches/wendling/eh/test/Analysis/RegionInfo/block_sort.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/block_sort.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/cond_loop.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/cond_loop.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/condition_complicated.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/condition_complicated.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/condition_complicated_2.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/condition_complicated_2.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/condition_forward_edge.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/condition_forward_edge.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/condition_same_exit.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/condition_same_exit.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/condition_simple.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/condition_simple.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/dg.exp
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/dg.exp
llvm/branches/wendling/eh/test/Analysis/RegionInfo/exit_in_condition.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/exit_in_condition.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/infinite_loop.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/infinite_loop.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/infinite_loop_2.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/infinite_loop_2.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/infinite_loop_3.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/infinite_loop_3.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/infinite_loop_4.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/infinite_loop_4.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/loop_with_condition.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/loop_with_condition.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/loops_1.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/loops_1.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/loops_2.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/loops_2.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/mix_1.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/mix_1.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/multiple_exiting_edge.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/multiple_exiting_edge.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/nested_loops.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/nested_loops.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/next.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/next.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/paper.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/paper.ll
llvm/branches/wendling/eh/test/Analysis/RegionInfo/two_loops_same_header.ll
- copied unchanged from r109962, llvm/trunk/test/Analysis/RegionInfo/two_loops_same_header.ll
llvm/branches/wendling/eh/test/Assembler/align-inst-alloca.ll
- copied unchanged from r109962, llvm/trunk/test/Assembler/align-inst-alloca.ll
llvm/branches/wendling/eh/test/Assembler/align-inst-load.ll
- copied unchanged from r109962, llvm/trunk/test/Assembler/align-inst-load.ll
llvm/branches/wendling/eh/test/Assembler/align-inst-store.ll
- copied unchanged from r109962, llvm/trunk/test/Assembler/align-inst-store.ll
llvm/branches/wendling/eh/test/Assembler/align-inst.ll
- copied unchanged from r109962, llvm/trunk/test/Assembler/align-inst.ll
llvm/branches/wendling/eh/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll
llvm/branches/wendling/eh/test/CodeGen/ARM/bfi.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/ARM/bfi.ll
llvm/branches/wendling/eh/test/CodeGen/ARM/fast-isel.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/ARM/fast-isel.ll
llvm/branches/wendling/eh/test/CodeGen/Generic/2010-07-27-DAGCombineCrash.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Generic/2010-07-27-DAGCombineCrash.ll
llvm/branches/wendling/eh/test/CodeGen/Mips/2010-07-20-Select.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
llvm/branches/wendling/eh/test/CodeGen/Mips/2010-07-20-Switch.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Mips/2010-07-20-Switch.ll
llvm/branches/wendling/eh/test/CodeGen/PowerPC/empty-functions.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/bfi.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Thumb2/bfi.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/machine-licm-vdup.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-badreg-operands.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/Thumb2/thumb2-badreg-operands.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2010-07-15-Crash.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
llvm/branches/wendling/eh/test/CodeGen/X86/barrier-sse.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/barrier-sse.ll
llvm/branches/wendling/eh/test/CodeGen/X86/barrier.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/barrier.ll
llvm/branches/wendling/eh/test/CodeGen/X86/empty-functions.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/empty-functions.ll
llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-atomic.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/fast-isel-atomic.ll
llvm/branches/wendling/eh/test/CodeGen/X86/lsr-i386.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/lsr-i386.ll
llvm/branches/wendling/eh/test/CodeGen/X86/lsr-normalization.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/lsr-normalization.ll
llvm/branches/wendling/eh/test/CodeGen/X86/shl-anyext.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/shl-anyext.ll
llvm/branches/wendling/eh/test/CodeGen/X86/vec_shift4.ll
- copied unchanged from r109962, llvm/trunk/test/CodeGen/X86/vec_shift4.ll
llvm/branches/wendling/eh/test/DebugInfo/2010-07-19-Crash.ll
- copied unchanged from r109962, llvm/trunk/test/DebugInfo/2010-07-19-Crash.ll
llvm/branches/wendling/eh/test/FrontendC++/2010-07-19-nowarn.cpp
- copied unchanged from r109962, llvm/trunk/test/FrontendC++/2010-07-19-nowarn.cpp
llvm/branches/wendling/eh/test/FrontendC++/2010-07-23-DeclLoc.cpp
- copied unchanged from r109962, llvm/trunk/test/FrontendC++/2010-07-23-DeclLoc.cpp
llvm/branches/wendling/eh/test/FrontendC/2010-07-27-MinNoFoldConst.c
- copied unchanged from r109962, llvm/trunk/test/FrontendC/2010-07-27-MinNoFoldConst.c
llvm/branches/wendling/eh/test/FrontendC/vla-2.c
- copied unchanged from r109962, llvm/trunk/test/FrontendC/vla-2.c
llvm/branches/wendling/eh/test/MC/AsmParser/ELF/ (props changed)
- copied from r109962, llvm/trunk/test/MC/AsmParser/ELF/
llvm/branches/wendling/eh/test/MC/AsmParser/ELF/dg.exp
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/ELF/dg.exp
llvm/branches/wendling/eh/test/MC/AsmParser/ELF/directive_section.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/ELF/directive_section.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-avx-clmul-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-clmul-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-avx-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-fma3-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_32-fma3-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-avx-clmul-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-clmul-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-avx-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-fma3-encoding.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/X86/x86_64-fma3-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/directive_elf_size.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/directive_elf_size.s
llvm/branches/wendling/eh/test/MC/AsmParser/macro-def-in-instantiation.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s
llvm/branches/wendling/eh/test/MC/AsmParser/macros-parsing.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/macros-parsing.s
llvm/branches/wendling/eh/test/MC/AsmParser/macros.s
- copied unchanged from r109962, llvm/trunk/test/MC/AsmParser/macros.s
llvm/branches/wendling/eh/test/MC/COFF/
- copied from r109962, llvm/trunk/test/MC/COFF/
llvm/branches/wendling/eh/test/MC/COFF/basic-coff.ll
- copied unchanged from r109962, llvm/trunk/test/MC/COFF/basic-coff.ll
llvm/branches/wendling/eh/test/MC/COFF/dg.exp
- copied unchanged from r109962, llvm/trunk/test/MC/COFF/dg.exp
llvm/branches/wendling/eh/test/Scripts/coff-dump.py
- copied unchanged from r109962, llvm/trunk/test/Scripts/coff-dump.py
llvm/branches/wendling/eh/test/Scripts/coff-dump.py.bat
- copied unchanged from r109962, llvm/trunk/test/Scripts/coff-dump.py.bat
llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/uglygep.ll
- copied unchanged from r109962, llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll
llvm/branches/wendling/eh/test/Transforms/InstCombine/2010-07-19-sqrt.ll
- copied unchanged from r109962, llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll
llvm/branches/wendling/eh/test/Transforms/LoopSimplify/2010-07-15-IncorrectDomFrontierUpdate.ll
- copied unchanged from r109962, llvm/trunk/test/Transforms/LoopSimplify/2010-07-15-IncorrectDomFrontierUpdate.ll
llvm/branches/wendling/eh/test/Transforms/MergeFunc/vectors-and-arrays.ll
- copied unchanged from r109962, llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll
llvm/branches/wendling/eh/tools/llvm-diff/ (props changed)
- copied from r109962, llvm/trunk/tools/llvm-diff/
llvm/branches/wendling/eh/tools/llvm-diff/CMakeLists.txt
- copied unchanged from r109962, llvm/trunk/tools/llvm-diff/CMakeLists.txt
llvm/branches/wendling/eh/tools/llvm-diff/DifferenceEngine.cpp
- copied unchanged from r109962, llvm/trunk/tools/llvm-diff/DifferenceEngine.cpp
llvm/branches/wendling/eh/tools/llvm-diff/DifferenceEngine.h
- copied unchanged from r109962, llvm/trunk/tools/llvm-diff/DifferenceEngine.h
llvm/branches/wendling/eh/tools/llvm-diff/Makefile
- copied unchanged from r109962, llvm/trunk/tools/llvm-diff/Makefile
llvm/branches/wendling/eh/tools/llvm-diff/llvm-diff.cpp
- copied unchanged from r109962, llvm/trunk/tools/llvm-diff/llvm-diff.cpp
llvm/branches/wendling/eh/unittests/Support/Casting.cpp
- copied unchanged from r109962, llvm/trunk/unittests/Support/Casting.cpp
llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/required-and-missing.c
- copied unchanged from r109962, llvm/trunk/utils/lit/lit/ExampleTests/required-and-missing.c
llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/required-and-present.c
- copied unchanged from r109962, llvm/trunk/utils/lit/lit/ExampleTests/required-and-present.c
Removed:
llvm/branches/wendling/eh/include/llvm/MC/MCParser/AsmParser.h
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.h
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.h
llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPointRegKill.cpp
llvm/branches/wendling/eh/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2007-06-14-branchfold.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
llvm/branches/wendling/eh/tools/edis/EDDisassembler.cpp
llvm/branches/wendling/eh/tools/edis/EDDisassembler.h
llvm/branches/wendling/eh/tools/edis/EDInfo.td
llvm/branches/wendling/eh/tools/edis/EDInst.cpp
llvm/branches/wendling/eh/tools/edis/EDInst.h
llvm/branches/wendling/eh/tools/edis/EDOperand.cpp
llvm/branches/wendling/eh/tools/edis/EDOperand.h
llvm/branches/wendling/eh/tools/edis/EDToken.cpp
llvm/branches/wendling/eh/tools/edis/EDToken.h
Modified:
llvm/branches/wendling/eh/ (props changed)
llvm/branches/wendling/eh/CMakeLists.txt
llvm/branches/wendling/eh/CREDITS.TXT
llvm/branches/wendling/eh/Makefile
llvm/branches/wendling/eh/Makefile.rules
llvm/branches/wendling/eh/README.txt
llvm/branches/wendling/eh/autoconf/configure.ac
llvm/branches/wendling/eh/configure
llvm/branches/wendling/eh/docs/LangRef.html
llvm/branches/wendling/eh/docs/MakefileGuide.html
llvm/branches/wendling/eh/docs/Passes.html
llvm/branches/wendling/eh/docs/ReleaseNotes.html
llvm/branches/wendling/eh/docs/WritingAnLLVMBackend.html
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llvm/branches/wendling/eh/include/llvm/ADT/DenseSet.h
llvm/branches/wendling/eh/include/llvm/ADT/ScopedHashTable.h
llvm/branches/wendling/eh/include/llvm/ADT/StringMap.h
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llvm/branches/wendling/eh/include/llvm/ADT/ValueMap.h
llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h
llvm/branches/wendling/eh/include/llvm/Analysis/Dominators.h
llvm/branches/wendling/eh/include/llvm/Analysis/LazyValueInfo.h
llvm/branches/wendling/eh/include/llvm/Analysis/LibCallAliasAnalysis.h
llvm/branches/wendling/eh/include/llvm/Analysis/LoopInfo.h
llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolution.h
llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpander.h
llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpressions.h
llvm/branches/wendling/eh/include/llvm/CodeGen/AsmPrinter.h
llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h
llvm/branches/wendling/eh/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h
llvm/branches/wendling/eh/include/llvm/CodeGen/MachineModuleInfo.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SchedulerRegistry.h
llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h
llvm/branches/wendling/eh/include/llvm/CompilerDriver/Action.h
llvm/branches/wendling/eh/include/llvm/CompilerDriver/Common.td
llvm/branches/wendling/eh/include/llvm/CompilerDriver/CompilationGraph.h
llvm/branches/wendling/eh/include/llvm/CompilerDriver/Error.h
llvm/branches/wendling/eh/include/llvm/CompilerDriver/Plugin.h
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llvm/branches/wendling/eh/include/llvm/MC/MCContext.h
llvm/branches/wendling/eh/include/llvm/MC/MCObjectStreamer.h
llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParser.h
llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParserExtension.h
llvm/branches/wendling/eh/include/llvm/MC/MCStreamer.h
llvm/branches/wendling/eh/include/llvm/Metadata.h
llvm/branches/wendling/eh/include/llvm/Module.h
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llvm/branches/wendling/eh/include/llvm/Support/COFF.h
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llvm/branches/wendling/eh/include/llvm/Support/StandardPasses.h
llvm/branches/wendling/eh/include/llvm/System/ThreadLocal.h
llvm/branches/wendling/eh/include/llvm/Target/Target.td
llvm/branches/wendling/eh/include/llvm/Target/TargetAsmParser.h
llvm/branches/wendling/eh/include/llvm/Target/TargetInstrDesc.h
llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h
llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h
llvm/branches/wendling/eh/include/llvm/Target/TargetMachine.h
llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h
llvm/branches/wendling/eh/include/llvm/Target/TargetOptions.h
llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h
llvm/branches/wendling/eh/include/llvm/Target/TargetRegistry.h
llvm/branches/wendling/eh/include/llvm/Transforms/IPO.h
llvm/branches/wendling/eh/include/llvm/Use.h
llvm/branches/wendling/eh/include/llvm/Value.h
llvm/branches/wendling/eh/include/llvm/ValueSymbolTable.h
llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisCounter.cpp
llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp
llvm/branches/wendling/eh/lib/Analysis/AliasDebugger.cpp
llvm/branches/wendling/eh/lib/Analysis/AliasSetTracker.cpp
llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp
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llvm/branches/wendling/eh/lib/Analysis/CMakeLists.txt
llvm/branches/wendling/eh/lib/Analysis/CaptureTracking.cpp
llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp
llvm/branches/wendling/eh/lib/Analysis/DbgInfoPrinter.cpp
llvm/branches/wendling/eh/lib/Analysis/DebugInfo.cpp
llvm/branches/wendling/eh/lib/Analysis/DomPrinter.cpp
llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraph.cpp
llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraphSCCPass.cpp
llvm/branches/wendling/eh/lib/Analysis/IPA/FindUsedTypes.cpp
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llvm/branches/wendling/eh/lib/Analysis/InlineCost.cpp
llvm/branches/wendling/eh/lib/Analysis/InstCount.cpp
llvm/branches/wendling/eh/lib/Analysis/InstructionSimplify.cpp
llvm/branches/wendling/eh/lib/Analysis/IntervalPartition.cpp
llvm/branches/wendling/eh/lib/Analysis/LazyValueInfo.cpp
llvm/branches/wendling/eh/lib/Analysis/LibCallAliasAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/Lint.cpp
llvm/branches/wendling/eh/lib/Analysis/LiveValues.cpp
llvm/branches/wendling/eh/lib/Analysis/LoopDependenceAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/LoopInfo.cpp
llvm/branches/wendling/eh/lib/Analysis/MemoryDependenceAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/ModuleDebugInfoPrinter.cpp
llvm/branches/wendling/eh/lib/Analysis/PointerTracking.cpp
llvm/branches/wendling/eh/lib/Analysis/PostDominators.cpp
llvm/branches/wendling/eh/lib/Analysis/ProfileInfo.cpp
llvm/branches/wendling/eh/lib/Analysis/ProfileVerifierPass.cpp
llvm/branches/wendling/eh/lib/Analysis/ScalarEvolution.cpp
llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionExpander.cpp
llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionNormalization.cpp
llvm/branches/wendling/eh/lib/AsmParser/LLParser.cpp
llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.cpp
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llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp
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llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.h
llvm/branches/wendling/eh/lib/CodeGen/Analysis.cpp
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
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llvm/branches/wendling/eh/lib/CodeGen/DeadMachineInstructionElim.cpp
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llvm/branches/wendling/eh/lib/CodeGen/ELFCodeEmitter.cpp
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llvm/branches/wendling/eh/lib/CodeGen/GCMetadata.cpp
llvm/branches/wendling/eh/lib/CodeGen/GCStrategy.cpp
llvm/branches/wendling/eh/lib/CodeGen/IfConversion.cpp
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llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveInterval.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveStackAnalysis.cpp
llvm/branches/wendling/eh/lib/CodeGen/LiveVariables.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp
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llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
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llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp
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llvm/branches/wendling/eh/lib/CodeGen/RegAllocPBQP.cpp
llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
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llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
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llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp
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llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
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llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.h
llvm/branches/wendling/eh/lib/CodeGen/VirtRegRewriter.cpp
llvm/branches/wendling/eh/lib/CompilerDriver/Action.cpp
llvm/branches/wendling/eh/lib/CompilerDriver/CompilationGraph.cpp
llvm/branches/wendling/eh/lib/CompilerDriver/Main.cpp
llvm/branches/wendling/eh/lib/CompilerDriver/Makefile
llvm/branches/wendling/eh/lib/CompilerDriver/Plugin.cpp
llvm/branches/wendling/eh/lib/ExecutionEngine/ExecutionEngineBindings.cpp
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JIT.cpp
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITEmitter.cpp
llvm/branches/wendling/eh/lib/Linker/LinkModules.cpp
llvm/branches/wendling/eh/lib/MC/CMakeLists.txt
llvm/branches/wendling/eh/lib/MC/MCAsmStreamer.cpp
llvm/branches/wendling/eh/lib/MC/MCAssembler.cpp
llvm/branches/wendling/eh/lib/MC/MCContext.cpp
llvm/branches/wendling/eh/lib/MC/MCMachOStreamer.cpp
llvm/branches/wendling/eh/lib/MC/MCObjectStreamer.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/AsmParser.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/DarwinAsmParser.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/MCAsmParser.cpp
llvm/branches/wendling/eh/lib/MC/MCParser/TargetAsmParser.cpp
llvm/branches/wendling/eh/lib/MC/MCStreamer.cpp
llvm/branches/wendling/eh/lib/MC/Makefile
llvm/branches/wendling/eh/lib/MC/WinCOFFObjectWriter.cpp
llvm/branches/wendling/eh/lib/MC/WinCOFFStreamer.cpp
llvm/branches/wendling/eh/lib/Support/CMakeLists.txt
llvm/branches/wendling/eh/lib/System/ThreadLocal.cpp
llvm/branches/wendling/eh/lib/System/Unix/ThreadLocal.inc
llvm/branches/wendling/eh/lib/System/Win32/ThreadLocal.inc
llvm/branches/wendling/eh/lib/Target/ARM/ARM.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMRegisterInfo.td
llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.h
llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/ARM/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
llvm/branches/wendling/eh/lib/Target/ARM/Makefile
llvm/branches/wendling/eh/lib/Target/ARM/README.txt
llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm/branches/wendling/eh/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.h
llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.cpp
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llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.h
llvm/branches/wendling/eh/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430BranchSelector.cpp
llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.cpp
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llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.h
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16.h
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.h
llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/PIC16Overlay.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.h
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.td
llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.h
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZRegisterInfo.h
llvm/branches/wendling/eh/lib/Target/TargetData.cpp
llvm/branches/wendling/eh/lib/Target/TargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
llvm/branches/wendling/eh/lib/Target/X86/CMakeLists.txt
llvm/branches/wendling/eh/lib/Target/X86/README-FPStack.txt
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llvm/branches/wendling/eh/lib/Target/X86/X86.h
llvm/branches/wendling/eh/lib/Target/X86/X86.td
llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86CodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPoint.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h
llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrFPStack.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h
llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrMMX.td
llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.h
llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.td
llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.cpp
llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.h
llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp
llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.cpp
llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.h
llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp
llvm/branches/wendling/eh/lib/Transforms/Hello/Hello.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/ArgumentPromotion.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/ConstantMerge.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/DeadArgumentElimination.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/DeadTypeElimination.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalDCE.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalOpt.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/IPConstantPropagation.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/InlineAlways.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/InlineSimple.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/Inliner.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/Internalize.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/LoopExtractor.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/LowerSetJmp.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/PartialInlining.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/PartialSpecialization.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/PruneEH.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/StripDeadPrototypes.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/StripSymbols.cpp
llvm/branches/wendling/eh/lib/Transforms/IPO/StructRetPromotion.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCalls.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCasts.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/branches/wendling/eh/lib/Transforms/Instrumentation/EdgeProfiling.cpp
llvm/branches/wendling/eh/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/ABCD.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/ADCE.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/BasicBlockPlacement.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/CodeGenPrepare.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/ConstantProp.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/DCE.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/GEPSplitter.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/GVN.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/IndVarSimplify.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/JumpThreading.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LICM.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopDeletion.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopIndexSplit.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopRotation.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnrollPass.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnswitch.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/MemCpyOptimizer.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/Reassociate.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/SCCP.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyCFGPass.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyLibCalls.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/Sink.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/TailDuplication.cpp
llvm/branches/wendling/eh/lib/Transforms/Scalar/TailRecursionElimination.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/BasicInliner.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/BreakCriticalEdges.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/BuildLibCalls.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/CloneFunction.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/CloneModule.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/InlineFunction.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/LCSSA.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/Local.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/LoopSimplify.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/LoopUnroll.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/SSI.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/branches/wendling/eh/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
llvm/branches/wendling/eh/lib/VMCore/AutoUpgrade.cpp
llvm/branches/wendling/eh/lib/VMCore/CMakeLists.txt
llvm/branches/wendling/eh/lib/VMCore/Constants.cpp
llvm/branches/wendling/eh/lib/VMCore/ConstantsContext.h
llvm/branches/wendling/eh/lib/VMCore/Core.cpp
llvm/branches/wendling/eh/lib/VMCore/Dominators.cpp
llvm/branches/wendling/eh/lib/VMCore/Globals.cpp
llvm/branches/wendling/eh/lib/VMCore/InlineAsm.cpp
llvm/branches/wendling/eh/lib/VMCore/Instruction.cpp
llvm/branches/wendling/eh/lib/VMCore/Instructions.cpp
llvm/branches/wendling/eh/lib/VMCore/LLVMContext.cpp
llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp
llvm/branches/wendling/eh/lib/VMCore/Module.cpp
llvm/branches/wendling/eh/lib/VMCore/Pass.cpp
llvm/branches/wendling/eh/lib/VMCore/PrintModulePass.cpp
llvm/branches/wendling/eh/lib/VMCore/Type.cpp
llvm/branches/wendling/eh/lib/VMCore/TypesContext.h
llvm/branches/wendling/eh/lib/VMCore/Use.cpp
llvm/branches/wendling/eh/lib/VMCore/Value.cpp
llvm/branches/wendling/eh/lib/VMCore/ValueSymbolTable.cpp
llvm/branches/wendling/eh/lib/VMCore/Verifier.cpp
llvm/branches/wendling/eh/test/CodeGen/ARM/arguments.ll
llvm/branches/wendling/eh/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
llvm/branches/wendling/eh/test/CodeGen/CellSPU/call_indirect.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-and2.ll
llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-uxtb.ll
llvm/branches/wendling/eh/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
llvm/branches/wendling/eh/test/CodeGen/X86/fabs.ll
llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-gep.ll
llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-shift-imm.ll
llvm/branches/wendling/eh/test/CodeGen/X86/global-sections.ll
llvm/branches/wendling/eh/test/CodeGen/X86/sse-minmax.ll
llvm/branches/wendling/eh/test/Feature/NamedMDNode.ll
llvm/branches/wendling/eh/test/FrontendC++/2009-07-15-LineNumbers.cpp
llvm/branches/wendling/eh/test/FrontendC/vla-1.c
llvm/branches/wendling/eh/test/FrontendObjC/2009-08-17-DebugInfo.m
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-new-encoder.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-new-encoder.s
llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_instructions.s
llvm/branches/wendling/eh/test/MC/AsmParser/directive_abort.s
llvm/branches/wendling/eh/test/MC/Disassembler/neon-tests.txt
llvm/branches/wendling/eh/test/Makefile
llvm/branches/wendling/eh/test/Other/inline-asm-newline-terminator.ll
llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/crash.ll
llvm/branches/wendling/eh/test/Transforms/JumpThreading/crash.ll
llvm/branches/wendling/eh/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll
llvm/branches/wendling/eh/tools/Makefile
llvm/branches/wendling/eh/tools/bugpoint/BugDriver.cpp
llvm/branches/wendling/eh/tools/bugpoint/BugDriver.h
llvm/branches/wendling/eh/tools/bugpoint/CrashDebugger.cpp
llvm/branches/wendling/eh/tools/bugpoint/ExecutionDriver.cpp
llvm/branches/wendling/eh/tools/bugpoint/ExtractFunction.cpp
llvm/branches/wendling/eh/tools/bugpoint/FindBugs.cpp
llvm/branches/wendling/eh/tools/bugpoint/Miscompilation.cpp
llvm/branches/wendling/eh/tools/bugpoint/OptimizerDriver.cpp
llvm/branches/wendling/eh/tools/bugpoint/ToolRunner.cpp
llvm/branches/wendling/eh/tools/edis/CMakeLists.txt
llvm/branches/wendling/eh/tools/edis/EDMain.cpp
llvm/branches/wendling/eh/tools/edis/Makefile
llvm/branches/wendling/eh/tools/llc/llc.cpp
llvm/branches/wendling/eh/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
llvm/branches/wendling/eh/tools/llvm-mc/CMakeLists.txt
llvm/branches/wendling/eh/tools/llvm-mc/Disassembler.cpp
llvm/branches/wendling/eh/tools/llvm-mc/Makefile
llvm/branches/wendling/eh/tools/llvm-mc/llvm-mc.cpp
llvm/branches/wendling/eh/tools/llvm-shlib/Makefile
llvm/branches/wendling/eh/tools/llvmc/Makefile
llvm/branches/wendling/eh/tools/llvmc/doc/LLVMC-Reference.rst
llvm/branches/wendling/eh/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp
llvm/branches/wendling/eh/tools/lto/Makefile
llvm/branches/wendling/eh/tools/opt/AnalysisWrappers.cpp
llvm/branches/wendling/eh/unittests/ADT/ValueMapTest.cpp
llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/JITTest.cpp
llvm/branches/wendling/eh/unittests/VMCore/DerivedTypesTest.cpp
llvm/branches/wendling/eh/unittests/VMCore/MetadataTest.cpp
llvm/branches/wendling/eh/utils/TableGen/AsmMatcherEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/AsmWriterEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.cpp
llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.h
llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp
llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/EDEmitter.h
llvm/branches/wendling/eh/utils/TableGen/FastISelEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/InstrInfoEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/LLVMCConfigurationEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/NeonEmitter.cpp
llvm/branches/wendling/eh/utils/TableGen/TableGen.cpp
llvm/branches/wendling/eh/utils/buildit/GNUmakefile
llvm/branches/wendling/eh/utils/buildit/build_llvm
llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/lit.cfg
llvm/branches/wendling/eh/utils/lit/lit/TestRunner.py
llvm/branches/wendling/eh/utils/lit/lit/TestingConfig.py
llvm/branches/wendling/eh/utils/valgrind/i386-pc-linux-gnu.supp
llvm/branches/wendling/eh/utils/valgrind/x86_64-pc-linux-gnu.supp
llvm/branches/wendling/eh/utils/vim/llvm.vim
Propchange: llvm/branches/wendling/eh/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Jul 31 19:59:02 2010
@@ -1 +1 @@
-/llvm/trunk:104459-108393
+/llvm/trunk:104459-109962
Modified: llvm/branches/wendling/eh/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -308,6 +308,7 @@
add_subdirectory(lib/Analysis/IPA)
add_subdirectory(lib/MC)
add_subdirectory(lib/MC/MCParser)
+add_subdirectory(lib/MC/MCDisassembler)
add_subdirectory(test)
add_subdirectory(utils/FileCheck)
Modified: llvm/branches/wendling/eh/CREDITS.TXT
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/CREDITS.TXT?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/CREDITS.TXT (original)
+++ llvm/branches/wendling/eh/CREDITS.TXT Sat Jul 31 19:59:02 2010
@@ -134,6 +134,11 @@
E: ggreif at gmail.com
D: Improvements for space efficiency
+N: James Grosbach
+E: grosbach at apple.com
+D: SjLj exception handling support
+D: General fixes and improvements for the ARM back-end
+
N: Lang Hames
E: lhames at gmail.com
D: PBQP-based register allocator
@@ -277,6 +282,11 @@
E: deeppatel1987 at gmail.com
D: ARM calling conventions rewrite, hard float support
+N: Wesley Peck
+E: peckw at wesleypeck.com
+W: http://wesleypeck.com/
+D: MicroBlaze backend
+
N: Vladimir Prus
W: http://vladimir_prus.blogspot.com
E: ghost at cs.msu.su
@@ -306,6 +316,10 @@
E: ashukla at cs.uiuc.edu
D: The `paths' pass
+N: Michael J. Spencer
+E: bigcheesegs at gmail.com
+D: Shepherding Windows COFF support into MC.
+
N: Reid Spencer
E: rspencer at reidspencer.com
W: http://reidspencer.com/
@@ -329,14 +343,9 @@
D: Cmake dependency chain and various bug fixes
N: Bill Wendling
-E: isanbard at gmail.com
+E: wendling at apple.com
D: Bunches of stuff
N: Bob Wilson
E: bob.wilson at acm.org
D: Advanced SIMD (NEON) support in the ARM backend
-
-N: Wesley Peck
-E: peckw at wesleypeck.com
-W: http://wesleypeck.com/
-D: MicroBlaze backend
Modified: llvm/branches/wendling/eh/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/Makefile (original)
+++ llvm/branches/wendling/eh/Makefile Sat Jul 31 19:59:02 2010
@@ -64,7 +64,8 @@
ifeq ($(MAKECMDGOALS),install-clang)
DIRS := tools/clang/tools/driver tools/clang/lib/Headers \
- tools/clang/runtime tools/clang/docs
+ tools/clang/runtime tools/clang/docs \
+ tools/lto
OPTIONAL_DIRS :=
NO_INSTALL = 1
endif
@@ -78,7 +79,8 @@
endif
ifeq ($(MAKECMDGOALS),clang-only)
- DIRS := $(filter-out tools runtime docs unittests, $(DIRS)) tools/clang
+ DIRS := $(filter-out tools runtime docs unittests, $(DIRS)) \
+ tools/clang tools/lto
OPTIONAL_DIRS :=
endif
@@ -110,7 +112,8 @@
--host=$(BUILD_TRIPLE) --target=$(BUILD_TRIPLE); \
cd .. ; \
fi; \
- ($(MAKE) -C BuildTools \
+ (unset SDKROOT; \
+ $(MAKE) -C BuildTools \
BUILD_DIRS_ONLY=1 \
UNIVERSAL= \
ENABLE_OPTIMIZED=$(ENABLE_OPTIMIZED) \
Modified: llvm/branches/wendling/eh/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/Makefile.rules?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/Makefile.rules (original)
+++ llvm/branches/wendling/eh/Makefile.rules Sat Jul 31 19:59:02 2010
@@ -203,7 +203,6 @@
LIBRARYNAME := $(patsubst %,plugin_llvmc_%,$(LLVMC_PLUGIN))
CPP.Flags += -DLLVMC_PLUGIN_NAME=$(LLVMC_PLUGIN)
-REQUIRES_EH := 1
ifeq ($(ENABLE_LLVMC_DYNAMIC),1)
LD.Flags += -lCompilerDriver
@@ -226,8 +225,6 @@
TOOLNAME = $(LLVMC_BASED_DRIVER)
-REQUIRES_EH := 1
-
ifeq ($(ENABLE_LLVMC_DYNAMIC),1)
LD.Flags += -lCompilerDriver
else
@@ -621,8 +618,7 @@
endif
# Adjust linker flags for building an executable
-ifneq ($(HOST_OS),Darwin)
-ifneq ($(DARWIN_MAJVERS),4)
+ifneq ($(HOST_OS), $(filter $(HOST_OS), Darwin Cygwin MingW))
ifdef TOOLNAME
LD.Flags += $(RPATH) -Wl,'$$ORIGIN/../lib'
ifdef EXAMPLE_TOOL
@@ -631,9 +627,13 @@
LD.Flags += $(RPATH) -Wl,$(ToolDir) $(RDYNAMIC)
endif
endif
+else
+ifneq ($(DARWIN_MAJVERS),4)
+ LD.Flags += $(RPATH) -Wl, at executable_path/../lib
endif
endif
+
#----------------------------------------------------------
# Options To Invoke Tools
#----------------------------------------------------------
@@ -1125,12 +1125,12 @@
endif
$(LibName.SO): $(ObjectsO) $(ProjLibsPaths) $(LLVMLibsPaths) $(LibDir)/.dir
$(Echo) Linking $(BuildMode) $(SharedLibKindMessage) \
- $(LIBRARYNAME)$(SHLIBEXT)
+ $(notdir $@)
$(Verb) $(Link) $(SharedLinkOptions) -o $@ $(ObjectsO) \
$(ProjLibsOptions) $(LLVMLibsOptions) $(LIBS)
else
$(LibName.SO): $(ObjectsO) $(LibDir)/.dir
- $(Echo) Linking $(BuildMode) Shared Library $(basename $@)
+ $(Echo) Linking $(BuildMode) Shared Library $(notdir $@)
$(Verb) $(Link) $(SharedLinkOptions) -o $@ $(ObjectsO)
endif
@@ -1336,10 +1336,33 @@
endif
ifeq ($(HOST_OS), $(filter $(HOST_OS), Linux NetBSD FreeBSD))
+ifneq ($(ARCH), Mips)
LD.Flags += -Wl,--version-script=$(LLVM_SRC_ROOT)/autoconf/ExportMap.map
endif
endif
+endif
+#---------------------------------------------------------
+# Tool Version Info Support
+#---------------------------------------------------------
+
+ifeq ($(HOST_OS),Darwin)
+ifdef TOOL_INFO_PLIST
+
+LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST)
+
+$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST)
+
+$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in $(ObjDir)/.dir
+ $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..."
+ $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \
+ -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \
+ -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \
+ -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \
+ $< > $@
+
+endif
+endif
#---------------------------------------------------------
# Provide targets for building the tools
Modified: llvm/branches/wendling/eh/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/README.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/README.txt (original)
+++ llvm/branches/wendling/eh/README.txt Sat Jul 31 19:59:02 2010
@@ -1,4 +1,4 @@
-Low Level Virtual Machine (LLVM)
+\Low Level Virtual Machine (LLVM)
================================
This directory and its subdirectories contain source code for the Low Level
@@ -13,3 +13,4 @@
If you're writing a package for LLVM, see docs/Packaging.html for our
suggestions.
+
Modified: llvm/branches/wendling/eh/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/autoconf/configure.ac?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/autoconf/configure.ac (original)
+++ llvm/branches/wendling/eh/autoconf/configure.ac Sat Jul 31 19:59:02 2010
@@ -1011,6 +1011,13 @@
dnl Find the install program
AC_PROG_INSTALL
+dnl Prepend src dir to install path dir if it's a relative path
+dnl This is a hack for installs that take place in something other
+dnl than the top level.
+case "$INSTALL" in
+ [[\\/$]]* | ?:[[\\/]]* ) ;;
+ *) INSTALL="\\\$(TOPSRCDIR)/$INSTALL" ;;
+esac
dnl Checks for documentation and testing tools that we can do without. If these
dnl are not found then they are set to "true" which always succeeds but does
@@ -1287,6 +1294,9 @@
dnl Try to find Darwin specific crash reporting library.
AC_CHECK_HEADERS([CrashReporterClient.h])
+dnl Try to find Darwin specific linker-section library.
+AC_CHECK_HEADERS([mach-o/getsect.h])
+
dnl===-----------------------------------------------------------------------===
dnl===
dnl=== SECTION 7: Check for types and structures
@@ -1345,6 +1355,9 @@
dnl atomic builtins are required for threading support.
AC_MSG_CHECKING(for GCC atomic builtins)
+dnl Since we'll be using these atomic builtins in C++ files we should test
+dnl the C++ compiler.
+AC_LANG_PUSH([C++])
AC_LINK_IFELSE(
AC_LANG_SOURCE(
[[int main() {
@@ -1356,12 +1369,29 @@
return 0;
}
]]),
+ AC_LANG_POP([C++])
AC_MSG_RESULT(yes)
AC_DEFINE(LLVM_MULTITHREADED, 1, Build multithreading support into LLVM),
AC_MSG_RESULT(no)
AC_DEFINE(LLVM_MULTITHREADED, 0, Build multithreading support into LLVM)
AC_MSG_WARN([LLVM will be built thread-unsafe because atomic builtins are missing]))
+dnl Check for Darwin-specific getsect().
+AC_MSG_CHECKING(for getsect())
+AC_COMPILE_IFELSE(
+ AC_LANG_SOURCE(
+ [[#include <mach-o/getsect.h>
+ int main() {
+ unsigned long p;
+ return (int)getsect("__DATA","__pass_info", &p);
+ }
+ ]]),
+ AC_MSG_RESULT(yes)
+ AC_DEFINE(HAVE_GETSECT, 1, Have Darwin getsect() support),
+ AC_MSG_RESULT(no)
+ AC_DEFINE(HAVE_GETSECT, 1, Have Darwin getsect() support)
+)
+
dnl===-----------------------------------------------------------------------===
dnl===
Modified: llvm/branches/wendling/eh/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/configure?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/configure (original)
+++ llvm/branches/wendling/eh/configure Sat Jul 31 19:59:02 2010
@@ -8004,6 +8004,10 @@
test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+case "$INSTALL" in
+ [\\/$]* | ?:[\\/]* ) ;;
+ *) INSTALL="\\\$(TOPSRCDIR)/$INSTALL" ;;
+esac
# Extract the first word of "bzip2", so it can be a program name with args.
set dummy bzip2; ac_word=$2
@@ -11387,7 +11391,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 11390 "configure"
+#line 11394 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -17120,6 +17124,176 @@
+for ac_header in mach-o/getsect.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+ { echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+ac_res=`eval echo '${'$as_ac_Header'}'`
+ { echo "$as_me:$LINENO: result: $ac_res" >&5
+echo "${ECHO_T}$ac_res" >&6; }
+else
+ # Is the header compilable?
+{ echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_compile") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_compiler=no
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+{ echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6; }
+
+# Is the header present?
+{ echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (ac_try="$ac_cpp conftest.$ac_ext"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+
+rm -f conftest.err conftest.$ac_ext
+{ echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6; }
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ ( cat <<\_ASBOX
+## ----------------------------------- ##
+## Report this to llvmbugs at cs.uiuc.edu ##
+## ----------------------------------- ##
+_ASBOX
+ ) | sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+{ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; }
+if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+ac_res=`eval echo '${'$as_ac_Header'}'`
+ { echo "$as_me:$LINENO: result: $ac_res" >&5
+echo "${ECHO_T}$ac_res" >&6; }
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
{ echo "$as_me:$LINENO: checking for HUGE_VAL sanity" >&5
@@ -19991,6 +20165,12 @@
{ echo "$as_me:$LINENO: checking for GCC atomic builtins" >&5
echo $ECHO_N "checking for GCC atomic builtins... $ECHO_C" >&6; }
+ac_ext=cpp
+ac_cpp='$CXXCPP $CPPFLAGS'
+ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
+
cat >conftest.$ac_ext <<_ACEOF
/* confdefs.h. */
_ACEOF
@@ -20041,6 +20221,12 @@
ac_status=$?
echo "$as_me:$LINENO: \$? = $ac_status" >&5
(exit $ac_status); }; }; then
+ ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
{ echo "$as_me:$LINENO: result: yes" >&5
echo "${ECHO_T}yes" >&6; }
@@ -20066,6 +20252,78 @@
rm -f core conftest.err conftest.$ac_objext \
conftest$ac_exeext conftest.$ac_ext
+{ echo "$as_me:$LINENO: checking for getsect()" >&5
+echo $ECHO_N "checking for getsect()... $ECHO_C" >&6; }
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <mach-o/getsect.h>
+ int main() {
+ unsigned long p;
+ return (int)getsect("__DATA","__pass_info", &p);
+ }
+
+_ACEOF
+rm -f conftest.$ac_objext
+if { (ac_try="$ac_compile"
+case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_compile") 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (case "(($ac_try" in
+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+ *) ac_try_echo=$ac_try;;
+esac
+eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
+ (eval "$ac_try") 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ { echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6; }
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_GETSECT 1
+_ACEOF
+
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ { echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6; }
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_GETSECT 1
+_ACEOF
+
+
+fi
+
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
if test "$llvm_cv_os_type" = "Linux" -a "$llvm_cv_target_arch" = "x86_64" ; then
Modified: llvm/branches/wendling/eh/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/LangRef.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/LangRef.html (original)
+++ llvm/branches/wendling/eh/docs/LangRef.html Sat Jul 31 19:59:02 2010
@@ -949,15 +949,17 @@
<div class="doc_text">
<p>Named metadata is a collection of metadata. <a href="#metadata">Metadata
- nodes</a> (but not metadata strings) and null are the only valid operands for
+ nodes</a> (but not metadata strings) are the only valid operands for
a named metadata.</p>
<h5>Syntax:</h5>
<pre class="doc_code">
-; An unnamed metadata node, which is referenced by the named metadata.
+; Some unnamed metadata nodes, which are referenced by the named metadata.
+!0 = metadata !{metadata !"zero"}
!1 = metadata !{metadata !"one"}
+!2 = metadata !{metadata !"two"}
; A named metadata.
-!name = !{null, !1}
+!name = !{!0, !1, !2}
</pre>
</div>
@@ -6125,8 +6127,8 @@
<h5>Syntax:</h5>
<p>This is an overloaded intrinsic. You can use llvm.memset on any integer bit
- width and for different address spaces. Not all targets support all bit
- widths however.</p>
+ width and for different address spaces. However, not all targets support all
+ bit widths.</p>
<pre>
declare void @llvm.memset.p0i8.i32(i8* <dest>, i8 <val>,
@@ -6140,14 +6142,14 @@
particular byte value.</p>
<p>Note that, unlike the standard libc function, the <tt>llvm.memset</tt>
- intrinsic does not return a value, takes extra alignment/volatile arguments,
- and the destination can be in an arbitrary address space.</p>
+ intrinsic does not return a value and takes extra alignment/volatile
+ arguments. Also, the destination can be in an arbitrary address space.</p>
<h5>Arguments:</h5>
<p>The first argument is a pointer to the destination to fill, the second is the
- byte value to fill it with, the third argument is an integer argument
+ byte value with which to fill it, the third argument is an integer argument
specifying the number of bytes to fill, and the fourth argument is the known
- alignment of destination location.</p>
+ alignment of the destination location.</p>
<p>If the call to this intrinsic has an alignment value that is not 0 or 1,
then the caller guarantees that the destination pointer is aligned to that
Modified: llvm/branches/wendling/eh/docs/MakefileGuide.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/MakefileGuide.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/MakefileGuide.html (original)
+++ llvm/branches/wendling/eh/docs/MakefileGuide.html Sat Jul 31 19:59:02 2010
@@ -785,6 +785,9 @@
not.</dd>
<dt><a name="PROJ_SRC_DIR"><tt>PROJ_SRC_DIR</tt></a></dt>
<dd>The directory which contains the source files to be built.</dd>
+ <dt><a name="BUILD_EXAMPLES"><tt>BUILD_EXAMPLES</tt></a></dt>
+ <dd>If set to 1, build examples in <tt>examples</tt> and (if building
+ Clang) <tt>tools/clang/examples</tt> directories.</dd>
<dt><a name="BZIP2"><tt>BZIP2</tt></a><small>(configured)</small></dt>
<dd>The path to the <tt>bzip2</tt> tool.</dd>
<dt><a name="CC"><tt>CC</tt></a><small>(configured)</small></dt>
Modified: llvm/branches/wendling/eh/docs/Passes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/Passes.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/Passes.html (original)
+++ llvm/branches/wendling/eh/docs/Passes.html Sat Jul 31 19:59:02 2010
@@ -120,6 +120,7 @@
<tr><td><a href="#print-used-types">-print-used-types</a></td><td>Find Used Types</td></tr>
<tr><td><a href="#profile-estimator">-profile-estimator</a></td><td>Estimate profiling information</td></tr>
<tr><td><a href="#profile-loader">-profile-loader</a></td><td>Load profile information from llvmprof.out</td></tr>
+<tr><td><a href="#regions">-regions</a></td><td>Detect single entry single exit regions in a function</td></tr>
<tr><td><a href="#profile-verifier">-profile-verifier</a></td><td>Verify profiling information</td></tr>
<tr><td><a href="#scalar-evolution">-scalar-evolution</a></td><td>Scalar Evolution Analysis</td></tr>
<tr><td><a href="#scev-aa">-scev-aa</a></td><td>ScalarEvolution-based Alias Analysis</td></tr>
@@ -771,6 +772,17 @@
<div class="doc_text">
<p>Pass that checks profiling information for plausibility.</p>
</div>
+<div class="doc_subsection">
+ <a name="regions">-regions: Detect single entry single exit regions in a function</a>
+</div>
+<div class="doc_text">
+ <p>
+ The <code>RegionInfo</code> pass detects single entry single exit regions in a
+ function, where a region is defined as any subgraph that is connected to the
+ remaining graph at only two spots. Furthermore, an hierarchical region tree is
+ built.
+ </p>
+</div>
<!-------------------------------------------------------------------------- -->
<div class="doc_subsection">
Modified: llvm/branches/wendling/eh/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/ReleaseNotes.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/ReleaseNotes.html (original)
+++ llvm/branches/wendling/eh/docs/ReleaseNotes.html Sat Jul 31 19:59:02 2010
@@ -118,40 +118,9 @@
integrating with other development tools. Clang is considered a
production-quality compiler for C and Objective-C on x86 (32- and 64-bit).</p>
-<p>In the LLVM 2.7 time-frame, the Clang team has made many improvements:</p>
+<p>In the LLVM 2.8 time-frame, the Clang team has made many improvements:</p>
<ul>
-
-<li>C++ Support: Clang is now capable of self-hosting! While still
-alpha-quality, Clang's C++ support has matured enough to build LLVM and Clang,
-and C++ is now enabled by default. See the <a
-href="http://clang.llvm.org/cxx_compatibility.html">Clang C++ compatibility
-page</a> for common C++ migration issues.</li>
-
-<li>Objective-C: Clang now includes experimental support for an updated
-Objective-C ABI on non-Darwin platforms. This includes support for non-fragile
-instance variables and accelerated proxies, as well as greater potential for
-future optimisations. The new ABI is used when compiling with the
--fobjc-nonfragile-abi and -fgnu-runtime options. Code compiled with these
-options may be mixed with code compiled with GCC or clang using the old GNU ABI,
-but requires the libobjc2 runtime from the GNUstep project.</li>
-
-<li>New warnings: Clang contains a number of new warnings, including
-control-flow warnings (unreachable code, missing return statements in a
-non-<code>void</code> function, etc.), sign-comparison warnings, and improved
-format-string warnings.</li>
-
-<li>CIndex API and Python bindings: Clang now includes a C API as part of the
-CIndex library. Although we may make some changes to the API in the future, it
-is intended to be stable and has been designed for use by external projects. See
-the Clang
-doxygen <a href="http://clang.llvm.org/doxygen/group__CINDEX.html">CIndex</a>
-documentation for more details. The CIndex API also includes a preliminary
-set of Python bindings.</li>
-
-<li>ARM Support: Clang now has ABI support for both the Darwin and Linux ARM
-ABIs. Coupled with many improvements to the LLVM ARM backend, Clang is now
-suitable for use as a beta quality ARM compiler.</li>
</ul>
</div>
@@ -170,10 +139,7 @@
future</a>!). The tool is very good at finding bugs that occur on specific
paths through code, such as on error conditions.</p>
-<p>In the LLVM 2.7 time-frame, the analyzer core has made several major and
- minor improvements, including better support for tracking the fields of
- structures, initial support (not enabled by default yet) for doing
- interprocedural (cross-function) analysis, and new checks have been added.
+<p>In the LLVM 2.8 time-frame,
</p>
</div>
@@ -190,26 +156,8 @@
implementation of the CLI) using LLVM for static and just-in-time
compilation.</p>
-<p>
-With the release of LLVM 2.7, VMKit has shifted to a great framework for writing
-virtual machines. VMKit now offers precise and efficient garbage collection with
-multi-threading support, thanks to the MMTk memory management toolkit, as well
-as just in time and ahead of time compilation with LLVM. The major changes in
-VMKit 0.27 are:</p>
-
-<ul>
+<p>With the release of LLVM 2.8, ...</p>
-<li>Garbage collection: VMKit now uses the MMTk toolkit for garbage collectors.
- The first collector to be ported is the MarkSweep collector, which is precise,
- and drastically improves the performance of VMKit.</li>
-<li>Line number information in the JVM: by using the debug metadata of LLVM, the
- JVM now supports precise line number information, useful when printing a stack
- trace.</li>
-<li>Interface calls in the JVM: we implemented a variant of the Interface Method
- Table technique for interface calls in the JVM.
-</li>
-
-</ul>
</div>
@@ -231,8 +179,10 @@
<p>
All of the code in the compiler-rt project is available under the standard LLVM
-License, a "BSD-style" license. New in LLVM 2.7: compiler_rt now
-supports ARM targets.</p>
+License, a "BSD-style" license. New in LLVM 2.8:
+
+Soft float support
+</p>
</div>
@@ -265,7 +215,7 @@
</p>
<p>
-DragonEgg is a new project which is seeing its first release with llvm-2.7.
+2.8 status here.
</p>
</div>
@@ -288,23 +238,13 @@
LLVM MC Project Blog Post</a>.
</p>
-<p>2.7 includes major parts of the work required by the new MC Project. A few
- targets have been refactored to support it, and work is underway to support a
- native assembler in LLVM. This work is not complete in LLVM 2.7, but it has
- made substantially more progress on LLVM mainline.</p>
-
-<p>One minor example of what MC can do is to transcode an AT&T syntax
- X86 .s file into intel syntax. You can do this with something like:</p>
-<pre>
- llvm-mc foo.s -output-asm-variant=1 -o foo-intel.s
-</pre>
-
+<p>2.8 status here</p>
</div>
<!-- *********************************************************************** -->
<div class="doc_section">
- <a name="externalproj">External Open Source Projects Using LLVM 2.7</a>
+ <a name="externalproj">External Open Source Projects Using LLVM 2.8</a>
</div>
<!-- *********************************************************************** -->
@@ -312,171 +252,13 @@
<p>An exciting aspect of LLVM is that it is used as an enabling technology for
a lot of other language and tools projects. This section lists some of the
- projects that have already been updated to work with LLVM 2.7.</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="pure">Pure</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://pure-lang.googlecode.com/">Pure</a>
-is an algebraic/functional programming language based on term rewriting.
-Programs are collections of equations which are used to evaluate expressions in
-a symbolic fashion. Pure offers dynamic typing, eager and lazy evaluation,
-lexical closures, a hygienic macro system (also based on term rewriting),
-built-in list and matrix support (including list and matrix comprehensions) and
-an easy-to-use C interface. The interpreter uses LLVM as a backend to
- JIT-compile Pure programs to fast native code.</p>
-
-<p>Pure versions 0.43 and later have been tested and are known to work with
-LLVM 2.7 (and continue to work with older LLVM releases >= 2.5).</p>
-
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="RoadsendPHP">Roadsend PHP</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://code.roadsend.com/rphp">Roadsend PHP</a> (rphp) is an open
-source implementation of the PHP programming
-language that uses LLVM for its optimizer, JIT and static compiler. This is a
-reimplementation of an earlier project that is now based on LLVM.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="UnladenSwallow">Unladen Swallow</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://code.google.com/p/unladen-swallow/">Unladen Swallow</a> is a
-branch of <a href="http://python.org/">Python</a> intended to be fully
-compatible and significantly faster. It uses LLVM's optimization passes and JIT
-compiler.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="tce">TTA-based Codesign Environment (TCE)</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://tce.cs.tut.fi/">TCE</a> is a toolset for designing
-application-specific processors (ASP) based on the Transport triggered
-architecture (TTA). The toolset provides a complete co-design flow from C/C++
-programs down to synthesizable VHDL and parallel program binaries. Processor
-customization points include the register files, function units, supported
-operations, and the interconnection network.</p>
-
-<p>TCE uses llvm-gcc/Clang and LLVM for C/C++ language support, target
-independent optimizations and also for parts of code generation. It generates
-new LLVM-based code generators "on the fly" for the designed TTA processors and
-loads them in to the compiler backend as runtime libraries to avoid per-target
-recompilation of larger parts of the compiler chain.</p>
-
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="safecode">SAFECode Compiler</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://safecode.cs.illinois.edu">SAFECode</a> is a memory safe C
-compiler built using LLVM. It takes standard, unannotated C code, analyzes the
-code to ensure that memory accesses and array indexing operations are safe, and
-instruments the code with run-time checks when safety cannot be proven
-statically.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="icedtea">IcedTea Java Virtual Machine Implementation</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://icedtea.classpath.org/wiki/Main_Page">IcedTea</a> provides a
-harness to build OpenJDK using only free software build tools and to provide
-replacements for the not-yet free parts of OpenJDK. One of the extensions that
-IcedTea provides is a new JIT compiler named <a
-href="http://icedtea.classpath.org/wiki/ZeroSharkFaq">Shark</a> which uses LLVM
-to provide native code generation without introducing processor-dependent
-code.
-</p>
-<p>Icedtea6 1.8 and later have been tested and are known to work with
-LLVM 2.7 (and continue to work with older LLVM releases >= 2.6 as well).
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="llvm-lua">LLVM-Lua</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://code.google.com/p/llvm-lua/">LLVM-Lua</a> uses LLVM
- to add JIT and static compiling support to the Lua VM. Lua
-bytecode is analyzed to remove type checks, then LLVM is used to compile the
-bytecode down to machine code.
-</p>
-<p>LLVM-Lua 1.2.0 have been tested and is known to work with LLVM 2.7.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="MacRuby">MacRuby</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://macruby.org">MacRuby</a> is an implementation of Ruby based on
-core Mac OS technologies, sponsored by Apple Inc. It uses LLVM at runtime for
-optimization passes, JIT compilation and exception handling. It also allows
-static (ahead-of-time) compilation of Ruby code straight to machine code.
-</p>
-<p>The upcoming MacRuby 0.6 release works with LLVM 2.7.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="GHC">Glasgow Haskell Compiler (GHC)</a>
-</div>
-
-<div class="doc_text">
-<p>
-<a href="http://www.haskell.org/ghc/">GHC</a> is an open source,
-state-of-the-art programming suite for Haskell, a standard lazy
-functional programming language. It includes an optimizing static
-compiler generating good code for a variety of platforms, together
-with an interactive system for convenient, quick development.</p>
-
-<p>In addition to the existing C and native code generators, GHC now
-supports an <a
-href="http://hackage.haskell.org/trac/ghc/wiki/Commentary/Compiler/Backends/LLVM">LLVM
-code generator</a>. GHC supports LLVM 2.7.</p>
-
+ projects that have already been updated to work with LLVM 2.8.</p>
</div>
<!-- *********************************************************************** -->
<div class="doc_section">
- <a name="whatsnew">What's New in LLVM 2.7?</a>
+ <a name="whatsnew">What's New in LLVM 2.8?</a>
</div>
<!-- *********************************************************************** -->
@@ -496,29 +278,11 @@
<div class="doc_text">
-<p>In addition to changes to the code, between LLVM 2.6 and 2.7, a number of
+<p>In addition to changes to the code, between LLVM 2.7 and 2.8, a number of
organization changes have happened:
</p>
<ul>
-<li>LLVM has a new <a href="http://llvm.org/Logo.html">official logo</a>!</li>
-
-<li>Ted Kremenek and Doug Gregor have stepped forward as <a
- href="http://llvm.org/docs/DeveloperPolicy.html#owners">Code Owners</a> of the
- Clang static analyzer and the Clang frontend, respectively.</li>
-
-<li>LLVM now has an <a href="http://blog.llvm.org">official Blog</a> at
- <a href="http://blog.llvm.org">http://blog.llvm.org</a>. This is a great way
- to learn about new LLVM-related features as they are implemented. Several
- features in this release are already explained on the blog.</li>
-
-<li>The LLVM web pages are now checked into the SVN server, in the "www",
- "www-pubs" and "www-releases" SVN modules. Previously they were hidden in a
- largely inaccessible old CVS server.</li>
-
-<li><a href="http://llvm.org">llvm.org</a> is now hosted on a new (and much
- faster) server. It is still graciously hosted at the University of Illinois
- of Urbana Champaign.</li>
</ul>
</div>
@@ -529,43 +293,10 @@
<div class="doc_text">
-<p>LLVM 2.7 includes several major new capabilities:</p>
+<p>LLVM 2.8 includes several major new capabilities:</p>
<ul>
-<li>2.7 includes initial support for the <a
- href="http://en.wikipedia.org/wiki/MicroBlaze">MicroBlaze</a> target.
- MicroBlaze is a soft processor core designed for Xilinx FPGAs.</li>
-
-<li>2.7 includes a new LLVM IR "extensible metadata" feature. This feature
- supports many different use cases, including allowing front-end authors to
- encode source level information into LLVM IR, which is consumed by later
- language-specific passes. This is a great way to do high-level optimizations
- like devirtualization, type-based alias analysis, etc. See the <a
- href="http://blog.llvm.org/2010/04/extensible-metadata-in-llvm-ir.html">
- Extensible Metadata Blog Post</a> for more information.</li>
-
-<li>2.7 encodes <a href="SourceLevelDebugging.html">debug information</a>
-in a completely new way, built on extensible metadata. The new implementation
-is much more memory efficient and paves the way for improvements to optimized
-code debugging experience.</li>
-
-<li>2.7 now directly supports taking the address of a label and doing an
- indirect branch through a pointer. This is particularly useful for
- interpreter loops, and is used to implement the GCC "address of label"
- extension. For more information, see the <a
-href="http://blog.llvm.org/2010/01/address-of-label-and-indirect-branches.html">
-Address of Label and Indirect Branches in LLVM IR Blog Post</a>.
-
-<li>2.7 is the first release to start supporting APIs for assembling and
- disassembling target machine code. These APIs are useful for a variety of
- low level clients, and are surfaced in the new "enhanced disassembly" API.
- For more information see the <a
- href="http://blog.llvm.org/2010/01/x86-disassembler.html">The X86
- Disassembler Blog Post</a> for more information.</li>
-
-<li>2.7 includes major parts of the work required by the new MC Project,
- see the <a href="#mc">MC update above</a> for more information.</li>
-
+<li>.</li>
</ul>
</div>
@@ -580,29 +311,18 @@
expose new optimization opportunities:</p>
<ul>
-<li>LLVM IR now supports a 16-bit "half float" data type through <a
- href="LangRef.html#int_fp16">two new intrinsics</a> and APFloat support.</li>
-<li>LLVM IR supports two new <a href="LangRef.html#fnattrs">function
- attributes</a>: inlinehint and alignstack(n). The former is a hint to the
- optimizer that a function was declared 'inline' and thus the inliner should
- weight it higher when considering inlining it. The later
- indicates to the code generator that the function diverges from the platform
- ABI on stack alignment.</li>
-<li>The new <a href="LangRef.html#int_objectsize">llvm.objectsize</a> intrinsic
- allows the optimizer to infer the sizes of memory objects in some cases.
- This intrinsic is used to implement the GCC <tt>__builtin_object_size</tt>
- extension.</li>
-<li>LLVM IR now supports marking load and store instructions with <a
- href="LangRef.html#i_load">"non-temporal" hints</a> (building on the new
- metadata feature). This hint encourages the code
- generator to generate non-temporal accesses when possible, which are useful
- for code that is carefully managing cache behavior. Currently, only the
- X86 backend provides target support for this feature.</li>
-
-<li>LLVM 2.7 has pre-alpha support for <a
- href="LangRef.html#t_union">unions in LLVM IR</a>.
- Unfortunately, this support is not really usable in 2.7, so if you're
- interested in pushing it forward, please help contribute to LLVM mainline.</li>
+
+<li>LLVM 2.8 changes the internal order of operands in <a
+ href="http://llvm.org/doxygen/classllvm_1_1InvokeInst.html"><tt>InvokeInst</tt></a>
+ and <a href="http://llvm.org/doxygen/classllvm_1_1CallInst.html"><tt>CallInst</tt></a>.
+ To be portable across releases, resort to <tt>CallSite</tt> and the
+ high-level accessors, such as <tt>getCalledValue</tt> and <tt>setUnwindDest</tt>.
+</li>
+<li>
+ You can no longer pass use_iterators directly to cast<> (and similar), because
+ these routines tend to perform costly dereference operations more than once. You
+ have to dereference the iterators yourself and pass them in.
+</li>
</ul>
@@ -620,48 +340,7 @@
<ul>
-<li>The inliner now merges arrays stack objects in different callees when
- inlining multiple call sites into one function. This reduces the stack size
- of the resultant function.</li>
-<li>The -basicaa alias analysis pass (which is the default) has been improved to
- be less dependent on "type safe" pointers. It can now look through bitcasts
- and other constructs more aggressively, allowing better load/store
- optimization.</li>
-<li>The load elimination optimization in the GVN Pass [<a
-href="http://blog.llvm.org/2009/12/introduction-to-load-elimination-in-gvn.html">intro
- blog post</a>] has been substantially improved to be more aggressive about
- partial redundancy elimination and do more aggressive phi translation. Please
- see the <a
- href="http://blog.llvm.org/2009/12/advanced-topics-in-redundant-load.html">
- Advanced Topics in Redundant Load Elimination with a Focus on PHI Translation
- Blog Post</a> for more details.</li>
-<li>The module <a href="LangRef.html#datalayout">target data string</a> now
- includes a notion of 'native' integer data types for the target. This
- helps mid-level optimizations avoid promoting complex sequences of
- operations to data types that are not natively supported (e.g. converting
- i32 operations to i64 on 32-bit chips).</li>
-<li>The mid-level optimizer is now conservative when operating on a module with
- no target data. Previously, it would default to SparcV9 settings, which is
- not what most people expected.</li>
-<li>Jump threading is now much more aggressive at simplifying correlated
- conditionals and threading blocks with otherwise complex logic. It has
- subsumed the old "Conditional Propagation" pass, and -condprop has been
- removed from LLVM 2.7.</li>
-<li>The -instcombine pass has been refactored from being one huge file to being
- a library of its own. Internally, it uses a customized IRBuilder to clean
- it up and simplify it.</li>
-
-<li>The optimal edge profiling pass is reliable and much more complete than in
- 2.6. It can be used with the llvm-prof tool but isn't wired up to the
- llvm-gcc and clang command line options yet.</li>
-
-<li>A new experimental alias analysis implementation, -scev-aa, has been added.
- It uses LLVM's Scalar Evolution implementation to do symbolic analysis of
- pointer offset expressions to disambiguate pointers. It can catch a few
- cases that basicaa cannot, particularly in complex loop nests.</li>
-
-<li>The default pass ordering has been tweaked for improved optimization
- effectiveness.</li>
+<li></li>
</ul>
@@ -676,19 +355,7 @@
<div class="doc_text">
<ul>
-<li>The JIT now supports generating debug information and is compatible with
-the new GDB 7.0 (and later) interfaces for registering dynamically generated
-debug info.</li>
-
-<li>The JIT now <a href="http://llvm.org/PR5184">defaults
-to compiling eagerly</a> to avoid a race condition in the lazy JIT.
-Clients that still want the lazy JIT can switch it on by calling
-<tt>ExecutionEngine::DisableLazyCompilation(false)</tt>.</li>
-
-<li>It is now possible to create more than one JIT instance in the same process.
-These JITs can generate machine code in parallel,
-although <a href="http://llvm.org/docs/ProgrammersManual.html#jitthreading">you
-still have to obey the other threading restrictions</a>.</li>
+<li></li>
</ul>
@@ -706,49 +373,7 @@
it run faster:</p>
<ul>
-<li>The 'llc -asm-verbose' option (which is now the default) has been enhanced
- to emit many useful comments to .s files indicating information about spill
- slots and loop nest structure. This should make it much easier to read and
- understand assembly files. This is wired up in llvm-gcc and clang to
- the <tt>-fverbose-asm</tt> option.</li>
-
-<li>New LSR with "full strength reduction" mode, which can reduce address
- register pressure in loops where address generation is important.</li>
-
-<li>A new codegen level Common Subexpression Elimination pass (MachineCSE)
- is available and enabled by default. It catches redundancies exposed by
- lowering.</li>
-<li>A new pre-register-allocation tail duplication pass is available and enabled
- by default, it can substantially improve branch prediction quality in some
- cases.</li>
-<li>A new sign and zero extension optimization pass (OptimizeExtsPass)
- is available and enabled by default. This pass can takes advantage
- architecture features like x86-64 implicit zero extension behavior and
- sub-registers.</li>
-<li>The code generator now supports a mode where it attempts to preserve the
- order of instructions in the input code. This is important for source that
- is hand scheduled and extremely sensitive to scheduling. It is compatible
- with the GCC <tt>-fno-schedule-insns</tt> option.</li>
-<li>The target-independent code generator now supports generating code with
- arbitrary numbers of result values. Returning more values than was
- previously supported is handled by returning through a hidden pointer. In
- 2.7, only the X86 and XCore targets have adopted support for this
- though.</li>
-<li>The code generator now supports generating code that follows the
- <a href="LangRef.html#callingconv">Glasgow Haskell Compiler Calling
- Convention</a> and ABI.</li>
-<li>The "<a href="CodeGenerator.html#selectiondag_select">DAG instruction
- selection</a>" phase of the code generator has been largely rewritten for
- 2.7. Previously, tblgen spit out tons of C++ code which was compiled and
- linked into the target to do the pattern matching, now it emits a much
- smaller table which is read by the target-independent code. The primary
- advantages of this approach is that the size and compile time of various
- targets is much improved. The X86 code generator shrunk by 1.5MB of code,
- for example.</li>
-<li>Almost the entire code generator has switched to emitting code through the
- MC interfaces instead of printing textually to the .s file. This led to a
- number of cleanups and speedups. In 2.7, debug an exception handling
- information does not go through MC yet.</li>
+<li>MachO writer works.</li>
</ul>
</div>
@@ -762,11 +387,9 @@
</p>
<ul>
-<li>The X86 backend now optimizes tails calls much more aggressively for
- functions that use the standard C calling convention.</li>
-<li>The X86 backend now models scalar SSE registers as subregs of the SSE vector
- registers, making the code generator more aggressive in cases where scalars
- and vector types are mixed.</li>
+<li>The X86 backend now supports holding X87 floating point stack values
+ in registers across basic blocks, dramatically improving performance of code
+ that uses long double, and when targetting CPUs that don't support SSE.</li>
</ul>
@@ -783,27 +406,7 @@
<ul>
-<li>The ARM backend now generates instructions in unified assembly syntax.</li>
-
-<li>llvm-gcc now has complete support for the ARM v7 NEON instruction set. This
- support differs slightly from the GCC implementation. Please see the
- <a
-href="http://blog.llvm.org/2010/04/arm-advanced-simd-neon-intrinsics-and.html">
- ARM Advanced SIMD (NEON) Intrinsics and Types in LLVM Blog Post</a> for
- helpful information if migrating code from GCC to LLVM-GCC.</li>
-
-<li>The ARM and Thumb code generators now use register scavenging for stack
- object address materialization. This allows the use of R3 as a general
- purpose register in Thumb1 code, as it was previous reserved for use in
- stack address materialization. Secondly, sequential uses of the same
- value will now re-use the materialized constant.</li>
-
-<li>The ARM backend now has good support for ARMv4 targets and has been tested
- on StrongARM hardware. Previously, LLVM only supported ARMv4T and
- newer chips.</li>
-
-<li>Atomic builtins are now supported for ARMv6 and ARMv7 (__sync_synchronize,
- __sync_fetch_and_add, etc.).</li>
+<li></li>
</ul>
@@ -822,34 +425,7 @@
</p>
<ul>
-<li>The optimizer uses the new CodeMetrics class to measure the size of code.
- Various passes (like the inliner, loop unswitcher, etc) all use this to make
- more accurate estimates of the code size impact of various
- optimizations.</li>
-<li>A new <a href="http://llvm.org/doxygen/InstructionSimplify_8h-source.html">
- llvm/Analysis/InstructionSimplify.h</a> interface is available for doing
- symbolic simplification of instructions (e.g. <tt>a+0</tt> -> <tt>a</tt>)
- without requiring the instruction to exist. This centralizes a lot of
- ad-hoc symbolic manipulation code scattered in various passes.</li>
-<li>The optimizer now uses a new <a
- href="http://llvm.org/doxygen/SSAUpdater_8h-source.html">SSAUpdater</a>
- class which efficiently supports
- doing unstructured SSA update operations. This centralized a bunch of code
- scattered throughout various passes (e.g. jump threading, lcssa,
- loop rotate, etc) for doing this sort of thing. The code generator has a
- similar <a href="http://llvm.org/doxygen/MachineSSAUpdater_8h-source.html">
- MachineSSAUpdater</a> class.</li>
-<li>The <a href="http://llvm.org/doxygen/Regex_8h-source.html">
- llvm/Support/Regex.h</a> header exposes a platform independent regular
- expression API. Building on this, the <a
- href="TestingGuide.html#FileCheck">FileCheck</a> utility now supports
- regular exressions.</li>
-<li>raw_ostream now supports a circular "debug stream" accessed with "dbgs()".
- By default, this stream works the same way as "errs()", but if you pass
- <tt>-debug-buffer-size=1000</tt> to opt, the debug stream is capped to a
- fixed sized circular buffer and the output is printed at the end of the
- program's execution. This is helpful if you have a long lived compiler
- process and you're interested in seeing snapshots in time.</li>
+<li></li>
</ul>
@@ -864,16 +440,7 @@
<p>Other miscellaneous features include:</p>
<ul>
-<li>You can now build LLVM as a big dynamic library (e.g. "libllvm2.7.so"). To
- get this, configure LLVM with the --enable-shared option.</li>
-
-<li>LLVM command line tools now overwrite their output by default. Previously,
- they would only do this with -f. This makes them more convenient to use, and
- behave more like standard unix tools.</li>
-
-<li>The opt and llc tools now autodetect whether their input is a .ll or .bc
- file, and automatically do the right thing. This means you don't need to
- explicitly use the llvm-as tool for most things.</li>
+<li></li>
</ul>
</div>
@@ -887,48 +454,18 @@
<div class="doc_text">
<p>If you're already an LLVM user or developer with out-of-tree changes based
-on LLVM 2.6, this section lists some "gotchas" that you may run into upgrading
+on LLVM 2.7, this section lists some "gotchas" that you may run into upgrading
from the previous release.</p>
<ul>
-<li>
-The Andersen's alias analysis ("anders-aa") pass, the Predicate Simplifier
-("predsimplify") pass, the LoopVR pass, the GVNPRE pass, and the random sampling
-profiling ("rsprofiling") passes have all been removed. They were not being
-actively maintained and had substantial problems. If you are interested in
-these components, you are welcome to ressurect them from SVN, fix the
-correctness problems, and resubmit them to mainline.</li>
-
-<li>LLVM now defaults to building most libraries with RTTI turned off, providing
-a code size reduction. Packagers who are interested in building LLVM to support
-plugins that require RTTI information should build with "make REQUIRE_RTTI=1"
-and should read the new <a href="Packaging.html">Advice on Packaging LLVM</a>
-document.</li>
-
-<li>The LLVM interpreter now defaults to <em>not</em> using <tt>libffi</tt> even
-if you have it installed. This makes it more likely that an LLVM built on one
-system will work when copied to a similar system. To use <tt>libffi</tt>,
-configure with <tt>--enable-libffi</tt>.</li>
-
-<li>Debug information uses a completely different representation, an LLVM 2.6
-.bc file should work with LLVM 2.7, but debug info won't come forward.</li>
-
-<li>The LLVM 2.6 (and earlier) "malloc" and "free" instructions got removed,
- along with LowerAllocations pass. Now you should just use a call to the
- malloc and free functions in libc. These calls are optimized as well as
- the old instructions were.</li>
+<li>.</li>
</ul>
<p>In addition, many APIs have changed in this release. Some of the major LLVM
API changes are:</p>
<ul>
-
-<li>The <tt>add</tt>, <tt>sub</tt>, and <tt>mul</tt> instructions no longer
-support floating-point operands. The <tt>fadd</tt>, <tt>fsub</tt>, and
-<tt>fmul</tt> instructions should be used for this purpose instead.</li>
-
</ul>
</div>
@@ -1007,8 +544,7 @@
<li>The MSIL, Alpha, SPU, MIPS, PIC16, Blackfin, MSP430, SystemZ and MicroBlaze
backends are experimental.</li>
<li><tt>llc</tt> "<tt>-filetype=asm</tt>" (the default) is the only
- supported value for this option. The MachO writer is experimental, and
- works much better in mainline SVN.</li>
+ supported value for this option. XXX Update me</li>
</ul>
</div>
@@ -1025,8 +561,6 @@
all <a href="http://llvm.org/PR879">inline assembly that uses the X86
floating point stack</a>. It supports the 'f' and 't' constraints, but not
'u'.</li>
- <li>The X86 backend generates inefficient floating point code when configured
- to generate code for systems that don't have SSE2.</li>
<li>Win64 code generation wasn't widely tested. Everything should work, but we
expect small issues to happen. Also, llvm-gcc cannot build the mingw64
runtime currently due to lack of support for the 'u' inline assembly
Modified: llvm/branches/wendling/eh/docs/WritingAnLLVMBackend.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/WritingAnLLVMBackend.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/WritingAnLLVMBackend.html (original)
+++ llvm/branches/wendling/eh/docs/WritingAnLLVMBackend.html Sat Jul 31 19:59:02 2010
@@ -1299,9 +1299,6 @@
</p>
<ul>
-<li><tt>isMoveInstr</tt> — Return true if the instruction is a register to
- register move; false, otherwise.</li>
-
<li><tt>isLoadFromStackSlot</tt> — If the specified machine instruction is
a direct load from a stack slot, return the register number of the
destination and the <tt>FrameIndex</tt> of the stack slot.</li>
Modified: llvm/branches/wendling/eh/docs/WritingAnLLVMPass.html
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/docs/WritingAnLLVMPass.html?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/docs/WritingAnLLVMPass.html (original)
+++ llvm/branches/wendling/eh/docs/WritingAnLLVMPass.html Sat Jul 31 19:59:02 2010
@@ -290,7 +290,7 @@
initialization value is not important.</p>
<div class="doc_code"><pre>
- RegisterPass<Hello> X("<i>hello</i>", "<i>Hello World Pass</i>",
+ INITIALIZE_PASS(Hello, "<i>hello</i>", "<i>Hello World Pass</i>",
false /* Only looks at CFG */,
false /* Analysis Pass */);
} <i>// end of anonymous namespace</i>
@@ -299,7 +299,7 @@
<p>Lastly, we <a href="#registration">register our class</a> <tt>Hello</tt>,
giving it a command line
argument "<tt>hello</tt>", and a name "<tt>Hello World Pass</tt>".
-Last two RegisterPass arguments are optional. Their default value is false.
+Last two arguments describe its behavior.
If a pass walks CFG without modifying it then third argument is set to true.
If a pass is an analysis pass, for example dominator tree pass, then true
is supplied as fourth argument. </p>
@@ -326,8 +326,9 @@
};
char Hello::ID = 0;
- RegisterPass<Hello> X("<i>hello</i>", "<i>Hello World Pass</i>");
+ INITIALIZE_PASS(Hello, "<i>Hello</i>", "<i>Hello World Pass</i>", false, false);
}
+
</pre></div>
<p>Now that it's all together, compile the file with a simple "<tt>gmake</tt>"
@@ -348,7 +349,7 @@
<p>Now that you have a brand new shiny shared object file, we can use the
<tt>opt</tt> command to run an LLVM program through your pass. Because you
-registered your pass with the <tt>RegisterPass</tt> template, you will be able to
+registered your pass with the <tt>INITIALIZE_PASS</tt> macro, you will be able to
use the <tt>opt</tt> tool to access it, once loaded.</p>
<p>To test it, follow the example at the end of the <a
@@ -966,9 +967,8 @@
pass registration works, and discussed some of the reasons that it is used and
what it does. Here we discuss how and why passes are registered.</p>
-<p>As we saw above, passes are registered with the <b><tt>RegisterPass</tt></b>
-template, which requires you to pass at least two
-parameters. The first parameter is the name of the pass that is to be used on
+<p>As we saw above, passes are registered with the <b><tt>INITIALIZE_PASS</tt></b>
+macro. The first parameter is the name of the pass that is to be used on
the command line to specify that the pass should be added to a program (for
example, with <tt>opt</tt> or <tt>bugpoint</tt>). The second argument is the
name of the pass, which is to be used for the <tt>-help</tt> output of
@@ -1247,7 +1247,7 @@
<p>Although <a href="#registration">Pass Registration</a> is optional for normal
passes, all analysis group implementations must be registered, and must use the
-<A href="#registerag"><tt>RegisterAnalysisGroup</tt></a> template to join the
+<A href="#registerag"><tt>INITIALIZE_AG_PASS</tt></a> template to join the
implementation pool. Also, a default implementation of the interface
<b>must</b> be registered with <A
href="#registerag"><tt>RegisterAnalysisGroup</tt></a>.</p>
@@ -1283,8 +1283,10 @@
<div class="doc_text">
<p>The <tt>RegisterAnalysisGroup</tt> template is used to register the analysis
-group itself as well as add pass implementations to the analysis group. First,
-an analysis should be registered, with a human readable name provided for it.
+group itself, while the <tt>INITIALIZE_AG_PASS</tt> is used to add pass
+implementations to the analysis group. First,
+an analysis group should be registered, with a human readable name
+provided for it.
Unlike registration of passes, there is no command line argument to be specified
for the Analysis Group Interface itself, because it is "abstract":</p>
@@ -1297,35 +1299,36 @@
<div class="doc_code"><pre>
<b>namespace</b> {
- //<i> Analysis Group implementations <b>must</b> be registered normally...</i>
- RegisterPass<FancyAA>
- B("<i>somefancyaa</i>", "<i>A more complex alias analysis implementation</i>");
-
//<i> Declare that we implement the AliasAnalysis interface</i>
- RegisterAnalysisGroup<<a href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>> C(B);
+ INITIALIZE_AG_PASS(FancyAA, <a href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>, "<i>somefancyaa</i>",
+ "<i>A more complex alias analysis implementation</i>",
+ false, // <i>Is CFG Only?</i>
+ true, // <i>Is Analysis?</i>
+ false, // <i>Is default Analysis Group implementation?</i>
+ );
}
</pre></div>
-<p>This just shows a class <tt>FancyAA</tt> that is registered normally, then
-uses the <tt>RegisterAnalysisGroup</tt> template to "join" the <tt><a
-href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a></tt>
+<p>This just shows a class <tt>FancyAA</tt> that
+uses the <tt>INITIALIZE_AG_PASS</tt> macro both to register and
+to "join" the <tt><a href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a></tt>
analysis group. Every implementation of an analysis group should join using
-this template. A single pass may join multiple different analysis groups with
-no problem.</p>
+this macro.</p>
<div class="doc_code"><pre>
<b>namespace</b> {
- //<i> Analysis Group implementations <b>must</b> be registered normally...</i>
- RegisterPass<<a href="http://llvm.org/doxygen/structBasicAliasAnalysis.html">BasicAliasAnalysis</a>>
- D("<i>basicaa</i>", "<i>Basic Alias Analysis (default AA impl)</i>");
-
//<i> Declare that we implement the AliasAnalysis interface</i>
- RegisterAnalysisGroup<<a href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>, <b>true</b>> E(D);
+ INITIALIZE_AG_PASS(BasicAA, <a href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>, "<i>basicaa</i>",
+ "<i>Basic Alias Analysis (default AA impl)</i>",
+ false, // <i>Is CFG Only?</i>
+ true, // <i>Is Analysis?</i>
+ true, // <i>Is default Analysis Group implementation?</i>
+ );
}
</pre></div>
-<p>Here we show how the default implementation is specified (using the extra
-argument to the <tt>RegisterAnalysisGroup</tt> template). There must be exactly
+<p>Here we show how the default implementation is specified (using the final
+argument to the <tt>INITIALIZE_AG_PASS</tt> template). There must be exactly
one default implementation available at all times for an Analysis Group to be
used. Only default implementation can derive from <tt>ImmutablePass</tt>.
Here we declare that the
Propchange: llvm/branches/wendling/eh/examples/BrainF/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -1,7 +1,10 @@
-Release
Debug
+Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/ExceptionDemo/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -0,0 +1,10 @@
+Debug
+Release
+Release-Asserts
+Debug+Coverage-Asserts
+Release+Coverage-Asserts
+Debug+Coverage
+Release+Coverage
+Debug+Checks
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Fibonacci/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,6 +2,10 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
+
Propchange: llvm/branches/wendling/eh/examples/HowToUseJIT/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,6 +2,10 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
+
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter2/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter3/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter4/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter5/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter6/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/Kaleidoscope/Chapter7/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,7 +2,9 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
-
+Debug+Asserts
+Release+Asserts
Propchange: llvm/branches/wendling/eh/examples/ModuleMaker/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,6 +2,10 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
+
Propchange: llvm/branches/wendling/eh/examples/ParallelJIT/
------------------------------------------------------------------------------
--- svn:ignore (original)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -2,6 +2,10 @@
Release
Release-Asserts
Debug+Coverage-Asserts
+Release+Coverage-Asserts
Debug+Coverage
Release+Coverage
Debug+Checks
+Debug+Asserts
+Release+Asserts
+
Modified: llvm/branches/wendling/eh/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm-c/Core.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm-c/Core.h (original)
+++ llvm/branches/wendling/eh/include/llvm-c/Core.h Sat Jul 31 19:59:02 2010
@@ -750,6 +750,9 @@
const char *Name);
void LLVMDeleteBasicBlock(LLVMBasicBlockRef BB);
+void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos);
+void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos);
+
/* Operations on instructions */
LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);
LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB);
Modified: llvm/branches/wendling/eh/include/llvm-c/EnhancedDisassembly.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm-c/EnhancedDisassembly.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm-c/EnhancedDisassembly.h (original)
+++ llvm/branches/wendling/eh/include/llvm-c/EnhancedDisassembly.h Sat Jul 31 19:59:02 2010
@@ -51,41 +51,38 @@
@typedef EDAssemblySyntax_t
An assembly syntax for use in tokenizing instructions.
*/
-typedef enum {
+enum {
/*! @constant kEDAssemblySyntaxX86Intel Intel syntax for i386 and x86_64. */
kEDAssemblySyntaxX86Intel = 0,
/*! @constant kEDAssemblySyntaxX86ATT AT&T syntax for i386 and x86_64. */
kEDAssemblySyntaxX86ATT = 1,
kEDAssemblySyntaxARMUAL = 2
-} EDAssemblySyntax_t;
+};
+typedef unsigned EDAssemblySyntax_t;
/*!
@typedef EDDisassemblerRef
Encapsulates a disassembler for a single CPU architecture.
*/
-struct EDDisassembler;
-typedef struct EDDisassembler *EDDisassemblerRef;
+typedef void *EDDisassemblerRef;
/*!
@typedef EDInstRef
Encapsulates a single disassembled instruction in one assembly syntax.
*/
-struct EDInst;
-typedef struct EDInst *EDInstRef;
+typedef void *EDInstRef;
/*!
@typedef EDTokenRef
Encapsulates a token from the disassembly of an instruction.
*/
-struct EDToken;
-typedef struct EDToken *EDTokenRef;
+typedef void *EDTokenRef;
/*!
@typedef EDOperandRef
Encapsulates an operand of an instruction.
*/
-struct EDOperand;
-typedef struct EDOperand *EDOperandRef;
+typedef void *EDOperandRef;
/*!
@functiongroup Getting a disassembler
Modified: llvm/branches/wendling/eh/include/llvm-c/ExecutionEngine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm-c/ExecutionEngine.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm-c/ExecutionEngine.h (original)
+++ llvm/branches/wendling/eh/include/llvm-c/ExecutionEngine.h Sat Jul 31 19:59:02 2010
@@ -116,6 +116,8 @@
LLVMBool LLVMFindFunction(LLVMExecutionEngineRef EE, const char *Name,
LLVMValueRef *OutFn);
+void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRef Fn);
+
LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef EE);
void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global,
Modified: llvm/branches/wendling/eh/include/llvm/ADT/DenseSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/DenseSet.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/DenseSet.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/DenseSet.h Sat Jul 31 19:59:02 2010
@@ -58,6 +58,7 @@
class Iterator {
typename MapTy::iterator I;
+ friend class DenseSet;
public:
typedef typename MapTy::iterator::difference_type difference_type;
typedef ValueT value_type;
@@ -77,6 +78,7 @@
class ConstIterator {
typename MapTy::const_iterator I;
+ friend class DenseSet;
public:
typedef typename MapTy::const_iterator::difference_type difference_type;
typedef ValueT value_type;
@@ -103,6 +105,10 @@
const_iterator begin() const { return ConstIterator(TheMap.begin()); }
const_iterator end() const { return ConstIterator(TheMap.end()); }
+ iterator find(const ValueT &V) { return Iterator(TheMap.find(V)); }
+ bool erase(Iterator I) { return TheMap.erase(I.I); }
+ bool erase(ConstIterator CI) { return TheMap.erase(CI.I); }
+
std::pair<iterator, bool> insert(const ValueT &V) {
return TheMap.insert(std::make_pair(V, 0));
}
Modified: llvm/branches/wendling/eh/include/llvm/ADT/ScopedHashTable.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/ScopedHashTable.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/ScopedHashTable.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/ScopedHashTable.h Sat Jul 31 19:59:02 2010
@@ -139,7 +139,12 @@
}
V lookup(const K &Key) {
- return TopLevelMap[Key]->getValue();
+ typename DenseMap<K, ScopedHashTableVal<K, V, KInfo>*, KInfo>::iterator
+ I = TopLevelMap.find(Key);
+ if (I != TopLevelMap.end())
+ return I->second->getValue();
+
+ return V();
}
void insert(const K &Key, const V &Val) {
Modified: llvm/branches/wendling/eh/include/llvm/ADT/StringMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/StringMap.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/StringMap.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/StringMap.h Sat Jul 31 19:59:02 2010
@@ -254,6 +254,10 @@
StringMap() : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {}
explicit StringMap(unsigned InitialSize)
: StringMapImpl(InitialSize, static_cast<unsigned>(sizeof(MapEntryTy))) {}
+
+ explicit StringMap(AllocatorTy A)
+ : StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))), Allocator(A) {}
+
explicit StringMap(const StringMap &RHS)
: StringMapImpl(static_cast<unsigned>(sizeof(MapEntryTy))) {
assert(RHS.empty() &&
Modified: llvm/branches/wendling/eh/include/llvm/ADT/StringSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/StringSet.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/StringSet.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/StringSet.h Sat Jul 31 19:59:02 2010
@@ -15,7 +15,6 @@
#define LLVM_ADT_STRINGSET_H
#include "llvm/ADT/StringMap.h"
-#include <cassert>
namespace llvm {
@@ -26,10 +25,10 @@
class StringSet : public llvm::StringMap<char, AllocatorTy> {
typedef llvm::StringMap<char, AllocatorTy> base;
public:
- bool insert(const std::string& InLang) {
+ bool insert(StringRef InLang) {
assert(!InLang.empty());
- const char* KeyStart = &InLang[0];
- const char* KeyEnd = KeyStart + InLang.size();
+ const char *KeyStart = InLang.data();
+ const char *KeyEnd = KeyStart + InLang.size();
return base::insert(llvm::StringMapEntry<char>::
Create(KeyStart, KeyEnd, base::getAllocator(), '+'));
}
Modified: llvm/branches/wendling/eh/include/llvm/ADT/ValueMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ADT/ValueMap.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ADT/ValueMap.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ADT/ValueMap.h Sat Jul 31 19:59:02 2010
@@ -87,7 +87,12 @@
typedef ValueT mapped_type;
typedef std::pair<KeyT, ValueT> value_type;
- ValueMap(const ValueMap& Other) : Map(Other.Map), Data(Other.Data) {}
+ ValueMap(const ValueMap& Other) : Map(Other.Map), Data(Other.Data) {
+ // Each ValueMapCVH key contains a pointer to the containing ValueMap.
+ // The keys in the new map need to point to the new map, not Other.
+ for (typename MapT::iterator I = Map.begin(), E = Map.end(); I != E; ++I)
+ I->first.Map = this;
+ }
explicit ValueMap(unsigned NumInitBuckets = 64)
: Map(NumInitBuckets), Data() {}
@@ -250,12 +255,6 @@
}
};
-
-template<typename KeyT, typename ValueT, typename Config, typename ValueInfoT>
-struct isPodLike<ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> > {
- static const bool value = true;
-};
-
template<typename KeyT, typename ValueT, typename Config, typename ValueInfoT>
struct DenseMapInfo<ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> > {
typedef ValueMapCallbackVH<KeyT, ValueT, Config, ValueInfoT> VH;
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/DebugInfo.h Sat Jul 31 19:59:02 2010
@@ -134,7 +134,7 @@
public:
explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}
- unsigned getLanguage() const { return getUnsignedField(2); }
+ unsigned getLanguage() const { return getUnsignedField(2); }
StringRef getFilename() const { return getStringField(3); }
StringRef getDirectory() const { return getStringField(4); }
StringRef getProducer() const { return getStringField(5); }
@@ -304,8 +304,7 @@
void dump() const;
/// replaceAllUsesWith - Replace all uses of debug info referenced by
- /// this descriptor. After this completes, the current debug info value
- /// is erased.
+ /// this descriptor.
void replaceAllUsesWith(DIDescriptor &D);
};
@@ -504,10 +503,18 @@
public:
explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}
DIScope getContext() const { return getFieldAs<DIScope>(1); }
- StringRef getDirectory() const { return getContext().getDirectory(); }
- StringRef getFilename() const { return getContext().getFilename(); }
unsigned getLineNumber() const { return getUnsignedField(2); }
unsigned getColumnNumber() const { return getUnsignedField(3); }
+ StringRef getDirectory() const {
+ DIFile F = getFieldAs<DIFile>(4);
+ StringRef dir = F.getDirectory();
+ return !dir.empty() ? dir : getContext().getDirectory();
+ }
+ StringRef getFilename() const {
+ DIFile F = getFieldAs<DIFile>(4);
+ StringRef filename = F.getFilename();
+ return !filename.empty() ? filename : getContext().getFilename();
+ }
};
/// DINameSpace - A wrapper for a C++ style name space.
@@ -694,8 +701,8 @@
/// CreateLexicalBlock - This creates a descriptor for a lexical block
/// with the specified parent context.
- DILexicalBlock CreateLexicalBlock(DIDescriptor Context, unsigned Line = 0,
- unsigned Col = 0);
+ DILexicalBlock CreateLexicalBlock(DIDescriptor Context, DIFile F,
+ unsigned Line = 0, unsigned Col = 0);
/// CreateNameSpace - This creates new descriptor for a namespace
/// with the specified parent context.
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/Dominators.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/Dominators.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/Dominators.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/Dominators.h Sat Jul 31 19:59:02 2010
@@ -995,6 +995,9 @@
/// print - Convert to human readable form
///
virtual void print(raw_ostream &OS, const Module* = 0) const;
+
+ /// dump - Dump the dominance frontier to dbgs().
+ void dump() const;
};
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/LazyValueInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/LazyValueInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/LazyValueInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/LazyValueInfo.h Sat Jul 31 19:59:02 2010
@@ -57,6 +57,10 @@
/// constant on the specified edge. Return null if not.
Constant *getConstantOnEdge(Value *V, BasicBlock *FromBB, BasicBlock *ToBB);
+ /// threadEdge - Inform the analysis cache that we have threaded an edge from
+ /// PredBB to OldSucc to be from PredBB to NewSucc instead.
+ void threadEdge(BasicBlock *PredBB, BasicBlock *OldSucc, BasicBlock *NewSucc);
+
// Implementation boilerplate.
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/LibCallAliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/LibCallAliasAnalysis.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/LibCallAliasAnalysis.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/LibCallAliasAnalysis.h Sat Jul 31 19:59:02 2010
@@ -49,6 +49,16 @@
return false;
}
+ /// getAdjustedAnalysisPointer - This method is used when a pass implements
+ /// an analysis interface through multiple inheritance. If needed, it
+ /// should override this to adjust the this pointer as needed for the
+ /// specified pass info.
+ virtual void *getAdjustedAnalysisPointer(const PassInfo *PI) {
+ if (PI->isPassID(&AliasAnalysis::ID))
+ return (AliasAnalysis*)this;
+ return this;
+ }
+
private:
ModRefResult AnalyzeLibCallDetails(const LibCallFunctionInfo *FI,
CallSite CS, Value *P, unsigned Size);
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/LoopInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/LoopInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/LoopInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/LoopInfo.h Sat Jul 31 19:59:02 2010
@@ -35,6 +35,7 @@
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/raw_ostream.h"
@@ -229,13 +230,16 @@
return 0;
}
+ /// Edge type.
+ typedef std::pair<BlockT*, BlockT*> Edge;
+
/// getExitEdges - Return all pairs of (_inside_block_,_outside_block_).
- typedef std::pair<const BlockT*,const BlockT*> Edge;
- void getExitEdges(SmallVectorImpl<Edge> &ExitEdges) const {
+ template <typename EdgeT>
+ void getExitEdges(SmallVectorImpl<EdgeT> &ExitEdges) const {
// Sort the blocks vector so that we can use binary search to do quick
// lookups.
SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
- std::sort(LoopBBs.begin(), LoopBBs.end());
+ array_pod_sort(LoopBBs.begin(), LoopBBs.end());
typedef GraphTraits<BlockT*> BlockTraits;
for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)
@@ -244,7 +248,7 @@
I != E; ++I)
if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
// Not in current loop? It must be an exit block.
- ExitEdges.push_back(std::make_pair(*BI, *I));
+ ExitEdges.push_back(EdgeT(*BI, *I));
}
/// getLoopPreheader - If there is a preheader for this loop, return it. A
@@ -505,6 +509,12 @@
}
};
+template<class BlockT, class LoopT>
+raw_ostream& operator<<(raw_ostream &OS, const LoopBase<BlockT, LoopT> &Loop) {
+ Loop.print(OS);
+ return OS;
+}
+
class Loop : public LoopBase<BasicBlock, Loop> {
public:
Loop() {}
@@ -552,12 +562,6 @@
///
PHINode *getCanonicalInductionVariable() const;
- /// getCanonicalInductionVariableIncrement - Return the LLVM value that holds
- /// the canonical induction variable value for the "next" iteration of the
- /// loop. This always succeeds if getCanonicalInductionVariable succeeds.
- ///
- Instruction *getCanonicalInductionVariableIncrement() const;
-
/// getTripCount - Return a loop-invariant LLVM value indicating the number of
/// times the loop will be executed. Note that this means that the backedge
/// of the loop executes N-1 times. If the trip-count cannot be determined,
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/Passes.h Sat Jul 31 19:59:02 2010
@@ -154,6 +154,13 @@
// print debug info intrinsics in human readable form
FunctionPass *createDbgInfoPrinterPass();
+ //===--------------------------------------------------------------------===//
+ //
+ // createRegionInfoPass - This pass finds all single entry single exit regions
+ // in a function and builds the region hierarchy.
+ //
+ FunctionPass *createRegionInfoPass();
+
// Print module-level debug info metadata in human-readable form.
ModulePass *createModuleDebugInfoPrinterPass();
}
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolution.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolution.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolution.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolution.h Sat Jul 31 19:59:02 2010
@@ -44,6 +44,7 @@
class Loop;
class LoopInfo;
class Operator;
+ class SCEVUnknown;
/// SCEV - This class represents an analyzed expression in the program. These
/// are opaque objects that the client is not allowed to do much with
@@ -175,6 +176,7 @@
friend class SCEVCallbackVH;
friend class SCEVExpander;
+ friend class SCEVUnknown;
/// F - The function we are analyzing.
///
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpander.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpander.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpander.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpander.h Sat Jul 31 19:59:02 2010
@@ -18,6 +18,7 @@
#include "llvm/Analysis/ScalarEvolutionNormalization.h"
#include "llvm/Support/IRBuilder.h"
#include "llvm/Support/TargetFolder.h"
+#include "llvm/Support/ValueHandle.h"
#include <set>
namespace llvm {
@@ -31,8 +32,8 @@
ScalarEvolution &SE;
std::map<std::pair<const SCEV *, Instruction *>, AssertingVH<Value> >
InsertedExpressions;
- std::set<Value*> InsertedValues;
- std::set<Value*> InsertedPostIncValues;
+ std::set<AssertingVH<Value> > InsertedValues;
+ std::set<AssertingVH<Value> > InsertedPostIncValues;
/// PostIncLoops - Addrecs referring to any of the given loops are expanded
/// in post-inc mode. For example, expanding {1,+,1}<L> in post-inc mode
@@ -70,13 +71,18 @@
/// clear - Erase the contents of the InsertedExpressions map so that users
/// trying to expand the same expression into multiple BasicBlocks or
/// different places within the same BasicBlock can do so.
- void clear() { InsertedExpressions.clear(); }
+ void clear() {
+ InsertedExpressions.clear();
+ InsertedValues.clear();
+ InsertedPostIncValues.clear();
+ }
/// getOrInsertCanonicalInductionVariable - This method returns the
/// canonical induction variable of the specified type for the specified
/// loop (inserting one if there is none). A canonical induction variable
/// starts at zero and steps by one on each iteration.
- Value *getOrInsertCanonicalInductionVariable(const Loop *L, const Type *Ty);
+ PHINode *getOrInsertCanonicalInductionVariable(const Loop *L,
+ const Type *Ty);
/// expandCodeFor - Insert code to directly compute the specified SCEV
/// expression into the program. The inserted code is inserted into the
Modified: llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpressions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpressions.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpressions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Analysis/ScalarEvolutionExpressions.h Sat Jul 31 19:59:02 2010
@@ -522,7 +522,10 @@
///
class SCEVUnknown : public SCEV {
friend class ScalarEvolution;
+ friend class ScalarEvolution::SCEVCallbackVH;
+ // This should be an AssertingVH, however SCEVUnknowns are allocated in a
+ // BumpPtrAllocator so their destructors are never called.
Value *V;
SCEVUnknown(const FoldingSetNodeIDRef ID, Value *v) :
SCEV(ID, scUnknown), V(v) {}
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/AsmPrinter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/AsmPrinter.h Sat Jul 31 19:59:02 2010
@@ -296,7 +296,7 @@
MCSymbol *GetBlockAddressSymbol(const BlockAddress *BA) const;
MCSymbol *GetBlockAddressSymbol(const BasicBlock *BB) const;
- //===------------------------------------------------------------------===//
+ //===------------------------------------------------------------------===//
// Emission Helper Routines.
//===------------------------------------------------------------------===//
public:
@@ -369,6 +369,10 @@
/// operands.
virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
+ /// getISAEncoding - Get the value for DW_AT_APPLE_isa. Zero if no isa
+ /// encoding specified.
+ virtual unsigned getISAEncoding() { return 0; }
+
//===------------------------------------------------------------------===//
// Dwarf Lowering Routines
//===------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/LiveInterval.h Sat Jul 31 19:59:02 2010
@@ -465,6 +465,8 @@
/// overlaps - Return true if the intersection of the two live intervals is
/// not empty.
bool overlaps(const LiveInterval& other) const {
+ if (other.empty())
+ return false;
return overlapsFrom(other, other.begin());
}
@@ -543,6 +545,7 @@
Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From);
void extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd);
Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex NewStr);
+ void markValNoForDeletion(VNInfo *V);
LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/LiveIntervalAnalysis.h Sat Jul 31 19:59:02 2010
@@ -197,6 +197,26 @@
return indexes_->getMBBEndIdx(mbb);
}
+ bool isLiveInToMBB(const LiveInterval &li,
+ const MachineBasicBlock *mbb) const {
+ return li.liveAt(getMBBStartIdx(mbb));
+ }
+
+ LiveRange* findEnteringRange(LiveInterval &li,
+ const MachineBasicBlock *mbb) {
+ return li.getLiveRangeContaining(getMBBStartIdx(mbb));
+ }
+
+ bool isLiveOutOfMBB(const LiveInterval &li,
+ const MachineBasicBlock *mbb) const {
+ return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
+ }
+
+ LiveRange* findExitingRange(LiveInterval &li,
+ const MachineBasicBlock *mbb) {
+ return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
+ }
+
MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
return indexes_->getMBBFromIndex(index);
}
@@ -217,6 +237,10 @@
indexes_->replaceMachineInstrInMaps(MI, NewMI);
}
+ void InsertMBBInMaps(MachineBasicBlock *MBB) {
+ indexes_->insertMBBInMaps(MBB);
+ }
+
bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
return indexes_->findLiveInMBBs(Start, End, MBBs);
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineFrameInfo.h Sat Jul 31 19:59:02 2010
@@ -94,13 +94,19 @@
// default, fixed objects are immutable unless marked otherwise.
bool isImmutable;
- // isSpillSlot - If true, the stack object is used as spill slot. It
+ // isSpillSlot - If true the stack object is used as spill slot. It
// cannot alias any other memory objects.
bool isSpillSlot;
- StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM, bool isSS)
+ // MayNeedSP - If true the stack object triggered the creation of the stack
+ // protector. We should allocate this object right after the stack
+ // protector.
+ bool MayNeedSP;
+
+ StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
+ bool isSS, bool NSP)
: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
- isSpillSlot(isSS) {}
+ isSpillSlot(isSS), MayNeedSP(NSP) {}
};
/// Objects - The list of stack objects allocated...
@@ -276,6 +282,14 @@
MaxAlignment = std::max(MaxAlignment, Align);
}
+ /// NeedsStackProtector - Returns true if the object may need stack
+ /// protectors.
+ bool MayNeedStackProtector(int ObjectIdx) const {
+ assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
+ "Invalid Object Idx!");
+ return Objects[ObjectIdx+NumFixedObjects].MayNeedSP;
+ }
+
/// getObjectOffset - Return the assigned stack offset of the specified object
/// from the incoming stack pointer.
///
@@ -382,25 +396,26 @@
return Objects[ObjectIdx+NumFixedObjects].Size == ~0ULL;
}
- /// CreateStackObject - Create a new statically sized stack object,
- /// returning a nonnegative identifier to represent it.
+ /// CreateStackObject - Create a new statically sized stack object, returning
+ /// a nonnegative identifier to represent it.
///
- int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS) {
+ int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS,
+ bool MayNeedSP = false) {
assert(Size != 0 && "Cannot allocate zero size stack objects!");
- Objects.push_back(StackObject(Size, Alignment, 0, false, isSS));
- int Index = (int)Objects.size()-NumFixedObjects-1;
+ Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedSP));
+ int Index = (int)Objects.size() - NumFixedObjects - 1;
assert(Index >= 0 && "Bad frame index!");
MaxAlignment = std::max(MaxAlignment, Alignment);
return Index;
}
- /// CreateSpillStackObject - Create a new statically sized stack
- /// object that represents a spill slot, returning a nonnegative
- /// identifier to represent it.
+ /// CreateSpillStackObject - Create a new statically sized stack object that
+ /// represents a spill slot, returning a nonnegative identifier to represent
+ /// it.
///
int CreateSpillStackObject(uint64_t Size, unsigned Alignment) {
- CreateStackObject(Size, Alignment, true);
- int Index = (int)Objects.size()-NumFixedObjects-1;
+ CreateStackObject(Size, Alignment, true, false);
+ int Index = (int)Objects.size() - NumFixedObjects - 1;
MaxAlignment = std::max(MaxAlignment, Alignment);
return Index;
}
@@ -417,9 +432,10 @@
/// variable sized object is created, whether or not the index returned is
/// actually used.
///
- int CreateVariableSizedObject() {
+ int CreateVariableSizedObject(unsigned Alignment) {
HasVarSizedObjects = true;
- Objects.push_back(StackObject(0, 1, 0, false, false));
+ Objects.push_back(StackObject(0, Alignment, 0, false, false, true));
+ MaxAlignment = std::max(MaxAlignment, Alignment);
return (int)Objects.size()-NumFixedObjects-1;
}
@@ -431,7 +447,7 @@
/// setCalleeSavedInfo - Used by prolog/epilog inserter to set the function's
/// callee saved information.
- void setCalleeSavedInfo(const std::vector<CalleeSavedInfo> &CSI) {
+ void setCalleeSavedInfo(const std::vector<CalleeSavedInfo> &CSI) {
CSInfo = CSI;
}
@@ -452,7 +468,7 @@
BitVector getPristineRegs(const MachineBasicBlock *MBB) const;
/// print - Used by the MachineFunction printer to print information about
- /// stack objects. Implemented in MachineFunction.cpp
+ /// stack objects. Implemented in MachineFunction.cpp
///
void print(const MachineFunction &MF, raw_ostream &OS) const;
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineInstr.h Sat Jul 31 19:59:02 2010
@@ -201,12 +201,14 @@
/// isLabel - Returns true if the MachineInstr represents a label.
///
bool isLabel() const {
- return getOpcode() == TargetOpcode::DBG_LABEL ||
+ return getOpcode() == TargetOpcode::PROLOG_LABEL ||
getOpcode() == TargetOpcode::EH_LABEL ||
getOpcode() == TargetOpcode::GC_LABEL;
}
- bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
+ bool isPrologLabel() const {
+ return getOpcode() == TargetOpcode::PROLOG_LABEL;
+ }
bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/MachineModuleInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/MachineModuleInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/MachineModuleInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/MachineModuleInfo.h Sat Jul 31 19:59:02 2010
@@ -344,7 +344,7 @@
VariableDbgInfo.push_back(std::make_pair(N, std::make_pair(Slot, Loc)));
}
- VariableDbgInfoMapTy &getVariableDbgInfo();
+ VariableDbgInfoMapTy &getVariableDbgInfo() { return VariableDbgInfo; }
}; // End class MachineModuleInfo
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SchedulerRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SchedulerRegistry.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SchedulerRegistry.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SchedulerRegistry.h Sat Jul 31 19:59:02 2010
@@ -78,12 +78,19 @@
ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel);
-/// createHybridListDAGScheduler - This creates a bottom up hybrid register
-/// usage reduction list scheduler that make use of latency information to
-/// avoid stalls for long latency instructions.
+/// createHybridListDAGScheduler - This creates a bottom up register pressure
+/// aware list scheduler that make use of latency information to avoid stalls
+/// for long latency instructions in low register pressure mode. In high
+/// register pressure mode it schedules to reduce register pressure.
ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level);
+/// createILPListDAGScheduler - This creates a bottom up register pressure
+/// aware list scheduler that tries to increase instruction level parallelism
+/// in low register pressure mode. In high register pressure mode it schedules
+/// to reduce register pressure.
+ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOpt::Level);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
Modified: llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CodeGen/SlotIndexes.h Sat Jul 31 19:59:02 2010
@@ -494,6 +494,11 @@
return SlotIndex(front(), 0);
}
+ /// Returns the base index of the last slot in this analysis.
+ SlotIndex getLastIndex() {
+ return SlotIndex(back(), 0);
+ }
+
/// Returns the invalid index marker for this analysis.
SlotIndex getInvalidIndex() {
return getZeroIndex();
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/Action.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/Action.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/Action.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/Action.h Sat Jul 31 19:59:02 2010
@@ -34,12 +34,16 @@
std::string OutFile_;
public:
- Action (const std::string& C, const StrVector& A,
- bool S, const std::string& O)
- : Command_(C), Args_(A), StopCompilation_(S), OutFile_(O)
- {}
+ void Construct (const std::string& C, const StrVector& A,
+ bool S, const std::string& O) {
+ Command_ = C;
+ Args_ = A;
+ StopCompilation_ = S;
+ OutFile_ = O;
+ }
+ bool IsConstructed () { return (Command_.size() != 0);}
- /// Execute - Executes the represented action.
+ /// Execute - Executes the command. Returns -1 on error.
int Execute () const;
bool StopCompilation () const { return StopCompilation_; }
const std::string& OutFile() { return OutFile_; }
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/Common.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/Common.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/Common.td (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/Common.td Sat Jul 31 19:59:02 2010
@@ -32,6 +32,7 @@
def alias_option;
def switch_option;
+def switch_list_option;
def parameter_option;
def parameter_list_option;
def prefix_option;
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/CompilationGraph.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/CompilationGraph.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/CompilationGraph.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/CompilationGraph.h Sat Jul 31 19:59:02 2010
@@ -36,7 +36,7 @@
public:
/// GetLanguage - Find the language name corresponding to a given file.
- const std::string& GetLanguage(const llvm::sys::Path&) const;
+ const std::string* GetLanguage(const llvm::sys::Path&) const;
};
/// Edge - Represents an edge of the compilation graph.
@@ -132,32 +132,32 @@
void insertNode(Tool* T);
/// insertEdge - Insert a new edge into the graph. Takes ownership
- /// of the Edge object.
- void insertEdge(const std::string& A, Edge* E);
+ /// of the Edge object. Returns non-zero value on error.
+ int insertEdge(const std::string& A, Edge* E);
- /// Build - Build target(s) from the input file set. Command-line
- /// options are passed implicitly as global variables.
+ /// Build - Build target(s) from the input file set. Command-line options
+ /// are passed implicitly as global variables. Returns non-zero value on
+ /// error (usually the failed program's exit code).
int Build(llvm::sys::Path const& TempDir, const LanguageMap& LangMap);
- /// Check - Check the compilation graph for common errors like
- /// cycles, input/output language mismatch and multiple default
- /// edges. Prints error messages and in case it finds any errors.
+ /// Check - Check the compilation graph for common errors like cycles,
+ /// input/output language mismatch and multiple default edges. Prints error
+ /// messages and in case it finds any errors.
int Check();
- /// getNode - Return a reference to the node correponding to the
- /// given tool name. Throws std::runtime_error.
- Node& getNode(const std::string& ToolName);
- const Node& getNode(const std::string& ToolName) const;
-
- /// viewGraph - This function is meant for use from the debugger.
- /// You can just say 'call G->viewGraph()' and a ghostview window
- /// should pop up from the program, displaying the compilation
- /// graph. This depends on there being a 'dot' and 'gv' program
- /// in your path.
+ /// getNode - Return a reference to the node corresponding to the given tool
+ /// name. Returns 0 on error.
+ Node* getNode(const std::string& ToolName);
+ const Node* getNode(const std::string& ToolName) const;
+
+ /// viewGraph - This function is meant for use from the debugger. You can
+ /// just say 'call G->viewGraph()' and a ghostview window should pop up from
+ /// the program, displaying the compilation graph. This depends on there
+ /// being a 'dot' and 'gv' program in your path.
void viewGraph();
/// writeGraph - Write Graphviz .dot source file to the current direcotry.
- void writeGraph(const std::string& OutputFilename);
+ int writeGraph(const std::string& OutputFilename);
// GraphTraits support.
friend NodesIterator GraphBegin(CompilationGraph*);
@@ -167,16 +167,15 @@
// Helper functions.
/// getToolsVector - Return a reference to the list of tool names
- /// corresponding to the given language name. Throws
- /// std::runtime_error.
- const tools_vector_type& getToolsVector(const std::string& LangName) const;
-
- /// PassThroughGraph - Pass the input file through the toolchain
- /// starting at StartNode.
- void PassThroughGraph (const llvm::sys::Path& In, const Node* StartNode,
- const InputLanguagesSet& InLangs,
- const llvm::sys::Path& TempDir,
- const LanguageMap& LangMap) const;
+ /// corresponding to the given language name. Returns 0 on error.
+ const tools_vector_type* getToolsVector(const std::string& LangName) const;
+
+ /// PassThroughGraph - Pass the input file through the toolchain starting at
+ /// StartNode.
+ int PassThroughGraph (const llvm::sys::Path& In, const Node* StartNode,
+ const InputLanguagesSet& InLangs,
+ const llvm::sys::Path& TempDir,
+ const LanguageMap& LangMap) const;
/// FindToolChain - Find head of the toolchain corresponding to
/// the given file.
@@ -185,26 +184,32 @@
InputLanguagesSet& InLangs,
const LanguageMap& LangMap) const;
- /// BuildInitial - Traverse the initial parts of the toolchains.
- void BuildInitial(InputLanguagesSet& InLangs,
- const llvm::sys::Path& TempDir,
- const LanguageMap& LangMap);
-
- /// TopologicalSort - Sort the nodes in topological order.
- void TopologicalSort(std::vector<const Node*>& Out);
- /// TopologicalSortFilterJoinNodes - Call TopologicalSort and
- /// filter the resulting list to include only Join nodes.
- void TopologicalSortFilterJoinNodes(std::vector<const Node*>& Out);
+ /// BuildInitial - Traverse the initial parts of the toolchains. Returns
+ /// non-zero value on error.
+ int BuildInitial(InputLanguagesSet& InLangs,
+ const llvm::sys::Path& TempDir,
+ const LanguageMap& LangMap);
+
+ /// TopologicalSort - Sort the nodes in topological order. Returns non-zero
+ /// value on error.
+ int TopologicalSort(std::vector<const Node*>& Out);
+ /// TopologicalSortFilterJoinNodes - Call TopologicalSort and filter the
+ /// resulting list to include only Join nodes. Returns non-zero value on
+ /// error.
+ int TopologicalSortFilterJoinNodes(std::vector<const Node*>& Out);
// Functions used to implement Check().
- /// CheckLanguageNames - Check that output/input language names
- /// match for all nodes.
+ /// CheckLanguageNames - Check that output/input language names match for
+ /// all nodes. Returns non-zero value on error (number of errors
+ /// encountered).
int CheckLanguageNames() const;
- /// CheckMultipleDefaultEdges - check that there are no multiple
- /// default default edges.
+ /// CheckMultipleDefaultEdges - check that there are no multiple default
+ /// default edges. Returns non-zero value on error (number of errors
+ /// encountered).
int CheckMultipleDefaultEdges() const;
- /// CheckCycles - Check that there are no cycles in the graph.
+ /// CheckCycles - Check that there are no cycles in the graph. Returns
+ /// non-zero value on error (number of errors encountered).
int CheckCycles();
};
@@ -270,7 +275,7 @@
}
inline pointer operator*() const {
- return &OwningGraph->getNode((*EdgeIter)->ToolName());
+ return OwningGraph->getNode((*EdgeIter)->ToolName());
}
inline pointer operator->() const {
return this->operator*();
@@ -301,7 +306,7 @@
typedef llvmc::NodeChildIterator ChildIteratorType;
static NodeType* getEntryNode(GraphType* G) {
- return &G->getNode("root");
+ return G->getNode("root");
}
static ChildIteratorType child_begin(NodeType* N) {
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/Error.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/Error.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/Error.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/Error.h Sat Jul 31 19:59:02 2010
@@ -7,28 +7,22 @@
//
//===----------------------------------------------------------------------===//
//
-// Exception classes for llvmc.
+// Error handling.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_INCLUDE_COMPILER_DRIVER_ERROR_H
#define LLVM_INCLUDE_COMPILER_DRIVER_ERROR_H
-#include <stdexcept>
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/raw_ostream.h"
namespace llvmc {
- /// error_code - This gets thrown during the compilation process if a tool
- /// invocation returns a non-zero exit code.
- class error_code: public std::runtime_error {
- int Code_;
- public:
- error_code (int c)
- : std::runtime_error("Tool returned error code"), Code_(c)
- {}
-
- int code() const { return Code_; }
- };
+ inline void PrintError(llvm::StringRef Err) {
+ extern const char* ProgramName;
+ llvm::errs() << ProgramName << ": " << Err << '\n';
+ }
}
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/Plugin.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/Plugin.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/Plugin.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/Plugin.h Sat Jul 31 19:59:02 2010
@@ -32,15 +32,15 @@
/// PreprocessOptions - The auto-generated function that performs various
/// consistency checks on options (like ensuring that -O2 and -O3 are not
/// used together).
- virtual void PreprocessOptions() const = 0;
+ virtual int PreprocessOptions() const = 0;
/// PopulateLanguageMap - The auto-generated function that fills in
/// the language map (map from file extensions to language names).
- virtual void PopulateLanguageMap(LanguageMap&) const = 0;
+ virtual int PopulateLanguageMap(LanguageMap&) const = 0;
/// PopulateCompilationGraph - The auto-generated function that
/// populates the compilation graph with nodes and edges.
- virtual void PopulateCompilationGraph(CompilationGraph&) const = 0;
+ virtual int PopulateCompilationGraph(CompilationGraph&) const = 0;
/// Needed to avoid a compiler warning.
virtual ~BasePlugin() {}
@@ -68,7 +68,7 @@
/// RunInitialization - Calls PreprocessOptions, PopulateLanguageMap and
/// PopulateCompilationGraph methods of all plugins. This populates the
/// global language map and the compilation graph.
- void RunInitialization(LanguageMap& langMap, CompilationGraph& graph) const;
+ int RunInitialization(LanguageMap& langMap, CompilationGraph& graph) const;
private:
// noncopyable
Modified: llvm/branches/wendling/eh/include/llvm/CompilerDriver/Tool.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/CompilerDriver/Tool.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/CompilerDriver/Tool.h (original)
+++ llvm/branches/wendling/eh/include/llvm/CompilerDriver/Tool.h Sat Jul 31 19:59:02 2010
@@ -38,17 +38,23 @@
virtual ~Tool() {}
- virtual Action GenerateAction (const PathVector& inFiles,
- bool HasChildren,
- const llvm::sys::Path& TempDir,
- const InputLanguagesSet& InLangs,
- const LanguageMap& LangMap) const = 0;
-
- virtual Action GenerateAction (const llvm::sys::Path& inFile,
- bool HasChildren,
- const llvm::sys::Path& TempDir,
- const InputLanguagesSet& InLangs,
- const LanguageMap& LangMap) const = 0;
+ /// GenerateAction - Generate an Action given particular command-line
+ /// options. Returns non-zero value on error.
+ virtual int GenerateAction (Action& Out,
+ const PathVector& inFiles,
+ const bool HasChildren,
+ const llvm::sys::Path& TempDir,
+ const InputLanguagesSet& InLangs,
+ const LanguageMap& LangMap) const = 0;
+
+ /// GenerateAction - Generate an Action given particular command-line
+ /// options. Returns non-zero value on error.
+ virtual int GenerateAction (Action& Out,
+ const llvm::sys::Path& inFile,
+ const bool HasChildren,
+ const llvm::sys::Path& TempDir,
+ const InputLanguagesSet& InLangs,
+ const LanguageMap& LangMap) const = 0;
virtual const char* Name() const = 0;
virtual const char** InputLanguages() const = 0;
@@ -74,11 +80,13 @@
void ClearJoinList() { JoinList_.clear(); }
bool JoinListEmpty() const { return JoinList_.empty(); }
- Action GenerateAction(bool HasChildren,
- const llvm::sys::Path& TempDir,
- const InputLanguagesSet& InLangs,
- const LanguageMap& LangMap) const {
- return GenerateAction(JoinList_, HasChildren, TempDir, InLangs, LangMap);
+ int GenerateAction(Action& Out,
+ const bool HasChildren,
+ const llvm::sys::Path& TempDir,
+ const InputLanguagesSet& InLangs,
+ const LanguageMap& LangMap) const {
+ return GenerateAction(Out, JoinList_, HasChildren, TempDir, InLangs,
+ LangMap);
}
// We shouldn't shadow base class's version of GenerateAction.
using Tool::GenerateAction;
Modified: llvm/branches/wendling/eh/include/llvm/Config/config.h.in
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Config/config.h.in?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Config/config.h.in (original)
+++ llvm/branches/wendling/eh/include/llvm/Config/config.h.in Sat Jul 31 19:59:02 2010
@@ -145,6 +145,9 @@
/* Define to 1 if you have the `getrusage' function. */
#undef HAVE_GETRUSAGE
+/* Have Darwin getsect() support */
+#undef HAVE_GETSECT
+
/* Define to 1 if you have the `gettimeofday' function. */
#undef HAVE_GETTIMEOFDAY
@@ -218,6 +221,9 @@
/* Define to 1 if you have the <mach-o/dyld.h> header file. */
#undef HAVE_MACH_O_DYLD_H
+/* Define to 1 if you have the <mach-o/getsect.h> header file. */
+#undef HAVE_MACH_O_GETSECT_H
+
/* Define if mallinfo() is available on this platform. */
#undef HAVE_MALLINFO
Modified: llvm/branches/wendling/eh/include/llvm/DerivedTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/DerivedTypes.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/DerivedTypes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/DerivedTypes.h Sat Jul 31 19:59:02 2010
@@ -52,10 +52,6 @@
///
void dropAllTypeUses();
- /// unlockedRefineAbstractTypeTo - Internal version of refineAbstractTypeTo
- /// that performs no locking. Only used for internal recursion.
- void unlockedRefineAbstractTypeTo(const Type *NewType);
-
public:
//===--------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/include/llvm/ExecutionEngine/JITMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ExecutionEngine/JITMemoryManager.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ExecutionEngine/JITMemoryManager.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ExecutionEngine/JITMemoryManager.h Sat Jul 31 19:59:02 2010
@@ -29,10 +29,9 @@
class JITMemoryManager {
protected:
bool HasGOT;
- bool SizeRequired;
public:
- JITMemoryManager() : HasGOT(false), SizeRequired(false) {}
+ JITMemoryManager() : HasGOT(false) {}
virtual ~JITMemoryManager();
/// CreateDefaultMemManager - This is used to create the default
@@ -71,12 +70,6 @@
/// return a pointer to its base.
virtual uint8_t *getGOTBase() const = 0;
- /// NeedsExactSize - If the memory manager requires to know the size of the
- /// objects to be emitted
- bool NeedsExactSize() const {
- return SizeRequired;
- }
-
//===--------------------------------------------------------------------===//
// Main Allocation Functions
//===--------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/include/llvm/GlobalValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/GlobalValue.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/GlobalValue.h (original)
+++ llvm/branches/wendling/eh/include/llvm/GlobalValue.h Sat Jul 31 19:59:02 2010
@@ -74,11 +74,10 @@
removeDeadConstantUsers(); // remove any dead constants using this.
}
- unsigned getAlignment() const { return Alignment; }
- void setAlignment(unsigned Align) {
- assert((Align & (Align-1)) == 0 && "Alignment is not a power of 2!");
- Alignment = Align;
+ unsigned getAlignment() const {
+ return (1u << Alignment) >> 1;
}
+ void setAlignment(unsigned Align);
VisibilityTypes getVisibility() const { return VisibilityTypes(Visibility); }
bool hasDefaultVisibility() const { return Visibility == DefaultVisibility; }
Modified: llvm/branches/wendling/eh/include/llvm/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Instruction.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Instruction.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Instruction.h Sat Jul 31 19:59:02 2010
@@ -170,16 +170,6 @@
void setMetadata(unsigned KindID, MDNode *Node);
void setMetadata(const char *Kind, MDNode *Node);
- /// setDbgMetadata - This is just an optimized helper function that is
- /// equivalent to setMetadata("dbg", Node);
- void setDbgMetadata(MDNode *Node);
-
- /// getDbgMetadata - This is just an optimized helper function that is
- /// equivalent to calling getMetadata("dbg").
- MDNode *getDbgMetadata() const {
- return DbgLoc.getAsMDNode(getContext());
- }
-
/// setDebugLoc - Set the debug location information for this instruction.
void setDebugLoc(const DebugLoc &Loc) { DbgLoc = Loc; }
@@ -199,7 +189,7 @@
void getAllMetadataImpl(SmallVectorImpl<std::pair<unsigned,MDNode*> > &)const;
void getAllMetadataOtherThanDebugLocImpl(SmallVectorImpl<std::pair<unsigned,
MDNode*> > &) const;
- void removeAllMetadata();
+ void clearMetadataHashEntries();
public:
//===--------------------------------------------------------------------===//
// Predicates and helper methods.
Modified: llvm/branches/wendling/eh/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Instructions.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Instructions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Instructions.h Sat Jul 31 19:59:02 2010
@@ -964,10 +964,14 @@
# undef protected
public:
- enum { ArgOffset = 0 }; ///< temporary, do not use for new code!
+ /// getNumArgOperands - Return the number of call arguments.
+ ///
unsigned getNumArgOperands() const { return getNumOperands() - 1; }
- Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
- void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
+
+ /// getArgOperand/setArgOperand - Return/set the i-th call argument.
+ ///
+ Value *getArgOperand(unsigned i) const { return getOperand(i); }
+ void setArgOperand(unsigned i, Value *v) { setOperand(i, v); }
/// getCallingConv/setCallingConv - Get or set the calling convention of this
/// function call.
@@ -1056,17 +1060,17 @@
/// indirect function invocation.
///
Function *getCalledFunction() const {
- return dyn_cast<Function>(Op<ArgOffset -1>());
+ return dyn_cast<Function>(Op<-1>());
}
/// getCalledValue - Get a pointer to the function that is invoked by this
/// instruction.
- const Value *getCalledValue() const { return Op<ArgOffset -1>(); }
- Value *getCalledValue() { return Op<ArgOffset -1>(); }
+ const Value *getCalledValue() const { return Op<-1>(); }
+ Value *getCalledValue() { return Op<-1>(); }
/// setCalledFunction - Set the function called.
void setCalledFunction(Value* Fn) {
- Op<ArgOffset -1>() = Fn;
+ Op<-1>() = Fn;
}
// Methods for support type inquiry through isa, cast, and dyn_cast:
@@ -2481,7 +2485,12 @@
/// Provide fast operand accessors
DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+ /// getNumArgOperands - Return the number of invoke arguments.
+ ///
unsigned getNumArgOperands() const { return getNumOperands() - 4; }
+
+ /// getArgOperand/setArgOperand - Return/set the i-th invoke argument.
+ ///
Value *getArgOperand(unsigned i) const { return getOperand(i); }
void setArgOperand(unsigned i, Value *v) { setOperand(i, v); }
@@ -2815,7 +2824,7 @@
TruncInst(
Value *S, ///< The value to be truncated
const Type *Ty, ///< The (smaller) type to truncate to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -2823,7 +2832,7 @@
TruncInst(
Value *S, ///< The value to be truncated
const Type *Ty, ///< The (smaller) type to truncate to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -2852,7 +2861,7 @@
ZExtInst(
Value *S, ///< The value to be zero extended
const Type *Ty, ///< The type to zero extend to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -2860,7 +2869,7 @@
ZExtInst(
Value *S, ///< The value to be zero extended
const Type *Ty, ///< The type to zero extend to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -2889,7 +2898,7 @@
SExtInst(
Value *S, ///< The value to be sign extended
const Type *Ty, ///< The type to sign extend to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -2897,7 +2906,7 @@
SExtInst(
Value *S, ///< The value to be sign extended
const Type *Ty, ///< The type to sign extend to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -2926,7 +2935,7 @@
FPTruncInst(
Value *S, ///< The value to be truncated
const Type *Ty, ///< The type to truncate to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -2934,7 +2943,7 @@
FPTruncInst(
Value *S, ///< The value to be truncated
const Type *Ty, ///< The type to truncate to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -2963,7 +2972,7 @@
FPExtInst(
Value *S, ///< The value to be extended
const Type *Ty, ///< The type to extend to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -2971,7 +2980,7 @@
FPExtInst(
Value *S, ///< The value to be extended
const Type *Ty, ///< The type to extend to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3000,7 +3009,7 @@
UIToFPInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3008,7 +3017,7 @@
UIToFPInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3037,7 +3046,7 @@
SIToFPInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3045,7 +3054,7 @@
SIToFPInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3074,7 +3083,7 @@
FPToUIInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3082,7 +3091,7 @@
FPToUIInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< Where to insert the new instruction
);
@@ -3111,7 +3120,7 @@
FPToSIInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3119,7 +3128,7 @@
FPToSIInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3144,7 +3153,7 @@
IntToPtrInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3152,7 +3161,7 @@
IntToPtrInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3184,7 +3193,7 @@
PtrToIntInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3192,7 +3201,7 @@
PtrToIntInst(
Value *S, ///< The value to be converted
const Type *Ty, ///< The type to convert to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
@@ -3221,7 +3230,7 @@
BitCastInst(
Value *S, ///< The value to be casted
const Type *Ty, ///< The type to casted to
- const Twine &NameStr = "", ///< A name for the new instruction
+ const Twine &NameStr = "", ///< A name for the new instruction
Instruction *InsertBefore = 0 ///< Where to insert the new instruction
);
@@ -3229,7 +3238,7 @@
BitCastInst(
Value *S, ///< The value to be casted
const Type *Ty, ///< The type to casted to
- const Twine &NameStr, ///< A name for the new instruction
+ const Twine &NameStr, ///< A name for the new instruction
BasicBlock *InsertAtEnd ///< The block to insert the instruction into
);
Modified: llvm/branches/wendling/eh/include/llvm/IntrinsicInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/IntrinsicInst.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/IntrinsicInst.h (original)
+++ llvm/branches/wendling/eh/include/llvm/IntrinsicInst.h Sat Jul 31 19:59:02 2010
@@ -103,7 +103,7 @@
Value *getValue();
uint64_t getOffset() const {
return cast<ConstantInt>(
- const_cast<Value*>(getArgOperand(1)))->getZExtValue();
+ const_cast<Value*>(getArgOperand(1)))->getZExtValue();
}
MDNode *getVariable() const { return cast<MDNode>(getArgOperand(2)); }
Modified: llvm/branches/wendling/eh/include/llvm/IntrinsicsARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/IntrinsicsARM.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/IntrinsicsARM.td (original)
+++ llvm/branches/wendling/eh/include/llvm/IntrinsicsARM.td Sat Jul 31 19:59:02 2010
@@ -21,6 +21,21 @@
}
//===----------------------------------------------------------------------===//
+// Saturating Arithmentic
+
+let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
+ def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, Commutative]>;
+ def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+ def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+ def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
+}
+
+//===----------------------------------------------------------------------===//
// Advanced SIMD (NEON)
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
Modified: llvm/branches/wendling/eh/include/llvm/LLVMContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/LLVMContext.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/LLVMContext.h (original)
+++ llvm/branches/wendling/eh/include/llvm/LLVMContext.h Sat Jul 31 19:59:02 2010
@@ -40,7 +40,7 @@
// Pinned metadata names, which always have the same value. This is a
// compile-time performance optimization, not a correctness optimization.
enum {
- MD_dbg = 1 // "dbg" -> 1.
+ MD_dbg = 0 // "dbg"
};
/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
@@ -48,8 +48,7 @@
unsigned getMDKindID(StringRef Name) const;
/// getMDKindNames - Populate client supplied SmallVector with the name for
- /// custom metadata IDs registered in this LLVMContext. ID #0 is not used,
- /// so it is filled in as an empty string.
+ /// custom metadata IDs registered in this LLVMContext.
void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;
/// setInlineAsmDiagnosticHandler - This method sets a handler that is invoked
Modified: llvm/branches/wendling/eh/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/LinkAllPasses.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/LinkAllPasses.h (original)
+++ llvm/branches/wendling/eh/include/llvm/LinkAllPasses.h Sat Jul 31 19:59:02 2010
@@ -22,6 +22,7 @@
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/PointerTracking.h"
#include "llvm/Analysis/PostDominators.h"
+#include "llvm/Analysis/RegionPrinter.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/Lint.h"
#include "llvm/Assembly/PrintModulePass.h"
@@ -106,6 +107,11 @@
(void) llvm::createPostDomOnlyViewerPass();
(void) llvm::createPostDomViewerPass();
(void) llvm::createReassociatePass();
+ (void) llvm::createRegionInfoPass();
+ (void) llvm::createRegionOnlyPrinterPass();
+ (void) llvm::createRegionOnlyViewerPass();
+ (void) llvm::createRegionPrinterPass();
+ (void) llvm::createRegionViewerPass();
(void) llvm::createSCCPPass();
(void) llvm::createScalarReplAggregatesPass();
(void) llvm::createSimplifyLibCallsPass();
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCAssembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCAssembler.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCAssembler.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCAssembler.h Sat Jul 31 19:59:02 2010
@@ -87,6 +87,7 @@
public:
// Only for sentinel.
MCFragment();
+ virtual ~MCFragment();
FragmentType getKind() const { return Kind; }
@@ -669,7 +670,9 @@
MCCodeEmitter &getEmitter() const { return Emitter; }
/// Finish - Do final processing and write the object to the output stream.
- void Finish();
+ /// \arg Writer is used for custom object writer (as the MCJIT does),
+ /// if not specified it is automatically created from backend.
+ void Finish(MCObjectWriter *Writer = 0);
// FIXME: This does not belong here.
bool getSubsectionsViaSymbols() const {
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCContext.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCContext.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCContext.h Sat Jul 31 19:59:02 2010
@@ -15,6 +15,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/raw_ostream.h"
+#include <vector> // FIXME: Shouldn't be needed.
namespace llvm {
class MCAsmInfo;
@@ -22,6 +23,7 @@
class MCSection;
class MCSymbol;
class MCLabel;
+ class MCDwarfFile;
class StringRef;
class Twine;
class MCSectionMachO;
@@ -66,6 +68,10 @@
/// .secure_log_reset appearing between them.
bool SecureLogUsed;
+ /// The dwarf file and directory tables from the dwarf .file directive.
+ std::vector<MCDwarfFile *> MCDwarfFiles;
+ std::vector<StringRef> MCDwarfDirs;
+
/// Allocator - Allocator object used for creating machine code objects.
///
/// We use a bump pointer allocator to avoid the need to track all allocated
@@ -139,6 +145,18 @@
/// @}
+ /// @name Dwarf Managment
+ /// @{
+
+ /// GetDwarfFile - creates an entry in the dwarf file and directory tables.
+ unsigned GetDwarfFile(StringRef FileName, unsigned FileNumber);
+
+ const std::vector<MCDwarfFile *> &getMCDwarfFiles() {
+ return MCDwarfFiles;
+ }
+
+ /// @}
+
char *getSecureLogFile() { return SecureLogFile; }
raw_ostream *getSecureLog() { return SecureLog; }
bool getSecureLogUsed() { return SecureLogUsed; }
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCObjectStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCObjectStreamer.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCObjectStreamer.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCObjectStreamer.h Sat Jul 31 19:59:02 2010
@@ -16,6 +16,9 @@
class MCAssembler;
class MCCodeEmitter;
class MCSectionData;
+class MCExpr;
+class MCFragment;
+class MCDataFragment;
class TargetAsmBackend;
class raw_ostream;
@@ -39,6 +42,14 @@
return CurSectionData;
}
+ MCFragment *getCurrentFragment() const;
+
+ /// Get a data fragment to write into, creating a new one if the current
+ /// fragment is not a data fragment.
+ MCDataFragment *getOrCreateDataFragment() const;
+
+ const MCExpr *AddValueSymbols(const MCExpr *Value);
+
public:
MCAssembler &getAssembler() { return *Assembler; }
Removed: llvm/branches/wendling/eh/include/llvm/MC/MCParser/AsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCParser/AsmParser.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCParser/AsmParser.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCParser/AsmParser.h (removed)
@@ -1,152 +0,0 @@
-//===- AsmParser.h - Parser for Assembly Files ------------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This class declares the parser for assembly files.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ASMPARSER_H
-#define ASMPARSER_H
-
-#include "llvm/MC/MCParser/AsmLexer.h"
-#include "llvm/MC/MCParser/AsmCond.h"
-#include "llvm/MC/MCParser/MCAsmParser.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/ADT/StringMap.h"
-#include <vector>
-
-namespace llvm {
-class AsmCond;
-class AsmToken;
-class MCAsmParserExtension;
-class MCContext;
-class MCExpr;
-class MCInst;
-class MCStreamer;
-class MCAsmInfo;
-class SourceMgr;
-class TargetAsmParser;
-class Twine;
-
-class AsmParser : public MCAsmParser {
- AsmParser(const AsmParser &); // DO NOT IMPLEMENT
- void operator=(const AsmParser &); // DO NOT IMPLEMENT
-private:
- AsmLexer Lexer;
- MCContext &Ctx;
- MCStreamer &Out;
- SourceMgr &SrcMgr;
- MCAsmParserExtension *GenericParser;
- MCAsmParserExtension *PlatformParser;
- TargetAsmParser *TargetParser;
-
- /// This is the current buffer index we're lexing from as managed by the
- /// SourceMgr object.
- int CurBuffer;
-
- AsmCond TheCondState;
- std::vector<AsmCond> TheCondStack;
-
- /// DirectiveMap - This is a table handlers for directives. Each handler is
- /// invoked after the directive identifier is read and is responsible for
- /// parsing and validating the rest of the directive. The handler is passed
- /// in the directive name and the location of the directive keyword.
- StringMap<std::pair<MCAsmParserExtension*, DirectiveHandler> > DirectiveMap;
-public:
- AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
- const MCAsmInfo &MAI);
- ~AsmParser();
-
- bool Run(bool NoInitialTextSection, bool NoFinalize = false);
-
- void AddDirectiveHandler(MCAsmParserExtension *Object,
- StringRef Directive,
- DirectiveHandler Handler) {
- DirectiveMap[Directive] = std::make_pair(Object, Handler);
- }
-
-public:
- TargetAsmParser &getTargetParser() const { return *TargetParser; }
- void setTargetParser(TargetAsmParser &P);
-
- /// @name MCAsmParser Interface
- /// {
-
- virtual SourceMgr &getSourceManager() { return SrcMgr; }
- virtual MCAsmLexer &getLexer() { return Lexer; }
- virtual MCContext &getContext() { return Ctx; }
- virtual MCStreamer &getStreamer() { return Out; }
-
- virtual void Warning(SMLoc L, const Twine &Meg);
- virtual bool Error(SMLoc L, const Twine &Msg);
-
- const AsmToken &Lex();
-
- bool ParseExpression(const MCExpr *&Res);
- virtual bool ParseExpression(const MCExpr *&Res, SMLoc &EndLoc);
- virtual bool ParseParenExpression(const MCExpr *&Res, SMLoc &EndLoc);
- virtual bool ParseAbsoluteExpression(int64_t &Res);
-
- /// }
-
-private:
- bool ParseStatement();
-
- void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const;
-
- /// EnterIncludeFile - Enter the specified file. This returns true on failure.
- bool EnterIncludeFile(const std::string &Filename);
-
- void EatToEndOfStatement();
-
- bool ParseAssignment(StringRef Name);
-
- bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc);
- bool ParseBinOpRHS(unsigned Precedence, const MCExpr *&Res, SMLoc &EndLoc);
- bool ParseParenExpr(const MCExpr *&Res, SMLoc &EndLoc);
-
- /// ParseIdentifier - Parse an identifier or string (as a quoted identifier)
- /// and set \arg Res to the identifier contents.
- bool ParseIdentifier(StringRef &Res);
-
- // Directive Parsing.
- bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz"
- bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ...
- bool ParseDirectiveFill(); // ".fill"
- bool ParseDirectiveSpace(); // ".space"
- bool ParseDirectiveSet(); // ".set"
- bool ParseDirectiveOrg(); // ".org"
- // ".align{,32}", ".p2align{,w,l}"
- bool ParseDirectiveAlign(bool IsPow2, unsigned ValueSize);
-
- /// ParseDirectiveSymbolAttribute - Parse a directive like ".globl" which
- /// accepts a single symbol (which should be a label or an external).
- bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr);
- bool ParseDirectiveELFType(); // ELF specific ".type"
-
- bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm"
-
- bool ParseDirectiveAbort(); // ".abort"
- bool ParseDirectiveInclude(); // ".include"
-
- bool ParseDirectiveIf(SMLoc DirectiveLoc); // ".if"
- bool ParseDirectiveElseIf(SMLoc DirectiveLoc); // ".elseif"
- bool ParseDirectiveElse(SMLoc DirectiveLoc); // ".else"
- bool ParseDirectiveEndIf(SMLoc DirectiveLoc); // .endif
-
- /// ParseEscapedString - Parse the current token as a string which may include
- /// escaped characters and return the string contents.
- bool ParseEscapedString(std::string &Data);
-};
-
-} // end namespace llvm
-
-#endif
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParser.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParser.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParser.h Sat Jul 31 19:59:02 2010
@@ -14,6 +14,7 @@
namespace llvm {
class AsmToken;
+class MCAsmInfo;
class MCAsmLexer;
class MCAsmParserExtension;
class MCContext;
@@ -22,17 +23,22 @@
class SMLoc;
class SourceMgr;
class StringRef;
+class Target;
+class TargetAsmParser;
class Twine;
/// MCAsmParser - Generic assembler parser interface, for use by target specific
/// assembly parsers.
class MCAsmParser {
public:
- typedef bool (MCAsmParserExtension::*DirectiveHandler)(StringRef, SMLoc);
+ typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc);
private:
MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT
void operator=(const MCAsmParser &); // DO NOT IMPLEMENT
+
+ TargetAsmParser *TargetParser;
+
protected: // Can only create subclasses.
MCAsmParser();
@@ -52,6 +58,12 @@
/// getStreamer - Return the output streamer for the assembler.
virtual MCStreamer &getStreamer() = 0;
+ TargetAsmParser &getTargetParser() const { return *TargetParser; }
+ void setTargetParser(TargetAsmParser &P);
+
+ /// Run - Run the parser on the input source buffer.
+ virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;
+
/// Warning - Emit a warning at the location \arg L, with the message \arg
/// Msg.
virtual void Warning(SMLoc L, const Twine &Msg) = 0;
@@ -71,12 +83,17 @@
const AsmToken &getTok();
/// \brief Report an error at the current lexer location.
- bool TokError(const char *Msg);
+ bool TokError(const Twine &Msg);
/// ParseIdentifier - Parse an identifier or string (as a quoted identifier)
/// and set \arg Res to the identifier contents.
virtual bool ParseIdentifier(StringRef &Res) = 0;
+ /// \brief Parse up to the end of statement and return the contents from the
+ /// current token until the end of the statement; the current token on exit
+ /// will be either the EndOfStatement or EOF.
+ virtual StringRef ParseStringToEndOfStatement() = 0;
+
/// ParseExpression - Parse an arbitrary expression.
///
/// @param Res - The value of the expression. The result is undefined
@@ -102,6 +119,10 @@
virtual bool ParseAbsoluteExpression(int64_t &Res) = 0;
};
+/// \brief Create an MCAsmParser instance.
+MCAsmParser *createMCAsmParser(const Target &, SourceMgr &, MCContext &,
+ MCStreamer &, const MCAsmInfo &);
+
} // End llvm namespace
#endif
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParserExtension.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParserExtension.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCParser/MCAsmParserExtension.h Sat Jul 31 19:59:02 2010
@@ -11,9 +11,11 @@
#define LLVM_MC_MCASMPARSEREXTENSION_H
#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/ADT/StringRef.h"
#include "llvm/Support/SMLoc.h"
namespace llvm {
+class Twine;
/// \brief Generic interface for extending the MCAsmParser,
/// which is implemented by target and object file assembly parser
@@ -27,6 +29,15 @@
protected:
MCAsmParserExtension();
+ // Helper template for implementing static dispatch functions.
+ template<typename T, bool (T::*Handler)(StringRef, SMLoc)>
+ static bool HandleDirective(MCAsmParserExtension *Target,
+ StringRef Directive,
+ SMLoc DirectiveLoc) {
+ T *Obj = static_cast<T*>(Target);
+ return (Obj->*Handler)(Directive, DirectiveLoc);
+ }
+
public:
virtual ~MCAsmParserExtension();
@@ -49,15 +60,14 @@
bool Error(SMLoc L, const Twine &Msg) {
return getParser().Error(L, Msg);
}
+ bool TokError(const Twine &Msg) {
+ return getParser().TokError(Msg);
+ }
const AsmToken &Lex() { return getParser().Lex(); }
const AsmToken &getTok() { return getParser().getTok(); }
- bool TokError(const char *Msg) {
- return getParser().TokError(Msg);
- }
-
/// @}
};
Modified: llvm/branches/wendling/eh/include/llvm/MC/MCStreamer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/MC/MCStreamer.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/MC/MCStreamer.h (original)
+++ llvm/branches/wendling/eh/include/llvm/MC/MCStreamer.h Sat Jul 31 19:59:02 2010
@@ -331,7 +331,7 @@
/// InstPrint.
///
/// \param CE - If given, a code emitter to use to show the instruction
- /// encoding inline with the assembly.
+ /// encoding inline with the assembly. This method takes ownership of \arg CE.
///
/// \param ShowInst - Whether to show the MCInst representation inline with
/// the assembly.
@@ -343,15 +343,20 @@
/// createMachOStreamer - Create a machine code streamer which will generate
/// Mach-O format object files.
+ ///
+ /// Takes ownership of \arg TAB and \arg CE.
MCStreamer *createMachOStreamer(MCContext &Ctx, TargetAsmBackend &TAB,
raw_ostream &OS, MCCodeEmitter *CE,
bool RelaxAll = false);
/// createWinCOFFStreamer - Create a machine code streamer which will
/// generate Microsoft COFF format object files.
+ ///
+ /// Takes ownership of \arg TAB and \arg CE.
MCStreamer *createWinCOFFStreamer(MCContext &Ctx,
TargetAsmBackend &TAB,
- MCCodeEmitter &CE, raw_ostream &OS);
+ MCCodeEmitter &CE, raw_ostream &OS,
+ bool RelaxAll = false);
/// createLoggingStreamer - Create a machine code streamer which just logs the
/// API calls and then dispatches to another streamer.
Modified: llvm/branches/wendling/eh/include/llvm/Metadata.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Metadata.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Metadata.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Metadata.h Sat Jul 31 19:59:02 2010
@@ -149,9 +149,6 @@
// critical code because it recursively visits all the MDNode's operands.
const Function *getFunction() const;
- // destroy - Delete this node. Only when there are no uses.
- void destroy();
-
/// Profile - calculate a unique identifier for this MDNode to collapse
/// duplicates
void Profile(FoldingSetNodeID &ID) const;
@@ -162,6 +159,9 @@
return V->getValueID() == MDNodeVal;
}
private:
+ // destroy - Delete this node. Only when there are no uses.
+ void destroy();
+
bool isNotUniqued() const {
return (getSubclassDataFromValue() & NotUniquedBit) != 0;
}
@@ -177,29 +177,23 @@
//===----------------------------------------------------------------------===//
/// NamedMDNode - a tuple of MDNodes.
/// NamedMDNode is always named. All NamedMDNode operand has a type of metadata.
-class NamedMDNode : public Value, public ilist_node<NamedMDNode> {
+class NamedMDNode : public ilist_node<NamedMDNode> {
friend class SymbolTableListTraits<NamedMDNode, Module>;
friend struct ilist_traits<NamedMDNode>;
friend class LLVMContextImpl;
+ friend class Module;
NamedMDNode(const NamedMDNode &); // DO NOT IMPLEMENT
std::string Name;
Module *Parent;
- void *Operands; // SmallVector<WeakVH<MDNode>, 4>
+ void *Operands; // SmallVector<TrackingVH<MDNode>, 4>
void setParent(Module *M) { Parent = M; }
-protected:
- explicit NamedMDNode(LLVMContext &C, const Twine &N, MDNode*const *Vals,
- unsigned NumVals, Module *M = 0);
-public:
- static NamedMDNode *Create(LLVMContext &C, const Twine &N,
- MDNode *const *MDs,
- unsigned NumMDs, Module *M = 0) {
- return new NamedMDNode(C, N, MDs, NumMDs, M);
- }
- static NamedMDNode *Create(const NamedMDNode *NMD, Module *M = 0);
+protected:
+ explicit NamedMDNode(const Twine &N);
+public:
/// eraseFromParent - Drop all references and remove the node from parent
/// module.
void eraseFromParent();
@@ -223,17 +217,11 @@
/// addOperand - Add metadata operand.
void addOperand(MDNode *M);
- /// setName - Set the name of this named metadata.
- void setName(const Twine &NewName);
-
/// getName - Return a constant reference to this named metadata's name.
StringRef getName() const;
- /// Methods for support type inquiry through isa, cast, and dyn_cast:
- static inline bool classof(const NamedMDNode *) { return true; }
- static bool classof(const Value *V) {
- return V->getValueID() == NamedMDNodeVal;
- }
+ /// print - Implement operator<< on NamedMDNode.
+ void print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW = 0) const;
};
} // end llvm namespace
Modified: llvm/branches/wendling/eh/include/llvm/Module.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Module.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Module.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Module.h Sat Jul 31 19:59:02 2010
@@ -28,7 +28,6 @@
class FunctionType;
class GVMaterializer;
class LLVMContext;
-class MDSymbolTable;
template<> struct ilist_traits<Function>
: public SymbolTableListTraits<Function, Module> {
@@ -61,7 +60,7 @@
};
template<> struct ilist_traits<NamedMDNode>
- : public SymbolTableListTraits<NamedMDNode, Module> {
+ : public ilist_default_traits<NamedMDNode> {
// createSentinel is used to get hold of a node that marks the end of
// the list...
NamedMDNode *createSentinel() const {
@@ -72,8 +71,8 @@
NamedMDNode *provideInitialHead() const { return createSentinel(); }
NamedMDNode *ensureHead(NamedMDNode*) const { return createSentinel(); }
static void noteHead(NamedMDNode*, NamedMDNode*) {}
- void addNodeToList(NamedMDNode *N);
- void removeNodeFromList(NamedMDNode *N);
+ void addNodeToList(NamedMDNode *) {}
+ void removeNodeFromList(NamedMDNode *) {}
private:
mutable ilist_node<NamedMDNode> Sentinel;
};
@@ -100,7 +99,7 @@
/// The type for the list of aliases.
typedef iplist<GlobalAlias> AliasListType;
/// The type for the list of named metadata.
- typedef iplist<NamedMDNode> NamedMDListType;
+ typedef ilist<NamedMDNode> NamedMDListType;
/// The type for the list of dependent libraries.
typedef std::vector<std::string> LibraryListType;
@@ -151,7 +150,7 @@
std::string ModuleID; ///< Human readable identifier for the module
std::string TargetTriple; ///< Platform target triple Module compiled on
std::string DataLayout; ///< Target data description
- MDSymbolTable *NamedMDSymTab; ///< NamedMDNode names.
+ void *NamedMDSymTab; ///< NamedMDNode names.
friend class Constant;
@@ -237,8 +236,7 @@
unsigned getMDKindID(StringRef Name) const;
/// getMDKindNames - Populate client supplied SmallVector with the name for
- /// custom metadata IDs registered in this LLVMContext. ID #0 is not used,
- /// so it is filled in as an empty string.
+ /// custom metadata IDs registered in this LLVMContext.
void getMDKindNames(SmallVectorImpl<StringRef> &Result) const;
/// @}
@@ -332,6 +330,10 @@
/// NamedMDNode with the specified name is not found.
NamedMDNode *getOrInsertNamedMetadata(StringRef Name);
+ /// eraseNamedMetadata - Remove the given NamedMDNode from this module
+ /// and delete it.
+ void eraseNamedMetadata(NamedMDNode *NMD);
+
/// @}
/// @name Type Accessors
/// @{
@@ -418,13 +420,6 @@
static iplist<GlobalAlias> Module::*getSublistAccess(GlobalAlias*) {
return &Module::AliasList;
}
- /// Get the Module's list of named metadata (constant).
- const NamedMDListType &getNamedMDList() const { return NamedMDList; }
- /// Get the Module's list of named metadata.
- NamedMDListType &getNamedMDList() { return NamedMDList; }
- static iplist<NamedMDNode> Module::*getSublistAccess(NamedMDNode *) {
- return &Module::NamedMDList;
- }
/// Get the symbol table of global variable and function identifiers
const ValueSymbolTable &getValueSymbolTable() const { return *ValSymTab; }
/// Get the Module's symbol table of global variable and function identifiers.
@@ -433,10 +428,6 @@
const TypeSymbolTable &getTypeSymbolTable() const { return *TypeSymTab; }
/// Get the Module's symbol table of types
TypeSymbolTable &getTypeSymbolTable() { return *TypeSymTab; }
- /// Get the symbol table of named metadata
- const MDSymbolTable &getMDSymbolTable() const { return *NamedMDSymTab; }
- /// Get the Module's symbol table of named metadata
- MDSymbolTable &getMDSymbolTable() { return *NamedMDSymTab; }
/// @}
/// @name Global Variable Iteration
Modified: llvm/branches/wendling/eh/include/llvm/PassSupport.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/PassSupport.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/PassSupport.h (original)
+++ llvm/branches/wendling/eh/include/llvm/PassSupport.h Sat Jul 31 19:59:02 2010
@@ -22,6 +22,7 @@
#define LLVM_PASS_SUPPORT_H
#include "Pass.h"
+#include "llvm/PassRegistry.h"
namespace llvm {
@@ -57,7 +58,7 @@
: PassName(name), PassArgument(arg), PassID(pi),
IsCFGOnlyPass(isCFGOnly),
IsAnalysis(is_analysis), IsAnalysisGroup(false), NormalCtor(normal) {
- registerPass();
+ PassRegistry::getPassRegistry()->registerPass(*this);
}
/// PassInfo ctor - Do not call this directly, this should only be invoked
/// through RegisterPass. This version is for use by analysis groups; it
@@ -126,15 +127,13 @@
return ItfImpl;
}
-protected:
- void registerPass();
- void unregisterPass();
-
private:
void operator=(const PassInfo &); // do not implement
PassInfo(const PassInfo &); // do not implement
};
+#define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \
+ static RegisterPass<passName> passName ## _info(arg, name, cfg, analysis)
template<typename PassName>
Pass *callDefaultCtor() { return new PassName(); }
@@ -165,6 +164,7 @@
: PassInfo(Name, PassArg, intptr_t(&passName::ID),
PassInfo::NormalCtor_t(callDefaultCtor<passName>),
CFGOnly, is_analysis) {
+
}
};
@@ -209,7 +209,9 @@
}
};
-
+#define INITIALIZE_AG_PASS(passName, agName, arg, name, cfg, analysis, def) \
+ static RegisterPass<passName> passName ## _info(arg, name, cfg, analysis); \
+ static RegisterAnalysisGroup<agName, def> passName ## _ag(passName ## _info)
//===---------------------------------------------------------------------------
/// PassRegistrationListener class - This class is meant to be derived from by
Modified: llvm/branches/wendling/eh/include/llvm/Support/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/COFF.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/COFF.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/COFF.h Sat Jul 31 19:59:02 2010
@@ -202,7 +202,7 @@
IMAGE_REL_I386_REL32 = 0x0014
};
- enum {
+ enum COMDATType {
IMAGE_COMDAT_SELECT_NODUPLICATES = 1,
IMAGE_COMDAT_SELECT_ANY,
IMAGE_COMDAT_SELECT_SAME_SIZE,
@@ -211,6 +211,58 @@
IMAGE_COMDAT_SELECT_LARGEST
};
+ // Auxiliary Symbol Formats
+ struct AuxiliaryFunctionDefinition {
+ uint32_t TagIndex;
+ uint32_t TotalSize;
+ uint32_t PointerToLinenumber;
+ uint32_t PointerToNextFunction;
+ uint8_t unused[2];
+ };
+
+ struct AuxiliarybfAndefSymbol {
+ uint8_t unused1[4];
+ uint16_t Linenumber;
+ uint8_t unused2[6];
+ uint32_t PointerToNextFunction;
+ uint8_t unused3[2];
+ };
+
+ struct AuxiliaryWeakExternal {
+ uint32_t TagIndex;
+ uint32_t Characteristics;
+ uint8_t unused[10];
+ };
+
+ /// These are not documented in the spec, but are located in WinNT.h.
+ enum WeakExternalCharacteristics {
+ IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY = 1,
+ IMAGE_WEAK_EXTERN_SEARCH_LIBRARY = 2,
+ IMAGE_WEAK_EXTERN_SEARCH_ALIAS = 3
+ };
+
+ struct AuxiliaryFile {
+ uint8_t FileName[18];
+ };
+
+ struct AuxiliarySectionDefinition {
+ uint32_t Length;
+ uint16_t NumberOfRelocations;
+ uint16_t NumberOfLinenumbers;
+ uint32_t CheckSum;
+ uint16_t Number;
+ uint8_t Selection;
+ uint8_t unused[3];
+ };
+
+ union Auxiliary {
+ AuxiliaryFunctionDefinition FunctionDefinition;
+ AuxiliarybfAndefSymbol bfAndefSymbol;
+ AuxiliaryWeakExternal WeakExternal;
+ AuxiliaryFile File;
+ AuxiliarySectionDefinition SectionDefinition;
+ };
+
} // End namespace llvm.
} // End namespace COFF.
Modified: llvm/branches/wendling/eh/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/CallSite.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/CallSite.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/CallSite.h Sat Jul 31 19:59:02 2010
@@ -49,13 +49,13 @@
PointerIntPair<InstrTy*, 1, bool> I;
public:
CallSiteBase() : I(0, false) {}
- CallSiteBase(CallTy *CI) : I(reinterpret_cast<InstrTy*>(CI), true) {}
- CallSiteBase(InvokeTy *II) : I(reinterpret_cast<InstrTy*>(II), false) {}
+ CallSiteBase(CallTy *CI) : I(CI, true) { assert(CI); }
+ CallSiteBase(InvokeTy *II) : I(II, false) { assert(II); }
CallSiteBase(ValTy *II) { *this = get(II); }
CallSiteBase(InstrTy *II) {
assert(II && "Null instruction given?");
*this = get(II);
- assert(I.getPointer());
+ assert(I.getPointer() && "Not a call?");
}
/// CallSiteBase::get - This static method is sort of like a constructor. It
@@ -66,9 +66,9 @@
static CallSiteBase get(ValTy *V) {
if (InstrTy *II = dyn_cast<InstrTy>(V)) {
if (II->getOpcode() == Instruction::Call)
- return CallSiteBase(reinterpret_cast<CallTy*>(II));
+ return CallSiteBase(static_cast<CallTy*>(II));
else if (II->getOpcode() == Instruction::Invoke)
- return CallSiteBase(reinterpret_cast<InvokeTy*>(II));
+ return CallSiteBase(static_cast<InvokeTy*>(II));
}
return CallSiteBase();
}
@@ -116,13 +116,13 @@
ValTy *getArgument(unsigned ArgNo) const {
assert(arg_begin() + ArgNo < arg_end() && "Argument # out of range!");
- return *(arg_begin()+ArgNo);
+ return *(arg_begin() + ArgNo);
}
void setArgument(unsigned ArgNo, Value* newVal) {
assert(getInstruction() && "Not a call or invoke instruction!");
assert(arg_begin() + ArgNo < arg_end() && "Argument # out of range!");
- getInstruction()->setOperand(getArgumentOffset() + ArgNo, newVal);
+ getInstruction()->setOperand(ArgNo, newVal);
}
/// Given a value use iterator, returns the argument that corresponds to it.
@@ -143,7 +143,7 @@
IterTy arg_begin() const {
assert(getInstruction() && "Not a call or invoke instruction!");
// Skip non-arguments
- return (*this)->op_begin() + getArgumentOffset();
+ return (*this)->op_begin();
}
IterTy arg_end() const { return (*this)->op_end() - getArgumentEndOffset(); }
@@ -253,17 +253,9 @@
}
private:
- /// Returns the operand number of the first argument
- unsigned getArgumentOffset() const {
- if (isCall())
- return CallInst::ArgOffset; // Skip Function (ATM)
- else
- return 0; // Args are at the front
- }
-
unsigned getArgumentEndOffset() const {
if (isCall())
- return CallInst::ArgOffset ? 0 : 1; // Unchanged (ATM)
+ return 1; // Skip Callee
else
// An invoke.
return 4; // Skip PersFn, BB, BB, Function
@@ -273,9 +265,7 @@
// FIXME: this is slow, since we do not have the fast versions of the op_*()
// functions here. See CallSite::getCallee.
if (isCall())
- return CallInst::ArgOffset
- ? getInstruction()->op_begin() // Unchanged
- : getInstruction()->op_end() - 1; // Skip Function
+ return getInstruction()->op_end() - 1; // Skip Callee
else
// An invoke.
return getInstruction()->op_end() - 4; // Skip PersFn, BB, BB, Function
@@ -299,6 +289,7 @@
public:
CallSite() {}
CallSite(Base B) : Base(B) {}
+ CallSite(Value* V) : Base(V) {}
CallSite(CallInst *CI) : Base(CI) {}
CallSite(InvokeInst *II) : Base(II) {}
CallSite(Instruction *II) : Base(II) {}
Modified: llvm/branches/wendling/eh/include/llvm/Support/Casting.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/Casting.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/Casting.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/Casting.h Sat Jul 31 19:59:02 2010
@@ -236,73 +236,6 @@
return (Val && isa<X>(Val)) ? cast<X, Y>(Val) : 0;
}
-
-#ifdef DEBUG_CAST_OPERATORS
-#include "llvm/Support/raw_ostream.h"
-
-struct bar {
- bar() {}
-private:
- bar(const bar &);
-};
-struct foo {
- void ext() const;
- /* static bool classof(const bar *X) {
- cerr << "Classof: " << X << "\n";
- return true;
- }*/
-};
-
-template <> struct isa_impl<foo,bar> {
- static inline bool doit(const bar &Val) {
- dbgs() << "Classof: " << &Val << "\n";
- return true;
- }
-};
-
-
-bar *fub();
-void test(bar &B1, const bar *B2) {
- // test various configurations of const
- const bar &B3 = B1;
- const bar *const B4 = B2;
-
- // test isa
- if (!isa<foo>(B1)) return;
- if (!isa<foo>(B2)) return;
- if (!isa<foo>(B3)) return;
- if (!isa<foo>(B4)) return;
-
- // test cast
- foo &F1 = cast<foo>(B1);
- const foo *F3 = cast<foo>(B2);
- const foo *F4 = cast<foo>(B2);
- const foo &F8 = cast<foo>(B3);
- const foo *F9 = cast<foo>(B4);
- foo *F10 = cast<foo>(fub());
-
- // test cast_or_null
- const foo *F11 = cast_or_null<foo>(B2);
- const foo *F12 = cast_or_null<foo>(B2);
- const foo *F13 = cast_or_null<foo>(B4);
- const foo *F14 = cast_or_null<foo>(fub()); // Shouldn't print.
-
- // These lines are errors...
- //foo *F20 = cast<foo>(B2); // Yields const foo*
- //foo &F21 = cast<foo>(B3); // Yields const foo&
- //foo *F22 = cast<foo>(B4); // Yields const foo*
- //foo &F23 = cast_or_null<foo>(B1);
- //const foo &F24 = cast_or_null<foo>(B3);
-}
-
-bar *fub() { return 0; }
-void main() {
- bar B;
- test(B, &B);
-}
-
-#endif
-
} // End llvm namespace
#endif
Modified: llvm/branches/wendling/eh/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/ELF.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/ELF.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/ELF.h Sat Jul 31 19:59:02 2010
@@ -257,22 +257,29 @@
// Section types.
enum {
- SHT_NULL = 0, // No associated section (inactive entry).
- SHT_PROGBITS = 1, // Program-defined contents.
- SHT_SYMTAB = 2, // Symbol table.
- SHT_STRTAB = 3, // String table.
- SHT_RELA = 4, // Relocation entries; explicit addends.
- SHT_HASH = 5, // Symbol hash table.
- SHT_DYNAMIC = 6, // Information for dynamic linking.
- SHT_NOTE = 7, // Information about the file.
- SHT_NOBITS = 8, // Data occupies no space in the file.
- SHT_REL = 9, // Relocation entries; no explicit addends.
- SHT_SHLIB = 10, // Reserved.
- SHT_DYNSYM = 11, // Symbol table.
- SHT_LOPROC = 0x70000000, // Lowest processor architecture-specific type.
- SHT_HIPROC = 0x7fffffff, // Highest processor architecture-specific type.
- SHT_LOUSER = 0x80000000, // Lowest type reserved for applications.
- SHT_HIUSER = 0xffffffff // Highest type reserved for applications.
+ SHT_NULL = 0, // No associated section (inactive entry).
+ SHT_PROGBITS = 1, // Program-defined contents.
+ SHT_SYMTAB = 2, // Symbol table.
+ SHT_STRTAB = 3, // String table.
+ SHT_RELA = 4, // Relocation entries; explicit addends.
+ SHT_HASH = 5, // Symbol hash table.
+ SHT_DYNAMIC = 6, // Information for dynamic linking.
+ SHT_NOTE = 7, // Information about the file.
+ SHT_NOBITS = 8, // Data occupies no space in the file.
+ SHT_REL = 9, // Relocation entries; no explicit addends.
+ SHT_SHLIB = 10, // Reserved.
+ SHT_DYNSYM = 11, // Symbol table.
+ SHT_INIT_ARRAY = 14, // Pointers to initialisation functions.
+ SHT_FINI_ARRAY = 15, // Pointers to termination functions.
+ SHT_PREINIT_ARRAY = 16, // Pointers to pre-init functions.
+ SHT_GROUP = 17, // Section group.
+ SHT_SYMTAB_SHNDX = 18, // Indicies for SHN_XINDEX entries.
+ SHT_LOOS = 0x60000000, // Lowest operating system-specific type.
+ SHT_HIOS = 0x6fffffff, // Highest operating system-specific type.
+ SHT_LOPROC = 0x70000000, // Lowest processor architecture-specific type.
+ SHT_HIPROC = 0x7fffffff, // Highest processor architecture-specific type.
+ SHT_LOUSER = 0x80000000, // Lowest type reserved for applications.
+ SHT_HIUSER = 0xffffffff // Highest type reserved for applications.
};
// Section flags.
@@ -339,10 +346,19 @@
STT_FUNC = 2, // Symbol is executable code (function, etc.)
STT_SECTION = 3, // Symbol refers to a section
STT_FILE = 4, // Local, absolute symbol that refers to a file
+ STT_COMMON = 5, // An uninitialised common block
+ STT_TLS = 6, // Thread local data object
STT_LOPROC = 13, // Lowest processor-specific symbol type
STT_HIPROC = 15 // Highest processor-specific symbol type
};
+enum {
+ STV_DEFAULT = 0, // Visibility is specified by binding type
+ STV_INTERNAL = 1, // Defined by processor supplements
+ STV_HIDDEN = 2, // Not visible to other components
+ STV_PROTECTED = 3 // Visible in other components but not preemptable
+};
+
// Relocation entry, without explicit addend.
struct Elf32_Rel {
Elf32_Addr r_offset; // Location (file byte offset, or program virtual addr)
@@ -356,7 +372,7 @@
void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
void setSymbolAndType(Elf32_Word s, unsigned char t) {
r_info = (s << 8) + t;
- };
+ }
};
// Relocation entry with explicit addend.
@@ -373,7 +389,7 @@
void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
void setSymbolAndType(Elf32_Word s, unsigned char t) {
r_info = (s << 8) + t;
- };
+ }
};
// Relocation entry, without explicit addend.
@@ -391,7 +407,7 @@
void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
void setSymbolAndType(Elf64_Xword s, unsigned char t) {
r_info = (s << 32) + (t&0xffffffffL);
- };
+ }
};
// Relocation entry with explicit addend.
@@ -410,7 +426,7 @@
void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
void setSymbolAndType(Elf64_Xword s, unsigned char t) {
r_info = (s << 32) + (t&0xffffffffL);
- };
+ }
};
// Program header for ELF32.
Modified: llvm/branches/wendling/eh/include/llvm/Support/GraphWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/GraphWriter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/GraphWriter.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/GraphWriter.h Sat Jul 31 19:59:02 2010
@@ -271,6 +271,12 @@
O << "[" << Attrs << "]";
O << ";\n";
}
+
+ /// getOStream - Get the raw output stream into the graph file. Useful to
+ /// write fancy things using addCustomGraphFeatures().
+ raw_ostream &getOStream() {
+ return O;
+ }
};
template<typename GraphType>
Modified: llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/IRBuilder.h Sat Jul 31 19:59:02 2010
@@ -165,41 +165,21 @@
}
/// getInt8 - Get a constant 8-bit value.
- ConstantInt *getInt8(int8_t C) {
- return ConstantInt::getSigned(getInt8Ty(), C);
- }
-
- /// getInt8 - Get a constant 8-bit value.
ConstantInt *getInt8(uint8_t C) {
return ConstantInt::get(getInt8Ty(), C);
}
/// getInt16 - Get a constant 16-bit value.
- ConstantInt *getInt16(int16_t C) {
- return ConstantInt::getSigned(getInt16Ty(), C);
- }
-
- /// getInt16 - Get a constant 16-bit value.
ConstantInt *getInt16(uint16_t C) {
return ConstantInt::get(getInt16Ty(), C);
}
/// getInt32 - Get a constant 32-bit value.
- ConstantInt *getInt32(int32_t C) {
- return ConstantInt::getSigned(getInt32Ty(), C);
- }
-
- /// getInt32 - Get a constant 32-bit value.
ConstantInt *getInt32(uint32_t C) {
return ConstantInt::get(getInt32Ty(), C);
}
/// getInt64 - Get a constant 64-bit value.
- ConstantInt *getInt64(int64_t C) {
- return ConstantInt::getSigned(getInt64Ty(), C);
- }
-
- /// getInt64 - Get a constant 64-bit value.
ConstantInt *getInt64(uint64_t C) {
return ConstantInt::get(getInt64Ty(), C);
}
Modified: llvm/branches/wendling/eh/include/llvm/Support/IRReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/IRReader.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/IRReader.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/IRReader.h Sat Jul 31 19:59:02 2010
@@ -79,10 +79,10 @@
(const unsigned char *)Buffer->getBufferEnd())) {
std::string ErrMsg;
Module *M = ParseBitcodeFile(Buffer, Context, &ErrMsg);
- // ParseBitcodeFile does not take ownership of the Buffer.
- delete Buffer;
if (M == 0)
Err = SMDiagnostic(Buffer->getBufferIdentifier(), ErrMsg);
+ // ParseBitcodeFile does not take ownership of the Buffer.
+ delete Buffer;
return M;
}
Modified: llvm/branches/wendling/eh/include/llvm/Support/MachO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/MachO.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/MachO.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/MachO.h Sat Jul 31 19:59:02 2010
@@ -14,11 +14,649 @@
#ifndef LLVM_SUPPORT_MACHO_H
#define LLVM_SUPPORT_MACHO_H
+#include "llvm/System/DataTypes.h"
+
// NOTE: The enums in this file are intentially named to be different than those
// in the headers in /usr/include/mach (on darwin systems) to avoid conflicts
// with those macros.
namespace llvm {
namespace MachO {
+ // Enums from <mach-o/loader.h>
+ enum {
+ // Constants for the "magic" field in llvm::MachO::mach_header and
+ // llvm::MachO::mach_header_64
+ HeaderMagic32 = 0xFEEDFACEu, // MH_MAGIC
+ HeaderMagic32Swapped = 0xCEFAEDFEu, // MH_CIGAM
+ HeaderMagic64 = 0xFEEDFACFu, // MH_MAGIC_64
+ HeaderMagic64Swapped = 0xCFFAEDFEu, // MH_CIGAM_64
+ UniversalMagic = 0xCAFEBABEu, // FAT_MAGIC
+ UniversalMagicSwapped = 0xBEBAFECAu, // FAT_CIGAM
+
+ // Constants for the "filetype" field in llvm::MachO::mach_header and
+ // llvm::MachO::mach_header_64
+ HeaderFileTypeObject = 0x1u, // MH_OBJECT
+ HeaderFileTypeExecutable = 0x2u, // MH_EXECUTE
+ HeaderFileTypeFixedVMShlib = 0x3u, // MH_FVMLIB
+ HeaderFileTypeCore = 0x4u, // MH_CORE
+ HeaderFileTypePreloadedExecutable = 0x5u, // MH_PRELOAD
+ HeaderFileTypeDynamicShlib = 0x6u, // MH_DYLIB
+ HeaderFileTypeDynamicLinkEditor = 0x7u, // MH_DYLINKER
+ HeaderFileTypeBundle = 0x8u, // MH_BUNDLE
+ HeaderFileTypeDynamicShlibStub = 0x9u, // MH_DYLIB_STUB
+ HeaderFileTypeDSYM = 0xAu, // MH_DSYM
+ HeaderFileTypeKextBundle = 0xBu, // MH_KEXT_BUNDLE
+
+ // Constant bits for the "flags" field in llvm::MachO::mach_header and
+ // llvm::MachO::mach_header_64
+ HeaderFlagBitNoUndefinedSymbols = 0x00000001u, // MH_NOUNDEFS
+ HeaderFlagBitIsIncrementalLinkObject= 0x00000002u, // MH_INCRLINK
+ HeaderFlagBitIsDynamicLinkObject = 0x00000004u, // MH_DYLDLINK
+ HeaderFlagBitBindAtLoad = 0x00000008u, // MH_BINDATLOAD
+ HeaderFlagBitPrebound = 0x00000010u, // MH_PREBOUND
+ HeaderFlagBitSplitSegments = 0x00000020u, // MH_SPLIT_SEGS
+ HeaderFlagBitLazyInit = 0x00000040u, // MH_LAZY_INIT
+ HeaderFlagBitTwoLevelNamespace = 0x00000080u, // MH_TWOLEVEL
+ HeaderFlagBitForceFlatNamespace = 0x00000100u, // MH_FORCE_FLAT
+ HeaderFlagBitNoMultipleDefintions = 0x00000200u, // MH_NOMULTIDEFS
+ HeaderFlagBitNoFixPrebinding = 0x00000400u, // MH_NOFIXPREBINDING
+ HeaderFlagBitPrebindable = 0x00000800u, // MH_PREBINDABLE
+ HeaderFlagBitAllModulesBound = 0x00001000u, // MH_ALLMODSBOUND
+ HeaderFlagBitSubsectionsViaSymbols = 0x00002000u, // MH_SUBSECTIONS_VIA_SYMBOLS
+ HeaderFlagBitCanonical = 0x00004000u, // MH_CANONICAL
+ HeaderFlagBitWeakDefines = 0x00008000u, // MH_WEAK_DEFINES
+ HeaderFlagBitBindsToWeak = 0x00010000u, // MH_BINDS_TO_WEAK
+ HeaderFlagBitAllowStackExecution = 0x00020000u, // MH_ALLOW_STACK_EXECUTION
+ HeaderFlagBitRootSafe = 0x00040000u, // MH_ROOT_SAFE
+ HeaderFlagBitSetUIDSafe = 0x00080000u, // MH_SETUID_SAFE
+ HeaderFlagBitNoReexportedDylibs = 0x00100000u, // MH_NO_REEXPORTED_DYLIBS
+ HeaderFlagBitPIE = 0x00200000u, // MH_PIE
+ HeaderFlagBitDeadStrippableDylib = 0x00400000u, // MH_DEAD_STRIPPABLE_DYLIB
+
+ // Constants for the "cmd" field in llvm::MachO::load_command
+ LoadCommandDynamicLinkerRequired = 0x80000000u, // LC_REQ_DYLD
+ LoadCommandSegment32 = 0x00000001u, // LC_SEGMENT
+ LoadCommandSymtab = 0x00000002u, // LC_SYMTAB
+ LoadCommandSymSeg = 0x00000003u, // LC_SYMSEG
+ LoadCommandThread = 0x00000004u, // LC_THREAD
+ LoadCommandUnixThread = 0x00000005u, // LC_UNIXTHREAD
+ LoadCommandFixedVMShlibLoad = 0x00000006u, // LC_LOADFVMLIB
+ LoadCommandFixedVMShlibIdent = 0x00000007u, // LC_IDFVMLIB
+ LoadCommandIdent = 0x00000008u, // LC_IDENT
+ LoadCommandFixedVMFileInclusion = 0x00000009u, // LC_FVMFILE
+ LoadCommandPrePage = 0x0000000Au, // LC_PREPAGE
+ LoadCommandDynamicSymtabInfo = 0x0000000Bu, // LC_DYSYMTAB
+ LoadCommandDylibLoad = 0x0000000Cu, // LC_LOAD_DYLIB
+ LoadCommandDylibIdent = 0x0000000Du, // LC_ID_DYLIB
+ LoadCommandDynamicLinkerLoad = 0x0000000Eu, // LC_LOAD_DYLINKER
+ LoadCommandDynamicLinkerIdent = 0x0000000Fu, // LC_ID_DYLINKER
+ LoadCommandDylibPrebound = 0x00000010u, // LC_PREBOUND_DYLIB
+ LoadCommandRoutines32 = 0x00000011u, // LC_ROUTINES
+ LoadCommandSubFramework = 0x00000012u, // LC_SUB_FRAMEWORK
+ LoadCommandSubUmbrella = 0x00000013u, // LC_SUB_UMBRELLA
+ LoadCommandSubClient = 0x00000014u, // LC_SUB_CLIENT
+ LoadCommandSubLibrary = 0x00000015u, // LC_SUB_LIBRARY
+ LoadCommandTwoLevelHints = 0x00000016u, // LC_TWOLEVEL_HINTS
+ LoadCommandPreBindChecksum = 0x00000017u, // LC_PREBIND_CKSUM
+ LoadCommandDylibLoadWeak = 0x80000018u, // LC_LOAD_WEAK_DYLIB
+ LoadCommandSegment64 = 0x00000019u, // LC_SEGMENT_64
+ LoadCommandRoutines64 = 0x0000001Au, // LC_ROUTINES_64
+ LoadCommandUUID = 0x0000001Bu, // LC_UUID
+ LoadCommandRunpath = 0x8000001Cu, // LC_RPATH
+ LoadCommandCodeSignature = 0x0000001Du, // LC_CODE_SIGNATURE
+ LoadCommandSegmentSplitInfo = 0x0000001Eu, // LC_SEGMENT_SPLIT_INFO
+ LoadCommandDylibReexport = 0x8000001Fu, // LC_REEXPORT_DYLIB
+ LoadCommandDylibLazyLoad = 0x00000020u, // LC_LAZY_LOAD_DYLIB
+ LoadCommandEncryptionInfo = 0x00000021u, // LC_ENCRYPTION_INFO
+ LoadCommandDynamicLinkerInfo = 0x00000022u, // LC_DYLD_INFO
+ LoadCommandDynamicLinkerInfoOnly = 0x80000022u, // LC_DYLD_INFO_ONLY
+ LoadCommandDylibLoadUpward = 0x80000023u, // LC_LOAD_UPWARD_DYLIB
+
+ // Constant bits for the "flags" field in llvm::MachO::segment_command
+ SegmentCommandFlagBitHighVM = 0x1u, // SG_HIGHVM
+ SegmentCommandFlagBitFixedVMLibrary = 0x2u, // SG_FVMLIB
+ SegmentCommandFlagBitNoRelocations = 0x4u, // SG_NORELOC
+ SegmentCommandFlagBitProtectedVersion1 = 0x8u, // SG_PROTECTED_VERSION_1
+
+
+ // Constant masks for the "flags" field in llvm::MachO::section and
+ // llvm::MachO::section_64
+ SectionFlagMaskSectionType = 0x000000ffu, // SECTION_TYPE
+ SectionFlagMaskAllAttributes = 0xffffff00u, // SECTION_ATTRIBUTES
+ SectionFlagMaskUserAttributes = 0xff000000u, // SECTION_ATTRIBUTES_USR
+ SectionFlagMaskSystemAttributes = 0x00ffff00u, // SECTION_ATTRIBUTES_SYS
+
+ // Constant masks for the "flags[7:0]" field in llvm::MachO::section and
+ // llvm::MachO::section_64 (mask "flags" with SECTION_TYPE)
+ SectionTypeRegular = 0x00u, // S_REGULAR
+ SectionTypeZeroFill = 0x01u, // S_ZEROFILL
+ SectionTypeCStringLiterals = 0x02u, // S_CSTRING_LITERALS
+ SectionType4ByteLiterals = 0x03u, // S_4BYTE_LITERALS
+ SectionType8ByteLiterals = 0x04u, // S_8BYTE_LITERALS
+ SectionTypeLiteralPointers = 0x05u, // S_LITERAL_POINTERS
+ SectionTypeNonLazySymbolPointers = 0x06u, // S_NON_LAZY_SYMBOL_POINTERS
+ SectionTypeLazySymbolPointers = 0x07u, // S_LAZY_SYMBOL_POINTERS
+ SectionTypeSymbolStubs = 0x08u, // S_SYMBOL_STUBS
+ SectionTypeModuleInitFunctionPointers = 0x09u, // S_MOD_INIT_FUNC_POINTERS
+ SectionTypeModuleTermFunctionPointers = 0x0au, // S_MOD_TERM_FUNC_POINTERS
+ SectionTypeCoalesced = 0x0bu, // S_COALESCED
+ SectionTypeZeroFillLarge = 0x0cu, // S_GB_ZEROFILL
+ SectionTypeInterposing = 0x0du, // S_INTERPOSING
+ SectionType16ByteLiterals = 0x0eu, // S_16BYTE_LITERALS
+ SectionTypeDTraceObjectFormat = 0x0fu, // S_DTRACE_DOF
+ SectionTypeLazyDylibSymbolPointers = 0x10u, // S_LAZY_DYLIB_SYMBOL_POINTERS
+
+ // Constant masks for the "flags[31:24]" field in llvm::MachO::section and
+ // llvm::MachO::section_64 (mask "flags" with SECTION_ATTRIBUTES_USR)
+ SectionAttrUserPureInstructions = 0x80000000u, // S_ATTR_PURE_INSTRUCTIONS
+ SectionAttrUserNoTableOfContents = 0x40000000u, // S_ATTR_NO_TOC
+ SectionAttrUserCanStripStaticSymbols = 0x20000000u, // S_ATTR_STRIP_STATIC_SYMS
+ SectionAttrUserNoDeadStrip = 0x10000000u, // S_ATTR_NO_DEAD_STRIP
+ SectionAttrUserLiveSupport = 0x08000000u, // S_ATTR_LIVE_SUPPORT
+ SectionAttrUserSelfModifyingCode = 0x04000000u, // S_ATTR_SELF_MODIFYING_CODE
+ SectionAttrUserDebug = 0x02000000u, // S_ATTR_DEBUG
+
+ // Constant masks for the "flags[23:8]" field in llvm::MachO::section and
+ // llvm::MachO::section_64 (mask "flags" with SECTION_ATTRIBUTES_SYS)
+ SectionAttrSytemSomeInstructions = 0x00000400u, // S_ATTR_SOME_INSTRUCTIONS
+ SectionAttrSytemHasExternalRelocations= 0x00000200u, // S_ATTR_EXT_RELOC
+ SectionAttrSytemHasLocalRelocations = 0x00000100u, // S_ATTR_LOC_RELOC
+
+ IndirectSymbolLocal = 0x80000000u, // INDIRECT_SYMBOL_LOCAL
+ IndirectSymbolAbsolute = 0x40000000u, // INDIRECT_SYMBOL_ABS
+
+ RebaseTypePointer = 1u, // REBASE_TYPE_POINTER
+ RebaseTypeTextAbsolute32 = 2u, // REBASE_TYPE_TEXT_ABSOLUTE32
+ RebaseTypeTextPCRelative32 = 3u, // REBASE_TYPE_TEXT_PCREL32
+
+ RebaseOpcodeMask = 0xF0u, // REBASE_OPCODE_MASK
+ RebaseImmediateMask = 0x0Fu, // REBASE_IMMEDIATE_MASK
+ RebaseOpcodeDone = 0x00u, // REBASE_OPCODE_DONE
+ RebaseOpcodeSetTypeImmediate = 0x10u, // REBASE_OPCODE_SET_TYPE_IMM
+ RebaseOpcodeSetSegmentAndOffsetULEB = 0x20u, // REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
+ RebaseOpcodeAddAddressULEB = 0x30u, // REBASE_OPCODE_ADD_ADDR_ULEB
+ RebaseOpcodeAddAddressImmediateScaled = 0x40u, // REBASE_OPCODE_ADD_ADDR_IMM_SCALED
+ RebaseOpcodeDoRebaseImmediateTimes = 0x50u, // REBASE_OPCODE_DO_REBASE_IMM_TIMES
+ RebaseOpcodeDoRebaseULEBTimes = 0x60u, // REBASE_OPCODE_DO_REBASE_ULEB_TIMES
+ RebaseOpcodeDoRebaseAddAddressULEB = 0x70u, // REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB
+ RebaseOpcodeDoRebaseULEBTimesSkippingULEB = 0x80u, // REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB
+
+
+ BindTypePointer = 1u, // BIND_TYPE_POINTER
+ BindTypeTextAbsolute32 = 2u, // BIND_TYPE_TEXT_ABSOLUTE32
+ BindTypeTextPCRelative32 = 3u, // BIND_TYPE_TEXT_PCREL32
+
+ BindSpecialDylibSelf = 0u, // BIND_SPECIAL_DYLIB_SELF
+ BindSpecialDylibMainExecutable = -1u, // BIND_SPECIAL_DYLIB_MAIN_EXECUTABLE
+ BindSpecialDylibFlatLookup = -2u, // BIND_SPECIAL_DYLIB_FLAT_LOOKUP
+
+ BindSymbolFlagsWeakImport = 0x1u, // BIND_SYMBOL_FLAGS_WEAK_IMPORT
+ BindSymbolFlagsNonWeakDefinition = 0x8u, // BIND_SYMBOL_FLAGS_NON_WEAK_DEFINITION
+
+ BindOpcodeMask = 0xF0u, // BIND_OPCODE_MASK
+ BindImmediateMask = 0x0Fu, // BIND_IMMEDIATE_MASK
+ BindOpcodeDone = 0x00u, // BIND_OPCODE_DONE
+ BindOpcodeSetDylibOrdinalImmediate = 0x10u, // BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
+ BindOpcodeSetDylibOrdinalULEB = 0x20u, // BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB
+ BindOpcodeSetDylibSpecialImmediate = 0x30u, // BIND_OPCODE_SET_DYLIB_SPECIAL_IMM
+ BindOpcodeSetSymbolTrailingFlagsImmediate = 0x40u, // BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
+ BindOpcodeSetTypeImmediate = 0x50u, // BIND_OPCODE_SET_TYPE_IMM
+ BindOpcodeSetAppendSLEB = 0x60u, // BIND_OPCODE_SET_ADDEND_SLEB
+ BindOpcodeSetSegmentAndOffsetULEB = 0x70u, // BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
+ BindOpcodeAddAddressULEB = 0x80u, // BIND_OPCODE_ADD_ADDR_ULEB
+ BindOpcodeDoBind = 0x90u, // BIND_OPCODE_DO_BIND
+ BindOpcodeDoBindAddAddressULEB = 0xA0u, // BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB
+ BindOpcodeDoBindAddAddressImmediateScaled = 0xB0u, // BIND_OPCODE_DO_BIND_ADD_ADDR_IMM_SCALED
+ BindOpcodeDoBindULEBTimesSkippingULEB = 0xC0u, // BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB
+
+ ExportSymbolFlagsKindMask = 0x03u, // EXPORT_SYMBOL_FLAGS_KIND_MASK
+ ExportSymbolFlagsKindRegular = 0x00u, // EXPORT_SYMBOL_FLAGS_KIND_REGULAR
+ ExportSymbolFlagsKindThreadLocal = 0x01u, // EXPORT_SYMBOL_FLAGS_KIND_THREAD_LOCAL
+ ExportSymbolFlagsWeakDefinition = 0x04u, // EXPORT_SYMBOL_FLAGS_WEAK_DEFINITION
+ ExportSymbolFlagsIndirectDefinition = 0x08u, // EXPORT_SYMBOL_FLAGS_INDIRECT_DEFINITION
+ ExportSymbolFlagsHasSpecializations = 0x10u, // EXPORT_SYMBOL_FLAGS_HAS_SPECIALIZATIONS
+
+
+ // Constant masks for the "n_type" field in llvm::MachO::nlist and
+ // llvm::MachO::nlist_64
+ NlistMaskStab = 0xe0, // N_STAB
+ NlistMaskPrivateExternal = 0x10, // N_PEXT
+ NlistMaskType = 0x0e, // N_TYPE
+ NlistMaskExternal = 0x01, // N_EXT
+
+ // Constants for the "n_type & N_TYPE" llvm::MachO::nlist and
+ // llvm::MachO::nlist_64
+ NListTypeUndefined = 0x0u, // N_UNDF
+ NListTypeAbsolute = 0x2u, // N_ABS
+ NListTypeSection = 0xeu, // N_SECT
+ NListTypePreboundUndefined = 0xcu, // N_PBUD
+ NListTypeIndirect = 0xau, // N_INDR
+
+ // Constant masks for the "n_sect" field in llvm::MachO::nlist and
+ // llvm::MachO::nlist_64
+ NListSectionNoSection = 0u, // NO_SECT
+ NListSectionMaxSection = 0xffu, // MAX_SECT
+
+ // Constant values for the "n_type" field in llvm::MachO::nlist and
+ // llvm::MachO::nlist_64 when "(n_type & NlistMaskStab) != 0"
+ StabGlobalSymbol = 0x20u, // N_GSYM
+ StabFunctionName = 0x22u, // N_FNAME
+ StabFunction = 0x24u, // N_FUN
+ StabStaticSymbol = 0x26u, // N_STSYM
+ StabLocalCommon = 0x28u, // N_LCSYM
+ StabBeginSymbol = 0x2Eu, // N_BNSYM
+ StabSourceFileOptions = 0x3Cu, // N_OPT
+ StabRegisterSymbol = 0x40u, // N_RSYM
+ StabSourceLine = 0x44u, // N_SLINE
+ StabEndSymbol = 0x4Eu, // N_ENSYM
+ StabStructureType = 0x60u, // N_SSYM
+ StabSourceFileName = 0x64u, // N_SO
+ StabObjectFileName = 0x66u, // N_OSO
+ StabLocalSymbol = 0x80u, // N_LSYM
+ StabBeginIncludeFileName = 0x82u, // N_BINCL
+ StabIncludeFileName = 0x84u, // N_SOL
+ StabCompilerParameters = 0x86u, // N_PARAMS
+ StabCompilerVersion = 0x88u, // N_VERSION
+ StabCompilerOptLevel = 0x8Au, // N_OLEVEL
+ StabParameter = 0xA0u, // N_PSYM
+ StabEndIncludeFile = 0xA2u, // N_EINCL
+ StabAlternateEntry = 0xA4u, // N_ENTRY
+ StabLeftBracket = 0xC0u, // N_LBRAC
+ StabDeletedIncludeFile = 0xC2u, // N_EXCL
+ StabRightBracket = 0xE0u, // N_RBRAC
+ StabBeginCommon = 0xE2u, // N_BCOMM
+ StabEndCommon = 0xE4u, // N_ECOMM
+ StabEndCommonLocal = 0xE8u, // N_ECOML
+ StabLength = 0xFEu // N_LENG
+
+ };
+
+ // Structs from <mach-o/loader.h>
+
+ struct mach_header {
+ uint32_t magic;
+ uint32_t cputype;
+ uint32_t cpusubtype;
+ uint32_t filetype;
+ uint32_t ncmds;
+ uint32_t sizeofcmds;
+ uint32_t flags;
+ };
+
+ struct mach_header_64 {
+ uint32_t magic;
+ uint32_t cputype;
+ uint32_t cpusubtype;
+ uint32_t filetype;
+ uint32_t ncmds;
+ uint32_t sizeofcmds;
+ uint32_t flags;
+ uint32_t reserved;
+ };
+
+ struct load_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ };
+
+ struct segment_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ char segname[16];
+ uint32_t vmaddr;
+ uint32_t vmsize;
+ uint32_t fileoff;
+ uint32_t filesize;
+ uint32_t maxprot;
+ uint32_t initprot;
+ uint32_t nsects;
+ uint32_t flags;
+ };
+
+ struct segment_command_64 {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ char segname[16];
+ uint64_t vmaddr;
+ uint64_t vmsize;
+ uint64_t fileoff;
+ uint64_t filesize;
+ uint32_t maxprot;
+ uint32_t initprot;
+ uint32_t nsects;
+ uint32_t flags;
+ };
+
+ struct section {
+ char sectname[16];
+ char segname[16];
+ uint32_t addr;
+ uint32_t size;
+ uint32_t offset;
+ uint32_t align;
+ uint32_t reloff;
+ uint32_t nreloc;
+ uint32_t flags;
+ uint32_t reserved1;
+ uint32_t reserved2;
+ };
+
+ struct section_64 {
+ char sectname[16];
+ char segname[16];
+ uint64_t addr;
+ uint64_t size;
+ uint32_t offset;
+ uint32_t align;
+ uint32_t reloff;
+ uint32_t nreloc;
+ uint32_t flags;
+ uint32_t reserved1;
+ uint32_t reserved2;
+ uint32_t reserved3;
+ };
+
+ struct fvmlib {
+ uint32_t name;
+ uint32_t minor_version;
+ uint32_t header_addr;
+ };
+
+ struct fvmlib_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ struct fvmlib fvmlib;
+ };
+
+ struct dylib {
+ uint32_t name;
+ uint32_t timestamp;
+ uint32_t current_version;
+ uint32_t compatibility_version;
+ };
+
+ struct dylib_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ struct dylib dylib;
+ };
+
+ struct sub_framework_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t umbrella;
+ };
+
+ struct sub_client_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t client;
+ };
+
+ struct sub_umbrella_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t sub_umbrella;
+ };
+
+ struct sub_library_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t sub_library;
+ };
+
+ struct prebound_dylib_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t name;
+ uint32_t nmodules;
+ uint32_t linked_modules;
+ };
+
+ struct dylinker_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t name;
+ };
+
+ struct thread_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ };
+
+ struct routines_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t init_address;
+ uint32_t init_module;
+ uint32_t reserved1;
+ uint32_t reserved2;
+ uint32_t reserved3;
+ uint32_t reserved4;
+ uint32_t reserved5;
+ uint32_t reserved6;
+ };
+
+ struct routines_command_64 {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint64_t init_address;
+ uint64_t init_module;
+ uint64_t reserved1;
+ uint64_t reserved2;
+ uint64_t reserved3;
+ uint64_t reserved4;
+ uint64_t reserved5;
+ uint64_t reserved6;
+ };
+
+ struct symtab_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t symoff;
+ uint32_t nsyms;
+ uint32_t stroff;
+ uint32_t strsize;
+ };
+
+ struct dysymtab_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t ilocalsym;
+ uint32_t nlocalsym;
+ uint32_t iextdefsym;
+ uint32_t nextdefsym;
+ uint32_t iundefsym;
+ uint32_t nundefsym;
+ uint32_t tocoff;
+ uint32_t ntoc;
+ uint32_t modtaboff;
+ uint32_t nmodtab;
+ uint32_t extrefsymoff;
+ uint32_t nextrefsyms;
+ uint32_t indirectsymoff;
+ uint32_t nindirectsyms;
+ uint32_t extreloff;
+ uint32_t nextrel;
+ uint32_t locreloff;
+ uint32_t nlocrel;
+ };
+
+ struct dylib_table_of_contents {
+ uint32_t symbol_index;
+ uint32_t module_index;
+ };
+
+ struct dylib_module {
+ uint32_t module_name;
+ uint32_t iextdefsym;
+ uint32_t nextdefsym;
+ uint32_t irefsym;
+ uint32_t nrefsym;
+ uint32_t ilocalsym;
+ uint32_t nlocalsym;
+ uint32_t iextrel;
+ uint32_t nextrel;
+ uint32_t iinit_iterm;
+ uint32_t ninit_nterm;
+ uint32_t objc_module_info_addr;
+ uint32_t objc_module_info_size;
+ };
+
+ struct dylib_module_64 {
+ uint32_t module_name;
+ uint32_t iextdefsym;
+ uint32_t nextdefsym;
+ uint32_t irefsym;
+ uint32_t nrefsym;
+ uint32_t ilocalsym;
+ uint32_t nlocalsym;
+ uint32_t iextrel;
+ uint32_t nextrel;
+ uint32_t iinit_iterm;
+ uint32_t ninit_nterm;
+ uint32_t objc_module_info_size;
+ uint64_t objc_module_info_addr;
+ };
+
+ struct dylib_reference {
+ uint32_t isym:24,
+ flags:8;
+ };
+
+
+ struct twolevel_hints_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t offset;
+ uint32_t nhints;
+ };
+
+ struct twolevel_hint {
+ uint32_t isub_image:8,
+ itoc:24;
+ };
+
+ struct prebind_cksum_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t cksum;
+ };
+
+ struct uuid_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint8_t uuid[16];
+ };
+
+ struct rpath_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t path;
+ };
+
+ struct linkedit_data_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t dataoff;
+ uint32_t datasize;
+ };
+
+ struct encryption_info_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t cryptoff;
+ uint32_t cryptsize;
+ uint32_t cryptid;
+ };
+
+ struct dyld_info_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t rebase_off;
+ uint32_t rebase_size;
+ uint32_t bind_off;
+ uint32_t bind_size;
+ uint32_t weak_bind_off;
+ uint32_t weak_bind_size;
+ uint32_t lazy_bind_off;
+ uint32_t lazy_bind_size;
+ uint32_t export_off;
+ uint32_t export_size;
+ };
+
+ struct symseg_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t offset;
+ uint32_t size;
+ };
+
+ struct ident_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ };
+
+ struct fvmfile_command {
+ uint32_t cmd;
+ uint32_t cmdsize;
+ uint32_t name;
+ uint32_t header_addr;
+ };
+
+
+ // Structs from <mach-o/fat.h>
+ struct fat_header {
+ uint32_t magic;
+ uint32_t nfat_arch;
+ };
+
+ struct fat_arch {
+ uint32_t cputype;
+ uint32_t cpusubtype;
+ uint32_t offset;
+ uint32_t size;
+ uint32_t align;
+ };
+
+ // Structs from <mach-o/fat.h>
+ struct nlist {
+ uint32_t n_strx;
+ uint8_t n_type;
+ uint8_t n_sect;
+ int16_t n_desc;
+ uint32_t n_value;
+ };
+
+ struct nlist_64 {
+ uint32_t n_strx;
+ uint8_t n_type;
+ uint8_t n_sect;
+ uint16_t n_desc;
+ uint64_t n_value;
+ };
+
+ // Get/Set functions from <mach-o/nlist.h>
+
+ static inline uint16_t GET_LIBRARY_ORDINAL(uint16_t n_desc)
+ {
+ return (((n_desc) >> 8u) & 0xffu);
+ }
+
+ static inline void SET_LIBRARY_ORDINAL(uint16_t &n_desc, uint8_t ordinal)
+ {
+ n_desc = (((n_desc) & 0x00ff) | (((ordinal) & 0xff) << 8));
+ }
+
+ static inline uint8_t GET_COMM_ALIGN (uint16_t n_desc)
+ {
+ return (n_desc >> 8u) & 0x0fu;
+ }
+
+ static inline void SET_COMM_ALIGN (uint16_t &n_desc, uint8_t align)
+ {
+ n_desc = ((n_desc & 0xf0ffu) | ((align & 0x0fu) << 8u));
+ }
+
// Enums from <mach/machine.h>
enum {
// Capability bits used in the definition of cpu_type.
Modified: llvm/branches/wendling/eh/include/llvm/Support/Registry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/Registry.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/Registry.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/Registry.h Sat Jul 31 19:59:02 2010
@@ -203,6 +203,8 @@
};
+ // Since these are defined in a header file, plugins must be sure to export
+ // these symbols.
template <typename T, typename U>
typename Registry<T,U>::node *Registry<T,U>::Head;
Modified: llvm/branches/wendling/eh/include/llvm/Support/StandardPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Support/StandardPasses.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Support/StandardPasses.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Support/StandardPasses.h Sat Jul 31 19:59:02 2010
@@ -20,6 +20,7 @@
#define LLVM_SUPPORT_STANDARDPASSES_H
#include "llvm/PassManager.h"
+#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Transforms/Scalar.h"
@@ -128,6 +129,8 @@
PM->add(createTailCallEliminationPass()); // Eliminate tail calls
PM->add(createCFGSimplificationPass()); // Merge & remove BBs
PM->add(createReassociatePass()); // Reassociate expressions
+ // Explicitly schedule this to ensure that it runs before any loop pass.
+ PM->add(new DominanceFrontier()); // Calculate Dominance Frontiers
PM->add(createLoopRotatePass()); // Rotate Loop
PM->add(createLICMPass()); // Hoist loop invariants
PM->add(createLoopUnswitchPass(OptimizeSize || OptimizationLevel < 3));
Modified: llvm/branches/wendling/eh/include/llvm/System/ThreadLocal.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/System/ThreadLocal.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/System/ThreadLocal.h (original)
+++ llvm/branches/wendling/eh/include/llvm/System/ThreadLocal.h Sat Jul 31 19:59:02 2010
@@ -19,6 +19,8 @@
namespace llvm {
namespace sys {
+ // ThreadLocalImpl - Common base class of all ThreadLocal instantiations.
+ // YOU SHOULD NEVER USE THIS DIRECTLY.
class ThreadLocalImpl {
void* data;
public:
@@ -26,14 +28,25 @@
virtual ~ThreadLocalImpl();
void setInstance(const void* d);
const void* getInstance();
+ void removeInstance();
};
+ /// ThreadLocal - A class used to abstract thread-local storage. It holds,
+ /// for each thread, a pointer a single object of type T.
template<class T>
class ThreadLocal : public ThreadLocalImpl {
public:
ThreadLocal() : ThreadLocalImpl() { }
+
+ /// get - Fetches a pointer to the object associated with the current
+ /// thread. If no object has yet been associated, it returns NULL;
T* get() { return static_cast<T*>(getInstance()); }
+
+ // set - Associates a pointer to an object with the current thread.
void set(T* d) { setInstance(d); }
+
+ // erase - Removes the pointer associated with the current thread.
+ void erase() { removeInstance(); }
};
}
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/Target.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/Target.td (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/Target.td Sat Jul 31 19:59:02 2010
@@ -198,6 +198,7 @@
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
+ bit isCompare = 0; // Is this instruction a comparison instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
@@ -409,7 +410,7 @@
let InOperandList = (ins variable_ops);
let AsmString = "";
}
-def DBG_LABEL : Instruction {
+def PROLOG_LABEL : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetAsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetAsmParser.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetAsmParser.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetAsmParser.h Sat Jul 31 19:59:02 2010
@@ -28,14 +28,20 @@
protected: // Can only create subclasses.
TargetAsmParser(const Target &);
- /// TheTarget - The Target that this machine was created for.
+ /// The Target that this machine was created for.
const Target &TheTarget;
+ /// The current set of available features.
+ unsigned AvailableFeatures;
+
public:
virtual ~TargetAsmParser();
const Target &getTarget() const { return TheTarget; }
+ unsigned getAvailableFeatures() const { return AvailableFeatures; }
+ void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
+
/// ParseInstruction - Parse one assembly instruction.
///
/// The parser is positioned following the instruction name. The target
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetInstrDesc.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetInstrDesc.h Sat Jul 31 19:59:02 2010
@@ -105,6 +105,7 @@
IndirectBranch,
Predicable,
NotDuplicable,
+ Compare,
DelaySlot,
FoldableAsLoad,
MayLoad,
@@ -315,7 +316,7 @@
bool isIndirectBranch() const {
return Flags & (1 << TID::IndirectBranch);
}
-
+
/// isConditionalBranch - Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
@@ -340,6 +341,11 @@
return Flags & (1 << TID::Predicable);
}
+ /// isCompare - Return true if this instruction is a comparison.
+ bool isCompare() const {
+ return Flags & (1 << TID::Compare);
+ }
+
/// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -92,15 +92,6 @@
AliasAnalysis *AA) const;
public:
- /// isMoveInstr - Return true if the instruction is a register to register
- /// move and return the source and dest operands and their sub-register
- /// indices by reference.
- virtual bool isMoveInstr(const MachineInstr& MI,
- unsigned& SrcReg, unsigned& DstReg,
- unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
- return false;
- }
-
/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
/// extension instruction. That is, it's like a copy where it's legal for the
/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
@@ -113,22 +104,6 @@
return false;
}
- /// isIdentityCopy - Return true if the instruction is a copy (or
- /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
- /// destination registers are the same.
- bool isIdentityCopy(const MachineInstr &MI) const {
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- SrcReg == DstReg)
- return true;
-
- if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
- MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
- MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
- return true;
- return false;
- }
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
@@ -371,7 +346,7 @@
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
+ assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
}
/// loadRegFromStackSlot - Load the specified register of the given register
@@ -383,7 +358,7 @@
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
+ assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
}
/// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
@@ -392,7 +367,7 @@
/// storeRegToStackSlot(). Returns false otherwise.
virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
- const std::vector<CalleeSavedInfo> &CSI,
+ const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const {
return false;
}
@@ -457,7 +432,7 @@
/// take care of adding a MachineMemOperand to the newly created instruction.
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI,
- const SmallVectorImpl<unsigned> &Ops,
+ const SmallVectorImpl<unsigned> &Ops,
MachineInstr* LoadMI) const {
return 0;
}
@@ -501,7 +476,7 @@
/// only differences between the two addresses are the offset. It also returns
/// the offsets by reference.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
- int64_t &Offset1, int64_t &Offset2) const {
+ int64_t &Offset1, int64_t &Offset2) const {
return false;
}
@@ -591,18 +566,6 @@
const MachineBasicBlock *MBB,
const MachineFunction &MF) const = 0;
- /// GetInstSize - Returns the size of the specified Instruction.
- ///
- virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
- assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
- return 0;
- }
-
- /// GetFunctionSizeInBytes - Returns the size of the specified
- /// MachineFunction.
- ///
- virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
-
/// Measure the specified inline asm to determine an approximation of its
/// length.
virtual unsigned getInlineAsmLength(const char *Str,
@@ -646,7 +609,6 @@
virtual bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const;
- virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
virtual ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetLowering.h Sat Jul 31 19:59:02 2010
@@ -168,6 +168,32 @@
return RC;
}
+ /// getRepRegClassFor - Return the 'representative' register class for the
+ /// specified value type. The 'representative' register class is the largest
+ /// legal super-reg register class for the register class of the value type.
+ /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
+ /// while the rep register class is GR64 on x86_64.
+ virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const {
+ assert(VT.isSimple() && "getRepRegClassFor called on illegal type!");
+ const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
+ return RC;
+ }
+
+ /// getRepRegClassCostFor - Return the cost of the 'representative' register
+ /// class for the specified value type.
+ virtual uint8_t getRepRegClassCostFor(EVT VT) const {
+ assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!");
+ return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
+ }
+
+ /// getRegPressureLimit - Return the register pressure "high water mark" for
+ /// the specific register class. The scheduler is in high register pressure
+ /// mode (for the specific register class) if it goes over the limit.
+ virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ return 0;
+ }
+
/// isTypeLegal - Return true if the target has native support for the
/// specified value type. This means that it has a register that directly
/// holds it without promotions or expansions.
@@ -766,6 +792,12 @@
return false;
}
+ /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
+ /// used for loads / stores from the global.
+ virtual unsigned getMaximalGlobalOffset() const {
+ return 0;
+ }
+
//===--------------------------------------------------------------------===//
// TargetLowering Optimization Methods
//
@@ -981,6 +1013,11 @@
Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
}
+ /// findRepresentativeClass - Return the largest legal super-reg register class
+ /// of the register class for the specified type and its associated "cost".
+ virtual std::pair<const TargetRegisterClass*, uint8_t>
+ findRepresentativeClass(EVT VT) const;
+
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void computeRegisterProperties();
@@ -1562,6 +1599,19 @@
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
+ /// RepRegClassForVT - This indicates the "representative" register class to
+ /// use for each ValueType the target supports natively. This information is
+ /// used by the scheduler to track register pressure. By default, the
+ /// representative register class is the largest legal super-reg register
+ /// class of the register class of the specified type. e.g. On x86, i8, i16,
+ /// and i32's representative class would be GR32.
+ const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
+
+ /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
+ /// register class for each ValueType. The cost is used by the scheduler to
+ /// approximate register pressure.
+ uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
+
/// Synthesizable indicates whether it is OK for the compiler to create new
/// operations using this type. All Legal types are Synthesizable except
/// MMX types on X86. Non-Legal types are not Synthesizable.
@@ -1672,6 +1722,15 @@
/// This field specifies whether the target can benefit from code placement
/// optimization.
bool benefitFromCodePlacementOpt;
+
+private:
+ /// isLegalRC - Return true if the value types that can be represented by the
+ /// specified register class are all legal.
+ bool isLegalRC(const TargetRegisterClass *RC) const;
+
+ /// hasLegalSuperRegRegClasses - Return true if the specified register class
+ /// has one or more super-reg register classes that are legal.
+ bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
};
/// GetReturnInfo - Given an LLVM IR type and return type attributes,
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetMachine.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetMachine.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetMachine.h Sat Jul 31 19:59:02 2010
@@ -75,7 +75,8 @@
None, // No preference
Latency, // Scheduling for shortest total latency.
RegPressure, // Scheduling for lowest register pressure.
- Hybrid // Scheduling for both latency and register pressure.
+ Hybrid, // Scheduling for both latency and register pressure.
+ ILP // Scheduling for ILP in low register pressure mode.
};
}
@@ -244,6 +245,18 @@
bool = true) {
return true;
}
+
+ /// addPassesToEmitMC - Add passes to the specified pass manager to get
+ /// machine code emitted with the MCJIT. This method returns true if machine
+ /// code is not supported. It fills the MCContext Ctx pointer which can be
+ /// used to build custom MCStreamer.
+ ///
+ virtual bool addPassesToEmitMC(PassManagerBase &,
+ MCContext *&,
+ CodeGenOpt::Level,
+ bool = true) {
+ return true;
+ }
};
/// LLVMTargetMachine - This class describes a target machine that is
@@ -287,12 +300,27 @@
JITCodeEmitter &MCE,
CodeGenOpt::Level,
bool DisableVerify = true);
+
+ /// addPassesToEmitMC - Add passes to the specified pass manager to get
+ /// machine code emitted with the MCJIT. This method returns true if machine
+ /// code is not supported. It fills the MCContext Ctx pointer which can be
+ /// used to build custom MCStreamer.
+ ///
+ virtual bool addPassesToEmitMC(PassManagerBase &PM,
+ MCContext *&Ctx,
+ CodeGenOpt::Level OptLevel,
+ bool DisableVerify = true);
/// Target-Independent Code Generator Pass Configuration Options.
-
- /// addInstSelector - This method should add any "last minute" LLVM->LLVM
- /// passes, then install an instruction selector pass, which converts from
- /// LLVM code to machine instructions.
+
+ /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
+ /// passes (which are run just before instruction selector).
+ virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
+ return true;
+ }
+
+ /// addInstSelector - This method should install an instruction selector pass,
+ /// which converts from LLVM code to machine instructions.
virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetOpcodes.h Sat Jul 31 19:59:02 2010
@@ -25,7 +25,7 @@
enum {
PHI = 0,
INLINEASM = 1,
- DBG_LABEL = 2,
+ PROLOG_LABEL = 2,
EH_LABEL = 3,
GC_LABEL = 4,
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetOptions.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetOptions.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetOptions.h Sat Jul 31 19:59:02 2010
@@ -71,13 +71,18 @@
/// UnsafeFPMath implies LessPreciseFPMAD.
extern bool UnsafeFPMath;
- /// FiniteOnlyFPMath - This returns true when the -enable-finite-only-fp-math
- /// option is specified on the command line. If this returns false (default),
- /// the code generator is not allowed to assume that FP arithmetic arguments
- /// and results are never NaNs or +-Infs.
- extern bool FiniteOnlyFPMathOption;
- extern bool FiniteOnlyFPMath();
-
+ /// NoInfsFPMath - This flag is enabled when the
+ /// -enable-no-infs-fp-math flag is specified on the command line. When
+ /// this flag is off (the default), the code generator is not allowed to
+ /// assume the FP arithmetic arguments and results are never +-Infs.
+ extern bool NoInfsFPMath;
+
+ /// NoNaNsFPMath - This flag is enabled when the
+ /// -enable-no-nans-fp-math flag is specified on the command line. When
+ /// this flag is off (the default), the code generator is not allowed to
+ /// assume the FP arithmetic arguments and results are never NaNs.
+ extern bool NoNaNsFPMath;
+
/// HonorSignDependentRoundingFPMath - This returns true when the
/// -enable-sign-dependent-rounding-fp-math is specified. If this returns
/// false (the default), the code generator is allowed to assume that the
@@ -135,8 +140,8 @@
/// StackAlignment - Override default stack alignment for target.
extern unsigned StackAlignment;
- /// RealignStack - This flag indicates, whether stack should be automatically
- /// realigned, if needed.
+ /// RealignStack - This flag indicates whether the stack should be
+ /// automatically realigned, if needed.
extern bool RealignStack;
/// DisableJumpTables - This flag indicates jump tables should not be
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetRegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -603,18 +603,18 @@
/// immediately on entry to the current function. This eliminates the need for
/// add/sub sp brackets around call sites. Returns true if the call frame is
/// included as part of the stack frame.
- virtual bool hasReservedCallFrame(MachineFunction &MF) const {
+ virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
return !hasFP(MF);
}
/// canSimplifyCallFramePseudos - When possible, it's best to simplify the
/// call frame pseudo ops before doing frame index elimination. This is
/// possible only when frame index references between the pseudos won't
- /// need adjusted for the call frame adjustments. Normally, that's true
+ /// need adjusting for the call frame adjustments. Normally, that's true
/// if the function has a reserved call frame or a frame pointer. Some
/// targets (Thumb2, for example) may have more complicated criteria,
/// however, and can override this behavior.
- virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const {
+ virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
return hasReservedCallFrame(MF) || hasFP(MF);
}
@@ -624,7 +624,7 @@
/// reserved as its spill slot. This tells PEI not to create a new stack frame
/// object for the given register. It should be called only after
/// processFunctionBeforeCalleeSavedScan().
- virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
+ virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
int &FrameIdx) const {
return false;
}
Modified: llvm/branches/wendling/eh/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Target/TargetRegistry.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Target/TargetRegistry.h Sat Jul 31 19:59:02 2010
@@ -65,7 +65,8 @@
const std::string &TT);
typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
const MCAsmInfo &MAI);
- typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P);
+ typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P,
+ TargetMachine &TM);
typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
unsigned SyntaxVariant,
@@ -237,10 +238,11 @@
///
/// \arg Parser - The target independent parser implementation to use for
/// parsing and lexing.
- TargetAsmParser *createAsmParser(MCAsmParser &Parser) const {
+ TargetAsmParser *createAsmParser(MCAsmParser &Parser,
+ TargetMachine &TM) const {
if (!AsmParserCtorFn)
return 0;
- return AsmParserCtorFn(*this, Parser);
+ return AsmParserCtorFn(*this, Parser, TM);
}
/// createAsmPrinter - Create a target specific assembly printer pass. This
@@ -276,9 +278,9 @@
///
/// \arg TT - The target triple.
/// \arg Ctx - The target context.
- /// \arg TAB - The target assembler backend object.
+ /// \arg TAB - The target assembler backend object. Takes ownership.
/// \arg _OS - The stream object.
- /// \arg _Emitter - The target independent assembler object.
+ /// \arg _Emitter - The target independent assembler object.Takes ownership.
/// \arg RelaxAll - Relax all fixups?
MCStreamer *createObjectStreamer(const std::string &TT, MCContext &Ctx,
TargetAsmBackend &TAB,
@@ -667,8 +669,9 @@
}
private:
- static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P) {
- return new AsmParserImpl(T, P);
+ static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P,
+ TargetMachine &TM) {
+ return new AsmParserImpl(T, P, TM);
}
};
Modified: llvm/branches/wendling/eh/include/llvm/Transforms/IPO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Transforms/IPO.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Transforms/IPO.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Transforms/IPO.h Sat Jul 31 19:59:02 2010
@@ -181,7 +181,7 @@
/// createBlockExtractorPass - This pass extracts all blocks (except those
/// specified in the argument list) from the functions in the module.
///
-ModulePass *createBlockExtractorPass(const std::vector<BasicBlock*> &BTNE);
+ModulePass *createBlockExtractorPass();
/// createStripDeadPrototypesPass - This pass removes any function declarations
/// (prototypes) that are not used.
Modified: llvm/branches/wendling/eh/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Use.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Use.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Use.h Sat Jul 31 19:59:02 2010
@@ -210,30 +210,6 @@
unsigned getOperandNo() const;
};
-
-template<> struct simplify_type<value_use_iterator<User> > {
- typedef User* SimpleType;
-
- static SimpleType getSimplifiedValue(const value_use_iterator<User> &Val) {
- return *Val;
- }
-};
-
-template<> struct simplify_type<const value_use_iterator<User> >
- : public simplify_type<value_use_iterator<User> > {};
-
-template<> struct simplify_type<value_use_iterator<const User> > {
- typedef const User* SimpleType;
-
- static SimpleType getSimplifiedValue(const
- value_use_iterator<const User> &Val) {
- return *Val;
- }
-};
-
-template<> struct simplify_type<const value_use_iterator<const User> >
- : public simplify_type<value_use_iterator<const User> > {};
-
} // End llvm namespace
#endif
Modified: llvm/branches/wendling/eh/include/llvm/Value.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/Value.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/Value.h (original)
+++ llvm/branches/wendling/eh/include/llvm/Value.h Sat Jul 31 19:59:02 2010
@@ -220,7 +220,6 @@
ConstantPointerNullVal, // This is an instance of ConstantPointerNull
MDNodeVal, // This is an instance of MDNode
MDStringVal, // This is an instance of MDString
- NamedMDNodeVal, // This is an instance of NamedMDNode
InlineAsmVal, // This is an instance of InlineAsm
PseudoSourceValueVal, // This is an instance of PseudoSourceValue
FixedStackPseudoSourceValueVal, // This is an instance of
@@ -266,6 +265,10 @@
SubclassOptionalData &= V->SubclassOptionalData;
}
+ /// hasValueHandle - Return true if there is a value handle associated with
+ /// this value.
+ bool hasValueHandle() const { return HasValueHandle; }
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const Value *) {
return true; // Values are always values.
@@ -304,6 +307,10 @@
return const_cast<Value*>(this)->DoPHITranslation(CurBB, PredBB);
}
+ /// MaximumAlignment - This is the greatest alignment value supported by
+ /// load, store, and alloca instructions, and global values.
+ static const unsigned MaximumAlignment = 1u << 29;
+
protected:
unsigned short getSubclassDataFromValue() const { return SubclassData; }
void setValueSubclassData(unsigned short D) { SubclassData = D; }
Modified: llvm/branches/wendling/eh/include/llvm/ValueSymbolTable.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/include/llvm/ValueSymbolTable.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/include/llvm/ValueSymbolTable.h (original)
+++ llvm/branches/wendling/eh/include/llvm/ValueSymbolTable.h Sat Jul 31 19:59:02 2010
@@ -128,94 +128,6 @@
/// @}
};
-/// This class provides a symbol table of name/NamedMDNode pairs. It is
-/// essentially a StringMap wrapper.
-
-class MDSymbolTable {
- friend class SymbolTableListTraits<NamedMDNode, Module>;
-/// @name Types
-/// @{
-private:
- /// @brief A mapping of names to metadata
- typedef StringMap<NamedMDNode*> MDMap;
-
-public:
- /// @brief An iterator over a ValueMap.
- typedef MDMap::iterator iterator;
-
- /// @brief A const_iterator over a ValueMap.
- typedef MDMap::const_iterator const_iterator;
-
-/// @}
-/// @name Constructors
-/// @{
-public:
-
- MDSymbolTable(const MDNode &); // DO NOT IMPLEMENT
- void operator=(const MDSymbolTable &); // DO NOT IMPLEMENT
- MDSymbolTable() : mmap(0) {}
- ~MDSymbolTable();
-
-/// @}
-/// @name Accessors
-/// @{
-public:
-
- /// This method finds the value with the given \p Name in the
- /// the symbol table.
- /// @returns the NamedMDNode associated with the \p Name
- /// @brief Lookup a named Value.
- NamedMDNode *lookup(StringRef Name) const { return mmap.lookup(Name); }
-
- /// @returns true iff the symbol table is empty
- /// @brief Determine if the symbol table is empty
- inline bool empty() const { return mmap.empty(); }
-
- /// @brief The number of name/type pairs is returned.
- inline unsigned size() const { return unsigned(mmap.size()); }
-
-/// @}
-/// @name Iteration
-/// @{
-public:
- /// @brief Get an iterator that from the beginning of the symbol table.
- inline iterator begin() { return mmap.begin(); }
-
- /// @brief Get a const_iterator that from the beginning of the symbol table.
- inline const_iterator begin() const { return mmap.begin(); }
-
- /// @brief Get an iterator to the end of the symbol table.
- inline iterator end() { return mmap.end(); }
-
- /// @brief Get a const_iterator to the end of the symbol table.
- inline const_iterator end() const { return mmap.end(); }
-
-/// @}
-/// @name Mutators
-/// @{
-public:
- /// insert - The method inserts a new entry into the stringmap. This will
- /// replace existing entry, if any.
- void insert(StringRef Name, NamedMDNode *Node) {
- StringMapEntry<NamedMDNode *> &Entry =
- mmap.GetOrCreateValue(Name, Node);
- if (Entry.getValue() != Node) {
- mmap.remove(&Entry);
- (void) mmap.GetOrCreateValue(Name, Node);
- }
- }
-
- /// This method removes a NamedMDNode from the symbol table.
- void remove(StringRef Name) { mmap.erase(Name); }
-
-/// @}
-/// @name Internal Data
-/// @{
-private:
- MDMap mmap; ///< The map that holds the symbol table.
-/// @}
-};
-
} // End llvm namespace
#endif
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisCounter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisCounter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisCounter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisCounter.cpp Sat Jul 31 19:59:02 2010
@@ -111,9 +111,8 @@
}
char AliasAnalysisCounter::ID = 0;
-static RegisterPass<AliasAnalysisCounter>
-X("count-aa", "Count Alias Analysis Query Responses", false, true);
-static RegisterAnalysisGroup<AliasAnalysis> Y(X);
+INITIALIZE_AG_PASS(AliasAnalysisCounter, AliasAnalysis, "count-aa",
+ "Count Alias Analysis Query Responses", false, true, false);
ModulePass *llvm::createAliasAnalysisCounterPass() {
return new AliasAnalysisCounter();
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasAnalysisEvaluator.cpp Sat Jul 31 19:59:02 2010
@@ -74,8 +74,8 @@
}
char AAEval::ID = 0;
-static RegisterPass<AAEval>
-X("aa-eval", "Exhaustive Alias Analysis Precision Evaluator", false, true);
+INITIALIZE_PASS(AAEval, "aa-eval",
+ "Exhaustive Alias Analysis Precision Evaluator", false, true);
FunctionPass *llvm::createAAEvalPass() { return new AAEval(); }
@@ -126,8 +126,7 @@
if (I->getType()->isPointerTy()) // Add all pointer instructions.
Pointers.insert(&*I);
Instruction &Inst = *I;
- CallSite CS = CallSite::get(&Inst);
- if (CS) {
+ if (CallSite CS = cast<Value>(&Inst)) {
Value *Callee = CS.getCalledValue();
// Skip actual functions for direct function calls.
if (!isa<Function>(Callee) && isInterestingPointer(Callee))
@@ -137,6 +136,7 @@
AI != AE; ++AI)
if (isInterestingPointer(*AI))
Pointers.insert(*AI);
+ CallSites.insert(CS);
} else {
// Consider all operands.
for (Instruction::op_iterator OI = Inst.op_begin(), OE = Inst.op_end();
@@ -144,8 +144,6 @@
if (isInterestingPointer(*OI))
Pointers.insert(*OI);
}
-
- if (CS.getInstruction()) CallSites.insert(CS);
}
if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasDebugger.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasDebugger.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasDebugger.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasDebugger.cpp Sat Jul 31 19:59:02 2010
@@ -126,9 +126,8 @@
}
char AliasDebugger::ID = 0;
-static RegisterPass<AliasDebugger>
-X("debug-aa", "AA use debugger", false, true);
-static RegisterAnalysisGroup<AliasAnalysis> Y(X);
+INITIALIZE_AG_PASS(AliasDebugger, AliasAnalysis, "debug-aa",
+ "AA use debugger", false, true, false);
Pass *llvm::createAliasDebugger() { return new AliasDebugger(); }
Modified: llvm/branches/wendling/eh/lib/Analysis/AliasSetTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/AliasSetTracker.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/AliasSetTracker.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/AliasSetTracker.cpp Sat Jul 31 19:59:02 2010
@@ -456,8 +456,7 @@
// If this is a call instruction, remove the callsite from the appropriate
// AliasSet.
- CallSite CS = CallSite::get(PtrVal);
- if (CS.getInstruction())
+ if (CallSite CS = PtrVal)
if (!AA.doesNotAccessMemory(CS))
if (AliasSet *AS = findAliasSetForCallSite(CS))
AS->removeCallSite(CS);
@@ -600,5 +599,5 @@
}
char AliasSetPrinter::ID = 0;
-static RegisterPass<AliasSetPrinter>
-X("print-alias-sets", "Alias Set Printer", false, true);
+INITIALIZE_PASS(AliasSetPrinter, "print-alias-sets",
+ "Alias Set Printer", false, true);
Modified: llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/BasicAliasAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -182,11 +182,9 @@
// Register this pass...
char NoAA::ID = 0;
-static RegisterPass<NoAA>
-U("no-aa", "No Alias Analysis (always returns 'may' alias)", true, true);
-
-// Declare that we implement the AliasAnalysis interface
-static RegisterAnalysisGroup<AliasAnalysis> V(U);
+INITIALIZE_AG_PASS(NoAA, AliasAnalysis, "no-aa",
+ "No Alias Analysis (always returns 'may' alias)",
+ true, true, false);
ImmutablePass *llvm::createNoAAPass() { return new NoAA(); }
@@ -275,11 +273,9 @@
// Register this pass...
char BasicAliasAnalysis::ID = 0;
-static RegisterPass<BasicAliasAnalysis>
-X("basicaa", "Basic Alias Analysis (default AA impl)", false, true);
-
-// Declare that we implement the AliasAnalysis interface
-static RegisterAnalysisGroup<AliasAnalysis, true> Y(X);
+INITIALIZE_AG_PASS(BasicAliasAnalysis, AliasAnalysis, "basicaa",
+ "Basic Alias Analysis (default AA impl)",
+ false, true, true);
ImmutablePass *llvm::createBasicAliasAnalysisPass() {
return new BasicAliasAnalysis();
Modified: llvm/branches/wendling/eh/lib/Analysis/CFGPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/CFGPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/CFGPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/CFGPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -41,8 +41,7 @@
}
char CFGViewer::ID = 0;
-static RegisterPass<CFGViewer>
-V0("view-cfg", "View CFG of function", false, true);
+INITIALIZE_PASS(CFGViewer, "view-cfg", "View CFG of function", false, true);
namespace {
struct CFGOnlyViewer : public FunctionPass {
@@ -63,9 +62,8 @@
}
char CFGOnlyViewer::ID = 0;
-static RegisterPass<CFGOnlyViewer>
-V1("view-cfg-only",
- "View CFG of function (with no function bodies)", false, true);
+INITIALIZE_PASS(CFGOnlyViewer, "view-cfg-only",
+ "View CFG of function (with no function bodies)", false, true);
namespace {
struct CFGPrinter : public FunctionPass {
Modified: llvm/branches/wendling/eh/lib/Analysis/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Analysis/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -38,6 +38,8 @@
ProfileInfoLoader.cpp
ProfileInfoLoaderPass.cpp
ProfileVerifierPass.cpp
+ RegionInfo.cpp
+ RegionPrinter.cpp
ScalarEvolution.cpp
ScalarEvolutionAliasAnalysis.cpp
ScalarEvolutionExpander.cpp
Modified: llvm/branches/wendling/eh/lib/Analysis/CaptureTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/CaptureTracking.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/CaptureTracking.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/CaptureTracking.cpp Sat Jul 31 19:59:02 2010
@@ -69,7 +69,7 @@
switch (I->getOpcode()) {
case Instruction::Call:
case Instruction::Invoke: {
- CallSite CS = CallSite::get(I);
+ CallSite CS(I);
// Not captured if the callee is readonly, doesn't return a copy through
// its return value and doesn't unwind (a readonly function can leak bits
// by throwing an exception or not depending on the input value).
Modified: llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ConstantFolding.cpp Sat Jul 31 19:59:02 2010
@@ -778,9 +778,9 @@
case Instruction::ICmp:
case Instruction::FCmp: assert(0 && "Invalid for compares");
case Instruction::Call:
- if (Function *F = dyn_cast<Function>(Ops[CallInst::ArgOffset ? 0:NumOps-1]))
+ if (Function *F = dyn_cast<Function>(Ops[NumOps - 1]))
if (canConstantFoldCallTo(F))
- return ConstantFoldCall(F, Ops+CallInst::ArgOffset, NumOps-1);
+ return ConstantFoldCall(F, Ops, NumOps - 1);
return 0;
case Instruction::PtrToInt:
// If the input is a inttoptr, eliminate the pair. This requires knowing
Modified: llvm/branches/wendling/eh/lib/Analysis/DbgInfoPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/DbgInfoPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/DbgInfoPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/DbgInfoPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -48,8 +48,8 @@
}
};
char PrintDbgInfo::ID = 0;
- static RegisterPass<PrintDbgInfo> X("print-dbginfo",
- "Print debug info in human readable form");
+ INITIALIZE_PASS(PrintDbgInfo, "print-dbginfo",
+ "Print debug info in human readable form", false, false);
}
FunctionPass *llvm::createDbgInfoPrinterPass() { return new PrintDbgInfo(); }
Modified: llvm/branches/wendling/eh/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/DebugInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/DebugInfo.cpp Sat Jul 31 19:59:02 2010
@@ -13,7 +13,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/Analysis/DebugInfo.h"
-#include "llvm/Target/TargetMachine.h" // FIXME: LAYERING VIOLATION!
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Intrinsics.h"
@@ -22,6 +21,7 @@
#include "llvm/Module.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Dwarf.h"
#include "llvm/Support/raw_ostream.h"
@@ -32,7 +32,7 @@
// DIDescriptor
//===----------------------------------------------------------------------===//
-StringRef
+StringRef
DIDescriptor::getStringField(unsigned Elt) const {
if (DbgNode == 0)
return StringRef();
@@ -60,7 +60,8 @@
return DIDescriptor();
if (Elt < DbgNode->getNumOperands())
- return DIDescriptor(dyn_cast_or_null<const MDNode>(DbgNode->getOperand(Elt)));
+ return
+ DIDescriptor(dyn_cast_or_null<const MDNode>(DbgNode->getOperand(Elt)));
return DIDescriptor();
}
@@ -233,8 +234,7 @@
}
/// replaceAllUsesWith - Replace all uses of debug info referenced by
-/// this descriptor. After this completes, the current debug info value
-/// is erased.
+/// this descriptor.
void DIDerivedType::replaceAllUsesWith(DIDescriptor &D) {
if (!DbgNode)
return;
@@ -249,7 +249,6 @@
const MDNode *DN = D;
const Value *V = cast_or_null<Value>(DN);
Node->replaceAllUsesWith(const_cast<Value*>(V));
- Node->destroy();
}
}
@@ -355,7 +354,7 @@
bool DILocation::Verify() const {
if (!DbgNode)
return false;
-
+
return DbgNode->getNumOperands() == 4;
}
@@ -378,7 +377,7 @@
Tag == dwarf::DW_TAG_const_type || Tag == dwarf::DW_TAG_volatile_type ||
Tag == dwarf::DW_TAG_restrict_type) {
DIType BaseType = getTypeDerivedFrom();
- // If this type is not derived from any type then take conservative
+ // If this type is not derived from any type then take conservative
// approach.
if (!BaseType.isValid())
return getSizeInBits();
@@ -387,17 +386,17 @@
else
return BaseType.getSizeInBits();
}
-
+
return getSizeInBits();
}
-/// isInlinedFnArgument - Return trule if this variable provides debugging
+/// isInlinedFnArgument - Return true if this variable provides debugging
/// information for an inlined function arguments.
bool DIVariable::isInlinedFnArgument(const Function *CurFn) {
assert(CurFn && "Invalid function");
if (!getContext().isSubprogram())
return false;
- // This variable is not inlined function argument if its scope
+ // This variable is not inlined function argument if its scope
// does not describe current function.
return !(DISubprogram(getContext()).describes(CurFn));
}
@@ -416,7 +415,7 @@
return false;
}
-unsigned DISubprogram::isOptimized() const {
+unsigned DISubprogram::isOptimized() const {
assert (DbgNode && "Invalid subprogram descriptor!");
if (DbgNode->getNumOperands() == 16)
return getUnsignedField(15);
@@ -426,7 +425,7 @@
StringRef DIScope::getFilename() const {
if (!DbgNode)
return StringRef();
- if (isLexicalBlock())
+ if (isLexicalBlock())
return DILexicalBlock(DbgNode).getFilename();
if (isSubprogram())
return DISubprogram(DbgNode).getFilename();
@@ -445,7 +444,7 @@
StringRef DIScope::getDirectory() const {
if (!DbgNode)
return StringRef();
- if (isLexicalBlock())
+ if (isLexicalBlock())
return DILexicalBlock(DbgNode).getDirectory();
if (isSubprogram())
return DISubprogram(DbgNode).getDirectory();
@@ -980,8 +979,8 @@
}
/// CreateSubprogramDefinition - Create new subprogram descriptor for the
-/// given declaration.
-DISubprogram DIFactory::CreateSubprogramDefinition(DISubprogram &SPDeclaration) {
+/// given declaration.
+DISubprogram DIFactory::CreateSubprogramDefinition(DISubprogram &SPDeclaration){
if (SPDeclaration.isDefinition())
return DISubprogram(SPDeclaration);
@@ -1073,10 +1072,10 @@
char One = '\1';
if (FName.startswith(StringRef(&One, 1)))
FName = FName.substr(1);
- NamedMDNode *FnLocals = M.getNamedMetadata(Twine("llvm.dbg.lv.", FName));
- if (!FnLocals)
- FnLocals = NamedMDNode::Create(VMContext, Twine("llvm.dbg.lv.", FName),
- NULL, 0, &M);
+
+ SmallString<32> Out;
+ NamedMDNode *FnLocals =
+ M.getOrInsertNamedMetadata(Twine("llvm.dbg.lv.", FName).toStringRef(Out));
FnLocals->addOperand(Node);
}
return DIVariable(Node);
@@ -1089,7 +1088,7 @@
const std::string &Name,
DIFile F,
unsigned LineNo,
- DIType Ty,
+ DIType Ty,
SmallVector<Value *, 9> &addr) {
SmallVector<Value *, 9> Elts;
Elts.push_back(GetTagConstant(Tag));
@@ -1107,14 +1106,19 @@
/// CreateBlock - This creates a descriptor for a lexical block with the
/// specified parent VMContext.
DILexicalBlock DIFactory::CreateLexicalBlock(DIDescriptor Context,
- unsigned LineNo, unsigned Col) {
+ DIFile F, unsigned LineNo,
+ unsigned Col) {
+ // Defeat MDNode uniqing for lexical blocks.
+ static unsigned int unique_id = 0;
Value *Elts[] = {
GetTagConstant(dwarf::DW_TAG_lexical_block),
Context,
ConstantInt::get(Type::getInt32Ty(VMContext), LineNo),
- ConstantInt::get(Type::getInt32Ty(VMContext), Col)
+ ConstantInt::get(Type::getInt32Ty(VMContext), Col),
+ F,
+ ConstantInt::get(Type::getInt32Ty(VMContext), unique_id++)
};
- return DILexicalBlock(MDNode::get(VMContext, &Elts[0], 4));
+ return DILexicalBlock(MDNode::get(VMContext, &Elts[0], 6));
}
/// CreateNameSpace - This creates new descriptor for a namespace
@@ -1174,7 +1178,7 @@
// If this block already has a terminator then insert this intrinsic
// before the terminator.
- if (TerminatorInst *T = InsertAtEnd->getTerminator())
+ if (TerminatorInst *T = InsertAtEnd->getTerminator())
return CallInst::Create(DeclareFn, Args, Args+2, "", T);
else
return CallInst::Create(DeclareFn, Args, Args+2, "", InsertAtEnd);}
@@ -1203,7 +1207,7 @@
if (!ValueFn)
ValueFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_value);
- Value *Args[] = { MDNode::get(V->getContext(), &V, 1),
+ Value *Args[] = { MDNode::get(V->getContext(), &V, 1),
ConstantInt::get(Type::getInt64Ty(V->getContext()), Offset),
D };
return CallInst::Create(ValueFn, Args, Args+3, "", InsertAtEnd);
@@ -1221,21 +1225,21 @@
++BI) {
if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(BI))
processDeclare(DDI);
-
+
DebugLoc Loc = BI->getDebugLoc();
if (Loc.isUnknown())
continue;
-
+
LLVMContext &Ctx = BI->getContext();
DIDescriptor Scope(Loc.getScope(Ctx));
-
+
if (Scope.isCompileUnit())
addCompileUnit(DICompileUnit(Scope));
else if (Scope.isSubprogram())
processSubprogram(DISubprogram(Scope));
else if (Scope.isLexicalBlock())
processLexicalBlock(DILexicalBlock(Scope));
-
+
if (MDNode *IA = Loc.getInlinedAt(Ctx))
processLocation(DILocation(IA));
}
@@ -1380,7 +1384,7 @@
return 0;
for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
- DIDescriptor DIG(cast_or_null<MDNode>(NMD->getOperand(i)));
+ DIDescriptor DIG(cast<MDNode>(NMD->getOperand(i)));
if (!DIG.isGlobalVariable())
continue;
if (DIGlobalVariable(DIG).getGlobal() == V)
@@ -1393,16 +1397,16 @@
/// It looks through pointer casts too.
static const DbgDeclareInst *findDbgDeclare(const Value *V) {
V = V->stripPointerCasts();
-
+
if (!isa<Instruction>(V) && !isa<Argument>(V))
return 0;
-
+
const Function *F = NULL;
if (const Instruction *I = dyn_cast<Instruction>(V))
F = I->getParent()->getParent();
else if (const Argument *A = dyn_cast<Argument>(V))
F = A->getParent();
-
+
for (Function::const_iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI)
for (BasicBlock::const_iterator BI = (*FI).begin(), BE = (*FI).end();
BI != BE; ++BI)
@@ -1460,10 +1464,10 @@
DIDescriptor D(Scope);
if (D.isSubprogram())
return DISubprogram(Scope);
-
+
if (D.isLexicalBlock())
return getDISubprogram(DILexicalBlock(Scope).getContext());
-
+
return DISubprogram();
}
@@ -1471,9 +1475,9 @@
DICompositeType llvm::getDICompositeType(DIType T) {
if (T.isCompositeType())
return DICompositeType(T);
-
+
if (T.isDerivedType())
return getDICompositeType(DIDerivedType(T).getTypeDerivedFrom());
-
+
return DICompositeType();
}
Modified: llvm/branches/wendling/eh/lib/Analysis/DomPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/DomPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/DomPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/DomPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -111,22 +111,23 @@
} // end anonymous namespace
char DomViewer::ID = 0;
-RegisterPass<DomViewer> A("view-dom",
- "View dominance tree of function");
+INITIALIZE_PASS(DomViewer, "view-dom",
+ "View dominance tree of function", false, false);
char DomOnlyViewer::ID = 0;
-RegisterPass<DomOnlyViewer> B("view-dom-only",
- "View dominance tree of function "
- "(with no function bodies)");
+INITIALIZE_PASS(DomOnlyViewer, "view-dom-only",
+ "View dominance tree of function (with no function bodies)",
+ false, false);
char PostDomViewer::ID = 0;
-RegisterPass<PostDomViewer> C("view-postdom",
- "View postdominance tree of function");
+INITIALIZE_PASS(PostDomViewer, "view-postdom",
+ "View postdominance tree of function", false, false);
char PostDomOnlyViewer::ID = 0;
-RegisterPass<PostDomOnlyViewer> D("view-postdom-only",
- "View postdominance tree of function "
- "(with no function bodies)");
+INITIALIZE_PASS(PostDomOnlyViewer, "view-postdom-only",
+ "View postdominance tree of function "
+ "(with no function bodies)",
+ false, false);
namespace {
struct DomPrinter
@@ -159,26 +160,26 @@
char DomPrinter::ID = 0;
-RegisterPass<DomPrinter> E("dot-dom",
- "Print dominance tree of function "
- "to 'dot' file");
+INITIALIZE_PASS(DomPrinter, "dot-dom",
+ "Print dominance tree of function to 'dot' file",
+ false, false);
char DomOnlyPrinter::ID = 0;
-RegisterPass<DomOnlyPrinter> F("dot-dom-only",
- "Print dominance tree of function "
- "to 'dot' file "
- "(with no function bodies)");
+INITIALIZE_PASS(DomOnlyPrinter, "dot-dom-only",
+ "Print dominance tree of function to 'dot' file "
+ "(with no function bodies)",
+ false, false);
char PostDomPrinter::ID = 0;
-RegisterPass<PostDomPrinter> G("dot-postdom",
- "Print postdominance tree of function "
- "to 'dot' file");
+INITIALIZE_PASS(PostDomPrinter, "dot-postdom",
+ "Print postdominance tree of function to 'dot' file",
+ false, false);
char PostDomOnlyPrinter::ID = 0;
-RegisterPass<PostDomOnlyPrinter> H("dot-postdom-only",
- "Print postdominance tree of function "
- "to 'dot' file "
- "(with no function bodies)");
+INITIALIZE_PASS(PostDomOnlyPrinter, "dot-postdom-only",
+ "Print postdominance tree of function to 'dot' file "
+ "(with no function bodies)",
+ false, false);
// Create methods available outside of this file, to use them
// "include/llvm/LinkAllPasses.h". Otherwise the pass would be deleted by
Modified: llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraph.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraph.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraph.cpp Sat Jul 31 19:59:02 2010
@@ -145,8 +145,8 @@
for (Function::iterator BB = F->begin(), BBE = F->end(); BB != BBE; ++BB)
for (BasicBlock::iterator II = BB->begin(), IE = BB->end();
II != IE; ++II) {
- CallSite CS = CallSite::get(II);
- if (CS.getInstruction() && !isa<DbgInfoIntrinsic>(II)) {
+ CallSite CS(cast<Value>(II));
+ if (CS && !isa<DbgInfoIntrinsic>(II)) {
const Function *Callee = CS.getCalledFunction();
if (Callee)
Node->addCalledFunction(CS, getOrInsertFunction(Callee));
@@ -172,9 +172,8 @@
} //End anonymous namespace
static RegisterAnalysisGroup<CallGraph> X("Call Graph");
-static RegisterPass<BasicCallGraph>
-Y("basiccg", "Basic CallGraph Construction", false, true);
-static RegisterAnalysisGroup<CallGraph, true> Z(Y);
+INITIALIZE_AG_PASS(BasicCallGraph, CallGraph, "basiccg",
+ "Basic CallGraph Construction", false, true, true);
char CallGraph::ID = 0;
char BasicCallGraph::ID = 0;
Modified: llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraphSCCPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraphSCCPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/IPA/CallGraphSCCPass.cpp Sat Jul 31 19:59:02 2010
@@ -209,7 +209,7 @@
// If the call edge is not from a call or invoke, then the function
// pass RAUW'd a call with another value. This can happen when
// constant folding happens of well known functions etc.
- CallSite::get(I->first).getInstruction() == 0) {
+ !CallSite(I->first)) {
assert(!CheckingMode &&
"CallGraphSCCPass did not update the CallGraph correctly!");
@@ -245,8 +245,8 @@
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
- CallSite CS = CallSite::get(I);
- if (!CS.getInstruction() || isa<DbgInfoIntrinsic>(I)) continue;
+ CallSite CS(cast<Value>(I));
+ if (!CS || isa<DbgInfoIntrinsic>(I)) continue;
// If this call site already existed in the callgraph, just verify it
// matches up to expectations and remove it from CallSites.
Modified: llvm/branches/wendling/eh/lib/Analysis/IPA/FindUsedTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/IPA/FindUsedTypes.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/IPA/FindUsedTypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/IPA/FindUsedTypes.cpp Sat Jul 31 19:59:02 2010
@@ -23,8 +23,8 @@
using namespace llvm;
char FindUsedTypes::ID = 0;
-static RegisterPass<FindUsedTypes>
-X("print-used-types", "Find Used Types", false, true);
+INITIALIZE_PASS(FindUsedTypes, "print-used-types",
+ "Find Used Types", false, true);
// IncorporateType - Incorporate one type and all of its subtypes into the
// collection of used types.
Modified: llvm/branches/wendling/eh/lib/Analysis/IVUsers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/IVUsers.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/IVUsers.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/IVUsers.cpp Sat Jul 31 19:59:02 2010
@@ -29,8 +29,7 @@
using namespace llvm;
char IVUsers::ID = 0;
-static RegisterPass<IVUsers>
-X("iv-users", "Induction Variable Users", false, true);
+INITIALIZE_PASS(IVUsers, "iv-users", "Induction Variable Users", false, true);
Pass *llvm::createIVUsersPass() {
return new IVUsers();
Modified: llvm/branches/wendling/eh/lib/Analysis/InlineCost.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/InlineCost.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/InlineCost.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/InlineCost.cpp Sat Jul 31 19:59:02 2010
@@ -152,14 +152,14 @@
if (isa<CallInst>(II) || isa<InvokeInst>(II)) {
if (isa<DbgInfoIntrinsic>(II))
continue; // Debug intrinsics don't count as size.
-
- CallSite CS = CallSite::get(const_cast<Instruction*>(&*II));
-
+
+ ImmutableCallSite CS(cast<Instruction>(II));
+
// If this function contains a call to setjmp or _setjmp, never inline
// it. This is a hack because we depend on the user marking their local
// variables as volatile if they are live across a setjmp call, and they
// probably won't do this in callers.
- if (Function *F = CS.getCalledFunction()) {
+ if (const Function *F = CS.getCalledFunction()) {
if (F->isDeclaration() &&
(F->getName() == "setjmp" || F->getName() == "_setjmp"))
callsSetJmp = true;
Modified: llvm/branches/wendling/eh/lib/Analysis/InstCount.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/InstCount.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/InstCount.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/InstCount.cpp Sat Jul 31 19:59:02 2010
@@ -64,8 +64,8 @@
}
char InstCount::ID = 0;
-static RegisterPass<InstCount>
-X("instcount", "Counts the various types of Instructions", false, true);
+INITIALIZE_PASS(InstCount, "instcount",
+ "Counts the various types of Instructions", false, true);
FunctionPass *llvm::createInstCountPass() { return new InstCount(); }
Modified: llvm/branches/wendling/eh/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/InstructionSimplify.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/InstructionSimplify.cpp Sat Jul 31 19:59:02 2010
@@ -440,27 +440,47 @@
const TargetData *TD) {
assert(From != To && "ReplaceAndSimplifyAllUses(X,X) is not valid!");
- // FromHandle - This keeps a weakvh on the from value so that we can know if
- // it gets deleted out from under us in a recursive simplification.
+ // FromHandle/ToHandle - This keeps a WeakVH on the from/to values so that
+ // we can know if it gets deleted out from under us or replaced in a
+ // recursive simplification.
WeakVH FromHandle(From);
+ WeakVH ToHandle(To);
while (!From->use_empty()) {
// Update the instruction to use the new value.
- Use &U = From->use_begin().getUse();
- Instruction *User = cast<Instruction>(U.getUser());
- U = To;
+ Use &TheUse = From->use_begin().getUse();
+ Instruction *User = cast<Instruction>(TheUse.getUser());
+ TheUse = To;
+
+ // Check to see if the instruction can be folded due to the operand
+ // replacement. For example changing (or X, Y) into (or X, -1) can replace
+ // the 'or' with -1.
+ Value *SimplifiedVal;
+ {
+ // Sanity check to make sure 'User' doesn't dangle across
+ // SimplifyInstruction.
+ AssertingVH<> UserHandle(User);
- // See if we can simplify it.
- if (Value *V = SimplifyInstruction(User, TD)) {
- // Recursively simplify this.
- ReplaceAndSimplifyAllUses(User, V, TD);
-
- // If the recursive simplification ended up revisiting and deleting 'From'
- // then we're done.
- if (FromHandle == 0)
- return;
+ SimplifiedVal = SimplifyInstruction(User, TD);
+ if (SimplifiedVal == 0) continue;
}
+
+ // Recursively simplify this user to the new value.
+ ReplaceAndSimplifyAllUses(User, SimplifiedVal, TD);
+ From = dyn_cast_or_null<Instruction>((Value*)FromHandle);
+ To = ToHandle;
+
+ assert(ToHandle && "To value deleted by recursive simplification?");
+
+ // If the recursive simplification ended up revisiting and deleting
+ // 'From' then we're done.
+ if (From == 0)
+ return;
}
+
+ // If 'From' has value handles referring to it, do a real RAUW to update them.
+ From->replaceAllUsesWith(To);
+
From->eraseFromParent();
}
Modified: llvm/branches/wendling/eh/lib/Analysis/IntervalPartition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/IntervalPartition.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/IntervalPartition.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/IntervalPartition.cpp Sat Jul 31 19:59:02 2010
@@ -16,8 +16,8 @@
using namespace llvm;
char IntervalPartition::ID = 0;
-static RegisterPass<IntervalPartition>
-X("intervals", "Interval Partition Construction", true, true);
+INITIALIZE_PASS(IntervalPartition, "intervals",
+ "Interval Partition Construction", true, true);
//===----------------------------------------------------------------------===//
// IntervalPartition Implementation
Modified: llvm/branches/wendling/eh/lib/Analysis/LazyValueInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/LazyValueInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/LazyValueInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/LazyValueInfo.cpp Sat Jul 31 19:59:02 2010
@@ -21,14 +21,16 @@
#include "llvm/Support/CFG.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/ValueHandle.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
char LazyValueInfo::ID = 0;
-static RegisterPass<LazyValueInfo>
-X("lazy-value-info", "Lazy Value Information Analysis", false, true);
+INITIALIZE_PASS(LazyValueInfo, "lazy-value-info",
+ "Lazy Value Information Analysis", false, true);
namespace llvm {
FunctionPass *createLazyValueInfoPass() { return new LazyValueInfo(); }
@@ -211,12 +213,36 @@
/// ValueCacheEntryTy - This is all of the cached block information for
/// exactly one Value*. The entries are sorted by the BasicBlock* of the
/// entries, allowing us to do a lookup with a binary search.
- typedef std::vector<BlockCacheEntryTy> ValueCacheEntryTy;
+ typedef std::map<BasicBlock*, LVILatticeVal> ValueCacheEntryTy;
private:
+ /// LVIValueHandle - A callback value handle update the cache when
+ /// values are erased.
+ struct LVIValueHandle : public CallbackVH {
+ LazyValueInfoCache *Parent;
+
+ LVIValueHandle(Value *V, LazyValueInfoCache *P)
+ : CallbackVH(V), Parent(P) { }
+
+ void deleted();
+ void allUsesReplacedWith(Value* V) {
+ deleted();
+ }
+
+ LVIValueHandle &operator=(Value *V) {
+ return *this = LVIValueHandle(V, Parent);
+ }
+ };
+
/// ValueCache - This is all of the cached information for all values,
/// mapped from Value* to key information.
- DenseMap<Value*, ValueCacheEntryTy> ValueCache;
+ std::map<LVIValueHandle, ValueCacheEntryTy> ValueCache;
+
+ /// OverDefinedCache - This tracks, on a per-block basis, the set of
+ /// values that are over-defined at the end of that block. This is required
+ /// for cache updating.
+ std::set<std::pair<BasicBlock*, Value*> > OverDefinedCache;
+
public:
/// getValueInBlock - This is the query interface to determine the lattice
@@ -226,30 +252,14 @@
/// getValueOnEdge - This is the query interface to determine the lattice
/// value for the specified Value* that is true on the specified edge.
LVILatticeVal getValueOnEdge(Value *V, BasicBlock *FromBB,BasicBlock *ToBB);
+
+ /// threadEdge - This is the update interface to inform the cache that an
+ /// edge from PredBB to OldSucc has been threaded to be from PredBB to
+ /// NewSucc.
+ void threadEdge(BasicBlock *PredBB,BasicBlock *OldSucc,BasicBlock *NewSucc);
};
} // end anonymous namespace
-namespace {
- struct BlockCacheEntryComparator {
- static int Compare(const void *LHSv, const void *RHSv) {
- const LazyValueInfoCache::BlockCacheEntryTy *LHS =
- static_cast<const LazyValueInfoCache::BlockCacheEntryTy *>(LHSv);
- const LazyValueInfoCache::BlockCacheEntryTy *RHS =
- static_cast<const LazyValueInfoCache::BlockCacheEntryTy *>(RHSv);
- if (LHS->first < RHS->first)
- return -1;
- if (LHS->first > RHS->first)
- return 1;
- return 0;
- }
-
- bool operator()(const LazyValueInfoCache::BlockCacheEntryTy &LHS,
- const LazyValueInfoCache::BlockCacheEntryTy &RHS) const {
- return LHS.first < RHS.first;
- }
- };
-}
-
//===----------------------------------------------------------------------===//
// LVIQuery Impl
//===----------------------------------------------------------------------===//
@@ -267,45 +277,36 @@
/// This is the current value being queried for.
Value *Val;
+ /// This is a pointer to the owning cache, for recursive queries.
+ LazyValueInfoCache &Parent;
+
/// This is all of the cached information about this value.
ValueCacheEntryTy &Cache;
+ /// This tracks, for each block, what values are overdefined.
+ std::set<std::pair<BasicBlock*, Value*> > &OverDefinedCache;
+
/// NewBlocks - This is a mapping of the new BasicBlocks which have been
/// added to cache but that are not in sorted order.
- DenseMap<BasicBlock*, LVILatticeVal> NewBlockInfo;
+ DenseSet<BasicBlock*> NewBlockInfo;
public:
- LVIQuery(Value *V, ValueCacheEntryTy &VC) : Val(V), Cache(VC) {
+ LVIQuery(Value *V, LazyValueInfoCache &P,
+ ValueCacheEntryTy &VC,
+ std::set<std::pair<BasicBlock*, Value*> > &ODC)
+ : Val(V), Parent(P), Cache(VC), OverDefinedCache(ODC) {
}
~LVIQuery() {
// When the query is done, insert the newly discovered facts into the
// cache in sorted order.
if (NewBlockInfo.empty()) return;
-
- // Grow the cache to exactly fit the new data.
- Cache.reserve(Cache.size() + NewBlockInfo.size());
- // If we only have one new entry, insert it instead of doing a full-on
- // sort.
- if (NewBlockInfo.size() == 1) {
- BlockCacheEntryTy Entry = *NewBlockInfo.begin();
- ValueCacheEntryTy::iterator I =
- std::lower_bound(Cache.begin(), Cache.end(), Entry,
- BlockCacheEntryComparator());
- assert((I == Cache.end() || I->first != Entry.first) &&
- "Entry already in map!");
-
- Cache.insert(I, Entry);
- return;
+ for (DenseSet<BasicBlock*>::iterator I = NewBlockInfo.begin(),
+ E = NewBlockInfo.end(); I != E; ++I) {
+ if (Cache[*I].isOverdefined())
+ OverDefinedCache.insert(std::make_pair(*I, Val));
}
-
- // TODO: If we only have two new elements, INSERT them both.
-
- Cache.insert(Cache.end(), NewBlockInfo.begin(), NewBlockInfo.end());
- array_pod_sort(Cache.begin(), Cache.end(),
- BlockCacheEntryComparator::Compare);
-
}
LVILatticeVal getBlockValue(BasicBlock *BB);
@@ -316,24 +317,25 @@
};
} // end anonymous namespace
+void LazyValueInfoCache::LVIValueHandle::deleted() {
+ Parent->ValueCache.erase(*this);
+ for (std::set<std::pair<BasicBlock*, Value*> >::iterator
+ I = Parent->OverDefinedCache.begin(),
+ E = Parent->OverDefinedCache.end();
+ I != E; ) {
+ std::set<std::pair<BasicBlock*, Value*> >::iterator tmp = I;
+ ++I;
+ if (tmp->second == getValPtr())
+ Parent->OverDefinedCache.erase(tmp);
+ }
+}
+
+
/// getCachedEntryForBlock - See if we already have a value for this block. If
-/// so, return it, otherwise create a new entry in the NewBlockInfo map to use.
+/// so, return it, otherwise create a new entry in the Cache map to use.
LVILatticeVal &LVIQuery::getCachedEntryForBlock(BasicBlock *BB) {
-
- // Do a binary search to see if we already have an entry for this block in
- // the cache set. If so, find it.
- if (!Cache.empty()) {
- ValueCacheEntryTy::iterator Entry =
- std::lower_bound(Cache.begin(), Cache.end(),
- BlockCacheEntryTy(BB, LVILatticeVal()),
- BlockCacheEntryComparator());
- if (Entry != Cache.end() && Entry->first == BB)
- return Entry->second;
- }
-
- // Otherwise, check to see if it's in NewBlockInfo or create a new entry if
- // not.
- return NewBlockInfo[BB];
+ NewBlockInfo.insert(BB);
+ return Cache[BB];
}
LVILatticeVal LVIQuery::getBlockValue(BasicBlock *BB) {
@@ -388,8 +390,27 @@
// If this value is defined by an instruction in this block, we have to
// process it here somehow or return overdefined.
if (PHINode *PN = dyn_cast<PHINode>(BBI)) {
- (void)PN;
- // TODO: PHI Translation in preds.
+ LVILatticeVal Result; // Start Undefined.
+
+ // Loop over all of our predecessors, merging what we know from them into
+ // result.
+ for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
+ Value* PhiVal = PN->getIncomingValueForBlock(*PI);
+ Result.mergeIn(Parent.getValueOnEdge(PhiVal, *PI, BB));
+
+ // If we hit overdefined, exit early. The BlockVals entry is already set
+ // to overdefined.
+ if (Result.isOverdefined()) {
+ DEBUG(dbgs() << " compute BB '" << BB->getName()
+ << "' - overdefined because of pred.\n");
+ return Result;
+ }
+ }
+
+ // Return the merged value, which is more precise than 'overdefined'.
+ assert(!Result.isOverdefined());
+ return getCachedEntryForBlock(BB) = Result;
+
} else {
}
@@ -474,7 +495,9 @@
DEBUG(dbgs() << "LVI Getting block end value " << *V << " at '"
<< BB->getName() << "'\n");
- LVILatticeVal Result = LVIQuery(V, ValueCache[V]).getBlockValue(BB);
+ LVILatticeVal Result = LVIQuery(V, *this,
+ ValueCache[LVIValueHandle(V, this)],
+ OverDefinedCache).getBlockValue(BB);
DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
@@ -488,14 +511,76 @@
DEBUG(dbgs() << "LVI Getting edge value " << *V << " from '"
<< FromBB->getName() << "' to '" << ToBB->getName() << "'\n");
+
LVILatticeVal Result =
- LVIQuery(V, ValueCache[V]).getEdgeValue(FromBB, ToBB);
+ LVIQuery(V, *this, ValueCache[LVIValueHandle(V, this)],
+ OverDefinedCache).getEdgeValue(FromBB, ToBB);
DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}
+void LazyValueInfoCache::threadEdge(BasicBlock *PredBB, BasicBlock *OldSucc,
+ BasicBlock *NewSucc) {
+ // When an edge in the graph has been threaded, values that we could not
+ // determine a value for before (i.e. were marked overdefined) may be possible
+ // to solve now. We do NOT try to proactively update these values. Instead,
+ // we clear their entries from the cache, and allow lazy updating to recompute
+ // them when needed.
+
+ // The updating process is fairly simple: we need to dropped cached info
+ // for all values that were marked overdefined in OldSucc, and for those same
+ // values in any successor of OldSucc (except NewSucc) in which they were
+ // also marked overdefined.
+ std::vector<BasicBlock*> worklist;
+ worklist.push_back(OldSucc);
+
+ DenseSet<Value*> ClearSet;
+ for (std::set<std::pair<BasicBlock*, Value*> >::iterator
+ I = OverDefinedCache.begin(), E = OverDefinedCache.end(); I != E; ++I) {
+ if (I->first == OldSucc)
+ ClearSet.insert(I->second);
+ }
+
+ // Use a worklist to perform a depth-first search of OldSucc's successors.
+ // NOTE: We do not need a visited list since any blocks we have already
+ // visited will have had their overdefined markers cleared already, and we
+ // thus won't loop to their successors.
+ while (!worklist.empty()) {
+ BasicBlock *ToUpdate = worklist.back();
+ worklist.pop_back();
+
+ // Skip blocks only accessible through NewSucc.
+ if (ToUpdate == NewSucc) continue;
+
+ bool changed = false;
+ for (DenseSet<Value*>::iterator I = ClearSet.begin(),E = ClearSet.end();
+ I != E; ++I) {
+ // If a value was marked overdefined in OldSucc, and is here too...
+ std::set<std::pair<BasicBlock*, Value*> >::iterator OI =
+ OverDefinedCache.find(std::make_pair(ToUpdate, *I));
+ if (OI == OverDefinedCache.end()) continue;
+
+ // Remove it from the caches.
+ ValueCacheEntryTy &Entry = ValueCache[LVIValueHandle(*I, this)];
+ ValueCacheEntryTy::iterator CI = Entry.find(ToUpdate);
+
+ assert(CI != Entry.end() && "Couldn't find entry to update?");
+ Entry.erase(CI);
+ OverDefinedCache.erase(OI);
+
+ // If we removed anything, then we potentially need to update
+ // blocks successors too.
+ changed = true;
+ }
+
+ if (!changed) continue;
+
+ worklist.insert(worklist.end(), succ_begin(ToUpdate), succ_end(ToUpdate));
+ }
+}
+
//===----------------------------------------------------------------------===//
// LazyValueInfo Impl
//===----------------------------------------------------------------------===//
@@ -579,4 +664,7 @@
return Unknown;
}
-
+void LazyValueInfo::threadEdge(BasicBlock *PredBB, BasicBlock *OldSucc,
+ BasicBlock* NewSucc) {
+ getCache(PImpl).threadEdge(PredBB, OldSucc, NewSucc);
+}
Modified: llvm/branches/wendling/eh/lib/Analysis/LibCallAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/LibCallAliasAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/LibCallAliasAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/LibCallAliasAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -20,11 +20,8 @@
// Register this pass...
char LibCallAliasAnalysis::ID = 0;
-static RegisterPass<LibCallAliasAnalysis>
-X("libcall-aa", "LibCall Alias Analysis", false, true);
-
-// Declare that we implement the AliasAnalysis interface
-static RegisterAnalysisGroup<AliasAnalysis> Y(X);
+INITIALIZE_AG_PASS(LibCallAliasAnalysis, AliasAnalysis, "libcall-aa",
+ "LibCall Alias Analysis", false, true, false);
FunctionPass *llvm::createLibCallAliasAnalysisPass(LibCallInfo *LCI) {
return new LibCallAliasAnalysis(LCI);
Modified: llvm/branches/wendling/eh/lib/Analysis/Lint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/Lint.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/Lint.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/Lint.cpp Sat Jul 31 19:59:02 2010
@@ -167,8 +167,7 @@
}
char Lint::ID = 0;
-static RegisterPass<Lint>
-X("lint", "Statically lint-checks LLVM IR", false, true);
+INITIALIZE_PASS(Lint, "lint", "Statically lint-checks LLVM IR", false, true);
// Assert - We know that cond should be true, if not print an error message.
#define Assert(C, M) \
Modified: llvm/branches/wendling/eh/lib/Analysis/LiveValues.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/LiveValues.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/LiveValues.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/LiveValues.cpp Sat Jul 31 19:59:02 2010
@@ -22,8 +22,8 @@
}
char LiveValues::ID = 0;
-static RegisterPass<LiveValues>
-X("live-values", "Value Liveness Analysis", false, true);
+INITIALIZE_PASS(LiveValues, "live-values",
+ "Value Liveness Analysis", false, true);
LiveValues::LiveValues() : FunctionPass(&ID) {}
Modified: llvm/branches/wendling/eh/lib/Analysis/LoopDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/LoopDependenceAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/LoopDependenceAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/LoopDependenceAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -46,8 +46,8 @@
return new LoopDependenceAnalysis();
}
-static RegisterPass<LoopDependenceAnalysis>
-R("lda", "Loop Dependence Analysis", false, true);
+INITIALIZE_PASS(LoopDependenceAnalysis, "lda",
+ "Loop Dependence Analysis", false, true);
char LoopDependenceAnalysis::ID = 0;
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/Analysis/LoopInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/LoopInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/LoopInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/LoopInfo.cpp Sat Jul 31 19:59:02 2010
@@ -38,8 +38,7 @@
cl::desc("Verify loop info (time consuming)"));
char LoopInfo::ID = 0;
-static RegisterPass<LoopInfo>
-X("loops", "Natural Loop Information", true, true);
+INITIALIZE_PASS(LoopInfo, "loops", "Natural Loop Information", true, true);
//===----------------------------------------------------------------------===//
// Loop implementation
@@ -124,14 +123,13 @@
BasicBlock *H = getHeader();
BasicBlock *Incoming = 0, *Backedge = 0;
- typedef GraphTraits<Inverse<BasicBlock*> > InvBlockTraits;
- InvBlockTraits::ChildIteratorType PI = InvBlockTraits::child_begin(H);
- assert(PI != InvBlockTraits::child_end(H) &&
+ pred_iterator PI = pred_begin(H);
+ assert(PI != pred_end(H) &&
"Loop must have at least one backedge!");
Backedge = *PI++;
- if (PI == InvBlockTraits::child_end(H)) return 0; // dead loop
+ if (PI == pred_end(H)) return 0; // dead loop
Incoming = *PI++;
- if (PI != InvBlockTraits::child_end(H)) return 0; // multiple backedges?
+ if (PI != pred_end(H)) return 0; // multiple backedges?
if (contains(Incoming)) {
if (contains(Backedge))
@@ -157,18 +155,6 @@
return 0;
}
-/// getCanonicalInductionVariableIncrement - Return the LLVM value that holds
-/// the canonical induction variable value for the "next" iteration of the
-/// loop. This always succeeds if getCanonicalInductionVariable succeeds.
-///
-Instruction *Loop::getCanonicalInductionVariableIncrement() const {
- if (PHINode *PN = getCanonicalInductionVariable()) {
- bool P1InLoop = contains(PN->getIncomingBlock(1));
- return cast<Instruction>(PN->getIncomingValue(P1InLoop));
- }
- return 0;
-}
-
/// getTripCount - Return a loop-invariant LLVM value indicating the number of
/// times the loop will be executed. Note that this means that the backedge
/// of the loop executes N-1 times. If the trip-count cannot be determined,
@@ -180,12 +166,12 @@
Value *Loop::getTripCount() const {
// Canonical loops will end with a 'cmp ne I, V', where I is the incremented
// canonical induction variable and V is the trip count of the loop.
- Instruction *Inc = getCanonicalInductionVariableIncrement();
- if (Inc == 0) return 0;
- PHINode *IV = cast<PHINode>(Inc->getOperand(0));
+ PHINode *IV = getCanonicalInductionVariable();
+ if (IV == 0 || IV->getNumIncomingValues() != 2) return 0;
- BasicBlock *BackedgeBlock =
- IV->getIncomingBlock(contains(IV->getIncomingBlock(1)));
+ bool P0InLoop = contains(IV->getIncomingBlock(0));
+ Value *Inc = IV->getIncomingValue(!P0InLoop);
+ BasicBlock *BackedgeBlock = IV->getIncomingBlock(!P0InLoop);
if (BranchInst *BI = dyn_cast<BranchInst>(BackedgeBlock->getTerminator()))
if (BI->isConditional()) {
@@ -341,16 +327,12 @@
BasicBlock *current = *BI;
switchExitBlocks.clear();
- typedef GraphTraits<BasicBlock *> BlockTraits;
- typedef GraphTraits<Inverse<BasicBlock *> > InvBlockTraits;
- for (BlockTraits::ChildIteratorType I =
- BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
- I != E; ++I) {
+ for (succ_iterator I = succ_begin(*BI), E = succ_end(*BI); I != E; ++I) {
// If block is inside the loop then it is not a exit block.
if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))
continue;
- InvBlockTraits::ChildIteratorType PI = InvBlockTraits::child_begin(*I);
+ pred_iterator PI = pred_begin(*I);
BasicBlock *firstPred = *PI;
// If current basic block is this exit block's first predecessor
@@ -363,8 +345,7 @@
// If a terminator has more then two successors, for example SwitchInst,
// then it is possible that there are multiple edges from current block
// to one exit block.
- if (std::distance(BlockTraits::child_begin(current),
- BlockTraits::child_end(current)) <= 2) {
+ if (std::distance(succ_begin(current), succ_end(current)) <= 2) {
ExitBlocks.push_back(*I);
continue;
}
Modified: llvm/branches/wendling/eh/lib/Analysis/MemoryDependenceAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/MemoryDependenceAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/MemoryDependenceAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -46,8 +46,8 @@
char MemoryDependenceAnalysis::ID = 0;
// Register this pass...
-static RegisterPass<MemoryDependenceAnalysis> X("memdep",
- "Memory Dependence Analysis", false, true);
+INITIALIZE_PASS(MemoryDependenceAnalysis, "memdep",
+ "Memory Dependence Analysis", false, true);
MemoryDependenceAnalysis::MemoryDependenceAnalysis()
: FunctionPass(&ID), PredCache(0) {
@@ -120,10 +120,9 @@
Pointer = CI->getArgOperand(0);
// calls to free() erase the entire structure
PointerSize = ~0ULL;
- } else if (isa<CallInst>(Inst) || isa<InvokeInst>(Inst)) {
+ } else if (CallSite InstCS = cast<Value>(Inst)) {
// Debug intrinsics don't cause dependences.
if (isa<DbgInfoIntrinsic>(Inst)) continue;
- CallSite InstCS = CallSite::get(Inst);
// If these two calls do not interfere, look past it.
switch (AA->getModRefInfo(CS, InstCS)) {
case AliasAnalysis::NoModRef:
@@ -387,7 +386,7 @@
MemSize = cast<ConstantInt>(II->getArgOperand(1))->getZExtValue();
break;
default:
- CallSite QueryCS = CallSite::get(QueryInst);
+ CallSite QueryCS(QueryInst);
bool isReadOnly = AA->onlyReadsMemory(QueryCS);
LocalCache = getCallSiteDependencyFrom(QueryCS, isReadOnly, ScanPos,
QueryParent);
Modified: llvm/branches/wendling/eh/lib/Analysis/ModuleDebugInfoPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ModuleDebugInfoPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ModuleDebugInfoPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ModuleDebugInfoPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -42,9 +42,8 @@
}
char ModuleDebugInfoPrinter::ID = 0;
-static RegisterPass<ModuleDebugInfoPrinter>
-X("module-debuginfo",
- "Decodes module-level debug info", false, true);
+INITIALIZE_PASS(ModuleDebugInfoPrinter, "module-debuginfo",
+ "Decodes module-level debug info", false, true);
ModulePass *llvm::createModuleDebugInfoPrinterPass() {
return new ModuleDebugInfoPrinter();
Modified: llvm/branches/wendling/eh/lib/Analysis/PointerTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/PointerTracking.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/PointerTracking.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/PointerTracking.cpp Sat Jul 31 19:59:02 2010
@@ -263,5 +263,5 @@
}
}
-static RegisterPass<PointerTracking> X("pointertracking",
- "Track pointer bounds", false, true);
+INITIALIZE_PASS(PointerTracking, "pointertracking",
+ "Track pointer bounds", false, true);
Modified: llvm/branches/wendling/eh/lib/Analysis/PostDominators.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/PostDominators.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/PostDominators.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/PostDominators.cpp Sat Jul 31 19:59:02 2010
@@ -28,8 +28,8 @@
char PostDominatorTree::ID = 0;
char PostDominanceFrontier::ID = 0;
-static RegisterPass<PostDominatorTree>
-F("postdomtree", "Post-Dominator Tree Construction", true, true);
+INITIALIZE_PASS(PostDominatorTree, "postdomtree",
+ "Post-Dominator Tree Construction", true, true);
bool PostDominatorTree::runOnFunction(Function &F) {
DT->recalculate(F);
@@ -53,8 +53,8 @@
// PostDominanceFrontier Implementation
//===----------------------------------------------------------------------===//
-static RegisterPass<PostDominanceFrontier>
-H("postdomfrontier", "Post-Dominance Frontier Construction", true, true);
+INITIALIZE_PASS(PostDominanceFrontier, "postdomfrontier",
+ "Post-Dominance Frontier Construction", true, true);
const DominanceFrontier::DomSetType &
PostDominanceFrontier::calculate(const PostDominatorTree &DT,
Modified: llvm/branches/wendling/eh/lib/Analysis/ProfileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ProfileInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ProfileInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ProfileInfo.cpp Sat Jul 31 19:59:02 2010
@@ -71,22 +71,24 @@
// Are there zero predecessors of this block?
if (PI == PE) {
- Edge e = getEdge(0,BB);
+ Edge e = getEdge(0, BB);
Count = getEdgeWeight(e);
} else {
// Otherwise, if there are predecessors, the execution count of this block is
// the sum of the edge frequencies from the incoming edges.
std::set<const BasicBlock*> ProcessedPreds;
Count = 0;
- for (; PI != PE; ++PI)
- if (ProcessedPreds.insert(*PI).second) {
- double w = getEdgeWeight(getEdge(*PI, BB));
+ for (; PI != PE; ++PI) {
+ const BasicBlock *P = *PI;
+ if (ProcessedPreds.insert(P).second) {
+ double w = getEdgeWeight(getEdge(P, BB));
if (w == MissingValue) {
Count = MissingValue;
break;
}
Count += w;
}
+ }
}
// If the predecessors did not suffice to get block weight, try successors.
@@ -1094,10 +1096,7 @@
char NoProfileInfo::ID = 0;
// Register this pass...
-static RegisterPass<NoProfileInfo>
-X("no-profile", "No Profile Information", false, true);
-
-// Declare that we implement the ProfileInfo interface
-static RegisterAnalysisGroup<ProfileInfo, true> Y(X);
+INITIALIZE_AG_PASS(NoProfileInfo, ProfileInfo, "no-profile",
+ "No Profile Information", false, true, true);
ImmutablePass *llvm::createNoProfileInfoPass() { return new NoProfileInfo(); }
Modified: llvm/branches/wendling/eh/lib/Analysis/ProfileVerifierPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ProfileVerifierPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ProfileVerifierPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ProfileVerifierPass.cpp Sat Jul 31 19:59:02 2010
@@ -366,8 +366,8 @@
char ProfileVerifierPassT<FType, BType>::ID = 0;
}
-static RegisterPass<ProfileVerifierPass>
-X("profile-verifier", "Verify profiling information", false, true);
+INITIALIZE_PASS(ProfileVerifierPass, "profile-verifier",
+ "Verify profiling information", false, true);
namespace llvm {
FunctionPass *createProfileVerifierPass() {
Modified: llvm/branches/wendling/eh/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ScalarEvolution.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ScalarEvolution.cpp Sat Jul 31 19:59:02 2010
@@ -103,8 +103,8 @@
"derived loop"),
cl::init(100));
-static RegisterPass<ScalarEvolution>
-R("scalar-evolution", "Scalar Evolution Analysis", false, true);
+INITIALIZE_PASS(ScalarEvolution, "scalar-evolution",
+ "Scalar Evolution Analysis", false, true);
char ScalarEvolution::ID = 0;
//===----------------------------------------------------------------------===//
@@ -495,9 +495,9 @@
/// than the complexity of the RHS. This comparator is used to canonicalize
/// expressions.
class SCEVComplexityCompare {
- LoopInfo *LI;
+ const LoopInfo *LI;
public:
- explicit SCEVComplexityCompare(LoopInfo *li) : LI(li) {}
+ explicit SCEVComplexityCompare(const LoopInfo *li) : LI(li) {}
bool operator()(const SCEV *LHS, const SCEV *RHS) const {
// Fast-path: SCEVs are uniqued so we can do a quick equality check.
@@ -505,8 +505,9 @@
return false;
// Primarily, sort the SCEVs by their getSCEVType().
- if (LHS->getSCEVType() != RHS->getSCEVType())
- return LHS->getSCEVType() < RHS->getSCEVType();
+ unsigned LType = LHS->getSCEVType(), RType = RHS->getSCEVType();
+ if (LType != RType)
+ return LType < RType;
// Aside from the getSCEVType() ordering, the particular ordering
// isn't very important except that it's beneficial to be consistent,
@@ -519,14 +520,16 @@
// Order pointer values after integer values. This helps SCEVExpander
// form GEPs.
- if (LU->getType()->isPointerTy() && !RU->getType()->isPointerTy())
- return false;
- if (RU->getType()->isPointerTy() && !LU->getType()->isPointerTy())
- return true;
+ bool LIsPointer = LU->getType()->isPointerTy(),
+ RIsPointer = RU->getType()->isPointerTy();
+ if (LIsPointer != RIsPointer)
+ return RIsPointer;
// Compare getValueID values.
- if (LU->getValue()->getValueID() != RU->getValue()->getValueID())
- return LU->getValue()->getValueID() < RU->getValue()->getValueID();
+ unsigned LID = LU->getValue()->getValueID(),
+ RID = RU->getValue()->getValueID();
+ if (LID != RID)
+ return LID < RID;
// Sort arguments by their position.
if (const Argument *LA = dyn_cast<Argument>(LU->getValue())) {
@@ -536,22 +539,20 @@
// For instructions, compare their loop depth, and their opcode.
// This is pretty loose.
- if (Instruction *LV = dyn_cast<Instruction>(LU->getValue())) {
- Instruction *RV = cast<Instruction>(RU->getValue());
+ if (const Instruction *LV = dyn_cast<Instruction>(LU->getValue())) {
+ const Instruction *RV = cast<Instruction>(RU->getValue());
// Compare loop depths.
- if (LI->getLoopDepth(LV->getParent()) !=
- LI->getLoopDepth(RV->getParent()))
- return LI->getLoopDepth(LV->getParent()) <
- LI->getLoopDepth(RV->getParent());
-
- // Compare opcodes.
- if (LV->getOpcode() != RV->getOpcode())
- return LV->getOpcode() < RV->getOpcode();
+ unsigned LDepth = LI->getLoopDepth(LV->getParent()),
+ RDepth = LI->getLoopDepth(RV->getParent());
+ if (LDepth != RDepth)
+ return LDepth < RDepth;
// Compare the number of operands.
- if (LV->getNumOperands() != RV->getNumOperands())
- return LV->getNumOperands() < RV->getNumOperands();
+ unsigned LNumOps = LV->getNumOperands(),
+ RNumOps = RV->getNumOperands();
+ if (LNumOps != RNumOps)
+ return LNumOps < RNumOps;
}
return false;
@@ -560,42 +561,51 @@
// Compare constant values.
if (const SCEVConstant *LC = dyn_cast<SCEVConstant>(LHS)) {
const SCEVConstant *RC = cast<SCEVConstant>(RHS);
- if (LC->getValue()->getBitWidth() != RC->getValue()->getBitWidth())
- return LC->getValue()->getBitWidth() < RC->getValue()->getBitWidth();
- return LC->getValue()->getValue().ult(RC->getValue()->getValue());
+ const ConstantInt *LCC = LC->getValue();
+ const ConstantInt *RCC = RC->getValue();
+ unsigned LBitWidth = LCC->getBitWidth(), RBitWidth = RCC->getBitWidth();
+ if (LBitWidth != RBitWidth)
+ return LBitWidth < RBitWidth;
+ return LCC->getValue().ult(RCC->getValue());
}
// Compare addrec loop depths.
if (const SCEVAddRecExpr *LA = dyn_cast<SCEVAddRecExpr>(LHS)) {
const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS);
- if (LA->getLoop()->getLoopDepth() != RA->getLoop()->getLoopDepth())
- return LA->getLoop()->getLoopDepth() < RA->getLoop()->getLoopDepth();
+ unsigned LDepth = LA->getLoop()->getLoopDepth(),
+ RDepth = RA->getLoop()->getLoopDepth();
+ if (LDepth != RDepth)
+ return LDepth < RDepth;
}
// Lexicographically compare n-ary expressions.
if (const SCEVNAryExpr *LC = dyn_cast<SCEVNAryExpr>(LHS)) {
const SCEVNAryExpr *RC = cast<SCEVNAryExpr>(RHS);
- for (unsigned i = 0, e = LC->getNumOperands(); i != e; ++i) {
- if (i >= RC->getNumOperands())
+ unsigned LNumOps = LC->getNumOperands(), RNumOps = RC->getNumOperands();
+ for (unsigned i = 0; i != LNumOps; ++i) {
+ if (i >= RNumOps)
return false;
- if (operator()(LC->getOperand(i), RC->getOperand(i)))
+ const SCEV *LOp = LC->getOperand(i), *ROp = RC->getOperand(i);
+ if (operator()(LOp, ROp))
return true;
- if (operator()(RC->getOperand(i), LC->getOperand(i)))
+ if (operator()(ROp, LOp))
return false;
}
- return LC->getNumOperands() < RC->getNumOperands();
+ return LNumOps < RNumOps;
}
// Lexicographically compare udiv expressions.
if (const SCEVUDivExpr *LC = dyn_cast<SCEVUDivExpr>(LHS)) {
const SCEVUDivExpr *RC = cast<SCEVUDivExpr>(RHS);
- if (operator()(LC->getLHS(), RC->getLHS()))
+ const SCEV *LL = LC->getLHS(), *LR = LC->getRHS(),
+ *RL = RC->getLHS(), *RR = RC->getRHS();
+ if (operator()(LL, RL))
return true;
- if (operator()(RC->getLHS(), LC->getLHS()))
+ if (operator()(RL, LL))
return false;
- if (operator()(LC->getRHS(), RC->getRHS()))
+ if (operator()(LR, RR))
return true;
- if (operator()(RC->getRHS(), LC->getRHS()))
+ if (operator()(RR, LR))
return false;
return false;
}
@@ -845,6 +855,13 @@
return getAddRecExpr(Operands, AddRec->getLoop());
}
+ // As a special case, fold trunc(undef) to undef. We don't want to
+ // know too much about SCEVUnknowns, but this special case is handy
+ // and harmless.
+ if (const SCEVUnknown *U = dyn_cast<SCEVUnknown>(Op))
+ if (isa<UndefValue>(U->getValue()))
+ return getSCEV(UndefValue::get(Ty));
+
// The cast wasn't folded; create an explicit cast node. We can reuse
// the existing insert position since if we get here, we won't have
// made any changes which would invalidate it.
@@ -1163,6 +1180,13 @@
return getAddRecExpr(Ops, AR->getLoop());
}
+ // As a special case, fold anyext(undef) to undef. We don't want to
+ // know too much about SCEVUnknowns, but this special case is handy
+ // and harmless.
+ if (const SCEVUnknown *U = dyn_cast<SCEVUnknown>(Op))
+ if (isa<UndefValue>(U->getValue()))
+ return getSCEV(UndefValue::get(Ty));
+
// If the expression is obviously signed, use the sext cast value.
if (isa<SCEVSMaxExpr>(Op))
return SExt;
@@ -2428,6 +2452,10 @@
///
const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS,
const SCEV *RHS) {
+ // Fast path: X - X --> 0.
+ if (LHS == RHS)
+ return getConstant(LHS->getType(), 0);
+
// X - Y --> X + -Y
return getAddExpr(LHS, getNegativeSCEV(RHS));
}
@@ -2570,7 +2598,7 @@
// Push the def-use children onto the Worklist stack.
for (Value::use_iterator UI = I->use_begin(), UE = I->use_end();
UI != UE; ++UI)
- Worklist.push_back(cast<Instruction>(UI));
+ Worklist.push_back(cast<Instruction>(*UI));
}
/// ForgetSymbolicValue - This looks up computed SCEV values for all
@@ -3636,6 +3664,26 @@
/// changed a value in a way that may effect its value, or which may
/// disconnect it from a def-use chain linking it to a loop.
void ScalarEvolution::forgetValue(Value *V) {
+ // If there's a SCEVUnknown tying this value into the SCEV
+ // space, remove it from the folding set map. The SCEVUnknown
+ // object and any other SCEV objects which reference it
+ // (transitively) remain allocated, effectively leaked until
+ // the underlying BumpPtrAllocator is freed.
+ //
+ // This permits SCEV pointers to be used as keys in maps
+ // such as the ValuesAtScopes map.
+ FoldingSetNodeID ID;
+ ID.AddInteger(scUnknown);
+ ID.AddPointer(V);
+ void *IP;
+ if (SCEV *S = UniqueSCEVs.FindNodeOrInsertPos(ID, IP)) {
+ UniqueSCEVs.RemoveNode(S);
+
+ // This isn't necessary, but we might as well remove the
+ // value from the ValuesAtScopes map too.
+ ValuesAtScopes.erase(S);
+ }
+
Instruction *I = dyn_cast<Instruction>(V);
if (!I) return;
@@ -3657,26 +3705,6 @@
ConstantEvolutionLoopExitValue.erase(PN);
}
- // If there's a SCEVUnknown tying this value into the SCEV
- // space, remove it from the folding set map. The SCEVUnknown
- // object and any other SCEV objects which reference it
- // (transitively) remain allocated, effectively leaked until
- // the underlying BumpPtrAllocator is freed.
- //
- // This permits SCEV pointers to be used as keys in maps
- // such as the ValuesAtScopes map.
- FoldingSetNodeID ID;
- ID.AddInteger(scUnknown);
- ID.AddPointer(I);
- void *IP;
- if (SCEV *S = UniqueSCEVs.FindNodeOrInsertPos(ID, IP)) {
- UniqueSCEVs.RemoveNode(S);
-
- // This isn't necessary, but we might as well remove the
- // value from the ValuesAtScopes map too.
- ValuesAtScopes.erase(S);
- }
-
PushDefUseChildren(I, Worklist);
}
}
@@ -5662,16 +5690,32 @@
// this now dangles!
}
-void ScalarEvolution::SCEVCallbackVH::allUsesReplacedWith(Value *) {
+void ScalarEvolution::SCEVCallbackVH::allUsesReplacedWith(Value *V) {
assert(SE && "SCEVCallbackVH called with a null ScalarEvolution!");
+ Value *Old = getValPtr();
+
+ // If there's a SCEVUnknown tying this value into the SCEV
+ // space, replace the SCEVUnknown's value with the new value
+ // for the benefit of any SCEVs still referencing it, and
+ // and remove it from the folding set map so that new scevs
+ // don't reference it.
+ FoldingSetNodeID ID;
+ ID.AddInteger(scUnknown);
+ ID.AddPointer(Old);
+ void *IP;
+ if (SCEVUnknown *S = cast_or_null<SCEVUnknown>(
+ SE->UniqueSCEVs.FindNodeOrInsertPos(ID, IP))) {
+ S->V = V;
+ SE->UniqueSCEVs.RemoveNode(S);
+ SE->ValuesAtScopes.erase(S);
+ }
+
// Forget all the expressions associated with users of the old value,
// so that future queries will recompute the expressions using the new
// value.
SmallVector<User *, 16> Worklist;
SmallPtrSet<User *, 8> Visited;
- Value *Old = getValPtr();
- bool DeleteOld = false;
for (Value::use_iterator UI = Old->use_begin(), UE = Old->use_end();
UI != UE; ++UI)
Worklist.push_back(*UI);
@@ -5679,10 +5723,8 @@
User *U = Worklist.pop_back_val();
// Deleting the Old value will cause this to dangle. Postpone
// that until everything else is done.
- if (U == Old) {
- DeleteOld = true;
+ if (U == Old)
continue;
- }
if (!Visited.insert(U))
continue;
if (PHINode *PN = dyn_cast<PHINode>(U))
@@ -5692,14 +5734,11 @@
UI != UE; ++UI)
Worklist.push_back(*UI);
}
- // Delete the Old value if it (indirectly) references itself.
- if (DeleteOld) {
- if (PHINode *PN = dyn_cast<PHINode>(Old))
- SE->ConstantEvolutionLoopExitValue.erase(PN);
- SE->Scalars.erase(Old);
- // this now dangles!
- }
- // this may dangle!
+ // Delete the Old value.
+ if (PHINode *PN = dyn_cast<PHINode>(Old))
+ SE->ConstantEvolutionLoopExitValue.erase(PN);
+ SE->Scalars.erase(Old);
+ // this now dangles!
}
ScalarEvolution::SCEVCallbackVH::SCEVCallbackVH(Value *V, ScalarEvolution *se)
Modified: llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -58,11 +58,8 @@
// Register this pass...
char ScalarEvolutionAliasAnalysis::ID = 0;
-static RegisterPass<ScalarEvolutionAliasAnalysis>
-X("scev-aa", "ScalarEvolution-based Alias Analysis", false, true);
-
-// Declare that we implement the AliasAnalysis interface
-static RegisterAnalysisGroup<AliasAnalysis> Y(X);
+INITIALIZE_AG_PASS(ScalarEvolutionAliasAnalysis, AliasAnalysis, "scev-aa",
+ "ScalarEvolution-based Alias Analysis", false, true, false);
FunctionPass *llvm::createScalarEvolutionAliasAnalysisPass() {
return new ScalarEvolutionAliasAnalysis();
Modified: llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionExpander.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionExpander.cpp Sat Jul 31 19:59:02 2010
@@ -647,6 +647,11 @@
bool operator()(std::pair<const Loop *, const SCEV *> LHS,
std::pair<const Loop *, const SCEV *> RHS) const {
+ // Keep pointer operands sorted at the end.
+ if (LHS.second->getType()->isPointerTy() !=
+ RHS.second->getType()->isPointerTy())
+ return LHS.second->getType()->isPointerTy();
+
// Compare loops with PickMostRelevantLoop.
if (LHS.first != RHS.first)
return PickMostRelevantLoop(LHS.first, RHS.first, DT) != LHS.first;
@@ -699,8 +704,15 @@
// The running sum expression is a pointer. Try to form a getelementptr
// at this level with that as the base.
SmallVector<const SCEV *, 4> NewOps;
- for (; I != E && I->first == CurLoop; ++I)
- NewOps.push_back(I->second);
+ for (; I != E && I->first == CurLoop; ++I) {
+ // If the operand is SCEVUnknown and not instructions, peek through
+ // it, to enable more of it to be folded into the GEP.
+ const SCEV *X = I->second;
+ if (const SCEVUnknown *U = dyn_cast<SCEVUnknown>(X))
+ if (!isa<Instruction>(U->getValue()))
+ X = SE.getSCEV(U->getValue());
+ NewOps.push_back(X);
+ }
Sum = expandAddToGEP(NewOps.begin(), NewOps.end(), PTy, Ty, Sum);
} else if (const PointerType *PTy = dyn_cast<PointerType>(Op->getType())) {
// The running sum is an integer, and there's a pointer at this level.
@@ -1047,9 +1059,7 @@
// First check for an existing canonical IV in a suitable type.
PHINode *CanonicalIV = 0;
if (PHINode *PN = L->getCanonicalInductionVariable())
- if (SE.isSCEVable(PN->getType()) &&
- SE.getEffectiveSCEVType(PN->getType())->isIntegerTy() &&
- SE.getTypeSizeInBits(PN->getType()) >= SE.getTypeSizeInBits(Ty))
+ if (SE.getTypeSizeInBits(PN->getType()) >= SE.getTypeSizeInBits(Ty))
CanonicalIV = PN;
// Rewrite an AddRec in terms of the canonical induction variable, if
@@ -1102,21 +1112,13 @@
SE.getUnknown(expand(Rest))));
}
- // {0,+,1} --> Insert a canonical induction variable into the loop!
- if (S->isAffine() && S->getOperand(1)->isOne()) {
- // If there's a canonical IV, just use it.
- if (CanonicalIV) {
- assert(Ty == SE.getEffectiveSCEVType(CanonicalIV->getType()) &&
- "IVs with types different from the canonical IV should "
- "already have been handled!");
- return CanonicalIV;
- }
-
+ // If we don't yet have a canonical IV, create one.
+ if (!CanonicalIV) {
// Create and insert the PHI node for the induction variable in the
// specified loop.
BasicBlock *Header = L->getHeader();
- PHINode *PN = PHINode::Create(Ty, "indvar", Header->begin());
- rememberInstruction(PN);
+ CanonicalIV = PHINode::Create(Ty, "indvar", Header->begin());
+ rememberInstruction(CanonicalIV);
Constant *One = ConstantInt::get(Ty, 1);
for (pred_iterator HPI = pred_begin(Header), HPE = pred_end(Header);
@@ -1125,40 +1127,45 @@
if (L->contains(HP)) {
// Insert a unit add instruction right before the terminator
// corresponding to the back-edge.
- Instruction *Add = BinaryOperator::CreateAdd(PN, One, "indvar.next",
- HP->getTerminator());
+ Instruction *Add = BinaryOperator::CreateAdd(CanonicalIV, One,
+ "indvar.next",
+ HP->getTerminator());
rememberInstruction(Add);
- PN->addIncoming(Add, HP);
+ CanonicalIV->addIncoming(Add, HP);
} else {
- PN->addIncoming(Constant::getNullValue(Ty), HP);
+ CanonicalIV->addIncoming(Constant::getNullValue(Ty), HP);
}
}
}
+ // {0,+,1} --> Insert a canonical induction variable into the loop!
+ if (S->isAffine() && S->getOperand(1)->isOne()) {
+ assert(Ty == SE.getEffectiveSCEVType(CanonicalIV->getType()) &&
+ "IVs with types different from the canonical IV should "
+ "already have been handled!");
+ return CanonicalIV;
+ }
+
// {0,+,F} --> {0,+,1} * F
- // Get the canonical induction variable I for this loop.
- Value *I = CanonicalIV ?
- CanonicalIV :
- getOrInsertCanonicalInductionVariable(L, Ty);
// If this is a simple linear addrec, emit it now as a special case.
if (S->isAffine()) // {0,+,F} --> i*F
return
expand(SE.getTruncateOrNoop(
- SE.getMulExpr(SE.getUnknown(I),
+ SE.getMulExpr(SE.getUnknown(CanonicalIV),
SE.getNoopOrAnyExtend(S->getOperand(1),
- I->getType())),
+ CanonicalIV->getType())),
Ty));
// If this is a chain of recurrences, turn it into a closed form, using the
// folders, then expandCodeFor the closed form. This allows the folders to
// simplify the expression without having to build a bunch of special code
// into this folder.
- const SCEV *IH = SE.getUnknown(I); // Get I as a "symbolic" SCEV.
+ const SCEV *IH = SE.getUnknown(CanonicalIV); // Get I as a "symbolic" SCEV.
// Promote S up to the canonical IV type, if the cast is foldable.
const SCEV *NewS = S;
- const SCEV *Ext = SE.getNoopOrAnyExtend(S, I->getType());
+ const SCEV *Ext = SE.getNoopOrAnyExtend(S, CanonicalIV->getType());
if (isa<SCEVAddRecExpr>(Ext))
NewS = Ext;
@@ -1337,16 +1344,21 @@
/// canonical induction variable of the specified type for the specified
/// loop (inserting one if there is none). A canonical induction variable
/// starts at zero and steps by one on each iteration.
-Value *
+PHINode *
SCEVExpander::getOrInsertCanonicalInductionVariable(const Loop *L,
const Type *Ty) {
assert(Ty->isIntegerTy() && "Can only insert integer induction variables!");
+
+ // Build a SCEV for {0,+,1}<L>.
const SCEV *H = SE.getAddRecExpr(SE.getConstant(Ty, 0),
SE.getConstant(Ty, 1), L);
+
+ // Emit code for it.
BasicBlock *SaveInsertBB = Builder.GetInsertBlock();
BasicBlock::iterator SaveInsertPt = Builder.GetInsertPoint();
- Value *V = expandCodeFor(H, 0, L->getHeader()->begin());
+ PHINode *V = cast<PHINode>(expandCodeFor(H, 0, L->getHeader()->begin()));
if (SaveInsertBB)
restoreInsertPoint(SaveInsertBB, SaveInsertPt);
+
return V;
}
Modified: llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionNormalization.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionNormalization.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionNormalization.cpp (original)
+++ llvm/branches/wendling/eh/lib/Analysis/ScalarEvolutionNormalization.cpp Sat Jul 31 19:59:02 2010
@@ -26,7 +26,7 @@
/// post-inc value when we cannot) or it can end up adding extra live-ranges to
/// the loop, resulting in reg-reg copies (if we use the pre-inc value when we
/// should use the post-inc value).
-static bool IVUseShouldUsePostIncValue(Instruction *User, Instruction *IV,
+static bool IVUseShouldUsePostIncValue(Instruction *User, Value *Operand,
const Loop *L, DominatorTree *DT) {
// If the user is in the loop, use the preinc value.
if (L->contains(User)) return false;
@@ -45,20 +45,17 @@
// their uses occur in the predecessor block, not the block the PHI lives in)
// should still use the post-inc value. Check for this case now.
PHINode *PN = dyn_cast<PHINode>(User);
- if (!PN) return false; // not a phi, not dominated by latch block.
+ if (!PN || !Operand) return false; // not a phi, not dominated by latch block.
- // Look at all of the uses of IV by the PHI node. If any use corresponds to
- // a block that is not dominated by the latch block, give up and use the
+ // Look at all of the uses of Operand by the PHI node. If any use corresponds
+ // to a block that is not dominated by the latch block, give up and use the
// preincremented value.
- unsigned NumUses = 0;
for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
- if (PN->getIncomingValue(i) == IV) {
- ++NumUses;
- if (!DT->dominates(LatchBlock, PN->getIncomingBlock(i)))
- return false;
- }
+ if (PN->getIncomingValue(i) == Operand &&
+ !DT->dominates(LatchBlock, PN->getIncomingBlock(i)))
+ return false;
- // Okay, all uses of IV by PN are in predecessor blocks that really are
+ // Okay, all uses of Operand by PN are in predecessor blocks that really are
// dominated by the latch block. Use the post-incremented value.
return true;
}
@@ -72,6 +69,7 @@
DominatorTree &DT) {
if (isa<SCEVConstant>(S) || isa<SCEVUnknown>(S))
return S;
+
if (const SCEVCastExpr *X = dyn_cast<SCEVCastExpr>(S)) {
const SCEV *O = X->getOperand();
const SCEV *N = TransformForPostIncUse(Kind, O, User, OperandValToReplace,
@@ -85,9 +83,64 @@
}
return S;
}
+
+ if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S)) {
+ // An addrec. This is the interesting part.
+ SmallVector<const SCEV *, 8> Operands;
+ const Loop *L = AR->getLoop();
+ // The addrec conceptually uses its operands at loop entry.
+ Instruction *LUser = L->getHeader()->begin();
+ // Transform each operand.
+ for (SCEVNAryExpr::op_iterator I = AR->op_begin(), E = AR->op_end();
+ I != E; ++I) {
+ const SCEV *O = *I;
+ const SCEV *N = TransformForPostIncUse(Kind, O, LUser, 0, Loops, SE, DT);
+ Operands.push_back(N);
+ }
+ const SCEV *Result = SE.getAddRecExpr(Operands, L);
+ switch (Kind) {
+ default: llvm_unreachable("Unexpected transform name!");
+ case NormalizeAutodetect:
+ if (IVUseShouldUsePostIncValue(User, OperandValToReplace, L, &DT)) {
+ const SCEV *TransformedStep =
+ TransformForPostIncUse(Kind, AR->getStepRecurrence(SE),
+ User, OperandValToReplace, Loops, SE, DT);
+ Result = SE.getMinusSCEV(Result, TransformedStep);
+ Loops.insert(L);
+ }
+#ifdef XDEBUG
+ assert(S == TransformForPostIncUse(Denormalize, Result,
+ User, OperandValToReplace,
+ Loops, SE, DT) &&
+ "SCEV normalization is not invertible!");
+#endif
+ break;
+ case Normalize:
+ if (Loops.count(L)) {
+ const SCEV *TransformedStep =
+ TransformForPostIncUse(Kind, AR->getStepRecurrence(SE),
+ User, OperandValToReplace, Loops, SE, DT);
+ Result = SE.getMinusSCEV(Result, TransformedStep);
+ }
+#ifdef XDEBUG
+ assert(S == TransformForPostIncUse(Denormalize, Result,
+ User, OperandValToReplace,
+ Loops, SE, DT) &&
+ "SCEV normalization is not invertible!");
+#endif
+ break;
+ case Denormalize:
+ if (Loops.count(L))
+ Result = cast<SCEVAddRecExpr>(Result)->getPostIncExpr(SE);
+ break;
+ }
+ return Result;
+ }
+
if (const SCEVNAryExpr *X = dyn_cast<SCEVNAryExpr>(S)) {
SmallVector<const SCEV *, 8> Operands;
bool Changed = false;
+ // Transform each operand.
for (SCEVNAryExpr::op_iterator I = X->op_begin(), E = X->op_end();
I != E; ++I) {
const SCEV *O = *I;
@@ -96,37 +149,7 @@
Changed |= N != O;
Operands.push_back(N);
}
- if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S)) {
- // An addrec. This is the interesting part.
- const Loop *L = AR->getLoop();
- const SCEV *Result = SE.getAddRecExpr(Operands, L);
- switch (Kind) {
- default: llvm_unreachable("Unexpected transform name!");
- case NormalizeAutodetect:
- if (Instruction *OI = dyn_cast<Instruction>(OperandValToReplace))
- if (IVUseShouldUsePostIncValue(User, OI, L, &DT)) {
- const SCEV *TransformedStep =
- TransformForPostIncUse(Kind, AR->getStepRecurrence(SE),
- User, OperandValToReplace, Loops, SE, DT);
- Result = SE.getMinusSCEV(Result, TransformedStep);
- Loops.insert(L);
- }
- break;
- case Normalize:
- if (Loops.count(L)) {
- const SCEV *TransformedStep =
- TransformForPostIncUse(Kind, AR->getStepRecurrence(SE),
- User, OperandValToReplace, Loops, SE, DT);
- Result = SE.getMinusSCEV(Result, TransformedStep);
- }
- break;
- case Denormalize:
- if (Loops.count(L))
- Result = SE.getAddExpr(Result, AR->getStepRecurrence(SE));
- break;
- }
- return Result;
- }
+ // If any operand actually changed, return a transformed result.
if (Changed)
switch (S->getSCEVType()) {
case scAddExpr: return SE.getAddExpr(Operands);
@@ -137,6 +160,7 @@
}
return S;
}
+
if (const SCEVUDivExpr *X = dyn_cast<SCEVUDivExpr>(S)) {
const SCEV *LO = X->getLHS();
const SCEV *RO = X->getRHS();
@@ -148,6 +172,7 @@
return SE.getUDivExpr(LN, RN);
return S;
}
+
llvm_unreachable("Unexpected SCEV kind!");
return 0;
}
Modified: llvm/branches/wendling/eh/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/AsmParser/LLParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/AsmParser/LLParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/AsmParser/LLParser.cpp Sat Jul 31 19:59:02 2010
@@ -543,27 +543,20 @@
ParseToken(lltok::lbrace, "Expected '{' here"))
return true;
- SmallVector<MDNode *, 8> Elts;
+ NamedMDNode *NMD = M->getOrInsertNamedMetadata(Name);
if (Lex.getKind() != lltok::rbrace)
do {
- // Null is a special case since it is typeless.
- if (EatIfPresent(lltok::kw_null)) {
- Elts.push_back(0);
- continue;
- }
-
if (ParseToken(lltok::exclaim, "Expected '!' here"))
return true;
MDNode *N = 0;
if (ParseMDNodeID(N)) return true;
- Elts.push_back(N);
+ NMD->addOperand(N);
} while (EatIfPresent(lltok::comma));
if (ParseToken(lltok::rbrace, "expected end of metadata node"))
return true;
- NamedMDNode::Create(Context, Name, Elts.data(), Elts.size(), M);
return false;
}
@@ -1161,6 +1154,8 @@
if (ParseUInt32(Alignment)) return true;
if (!isPowerOf2_32(Alignment))
return Error(AlignLoc, "alignment is not a power of two");
+ if (Alignment > Value::MaximumAlignment)
+ return Error(AlignLoc, "huge alignments are not supported yet");
return false;
}
@@ -1183,6 +1178,7 @@
if (Lex.getKind() != lltok::kw_align)
return Error(Lex.getLoc(), "expected metadata or 'align'");
+ LocTy AlignLoc = Lex.getLoc();
if (ParseOptionalAlignment(Alignment)) return true;
}
Modified: llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.cpp Sat Jul 31 19:59:02 2010
@@ -39,6 +39,7 @@
std::vector<BasicBlock*>().swap(FunctionBBs);
std::vector<Function*>().swap(FunctionsWithBodies);
DeferredFunctionInfo.clear();
+ MDKindMap.clear();
}
//===----------------------------------------------------------------------===//
@@ -800,20 +801,13 @@
// Read named metadata elements.
unsigned Size = Record.size();
- SmallVector<MDNode *, 8> Elts;
+ NamedMDNode *NMD = TheModule->getOrInsertNamedMetadata(Name);
for (unsigned i = 0; i != Size; ++i) {
- if (Record[i] == ~0U) {
- Elts.push_back(NULL);
- continue;
- }
MDNode *MD = dyn_cast<MDNode>(MDValueList.getValueFwdRef(Record[i]));
if (MD == 0)
return Error("Malformed metadata record");
- Elts.push_back(MD);
+ NMD->addOperand(MD);
}
- Value *V = NamedMDNode::Create(Context, Name.str(), Elts.data(),
- Elts.size(), TheModule);
- MDValueList.AssignValue(V, NextMDValueNo++);
break;
}
case bitc::METADATA_FN_NODE:
@@ -859,13 +853,12 @@
SmallString<8> Name;
Name.resize(RecordLength-1);
unsigned Kind = Record[0];
- (void) Kind;
for (unsigned i = 1; i != RecordLength; ++i)
Name[i-1] = Record[i];
unsigned NewKind = TheModule->getMDKindID(Name.str());
- assert(Kind == NewKind &&
- "FIXME: Unable to handle custom metadata mismatch!");(void)NewKind;
+ if (!MDKindMap.insert(std::make_pair(Kind, NewKind)).second)
+ return Error("Conflicting METADATA_KIND records");
break;
}
}
@@ -1621,8 +1614,12 @@
Instruction *Inst = InstructionList[Record[0]];
for (unsigned i = 1; i != RecordLength; i = i+2) {
unsigned Kind = Record[i];
+ DenseMap<unsigned, unsigned>::iterator I =
+ MDKindMap.find(Kind);
+ if (I == MDKindMap.end())
+ return Error("Invalid metadata kind ID");
Value *Node = MDValueList.getValueFwdRef(Record[i+1]);
- Inst->setMetadata(Kind, cast<MDNode>(Node));
+ Inst->setMetadata(I->second, cast<MDNode>(Node));
}
break;
}
Modified: llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.h (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Reader/BitcodeReader.h Sat Jul 31 19:59:02 2010
@@ -156,6 +156,9 @@
// stored here with their replacement function.
typedef std::vector<std::pair<Function*, Function*> > UpgradedIntrinsicMap;
UpgradedIntrinsicMap UpgradedIntrinsics;
+
+ // Map the bitcode's custom MDKind ID to the Module's MDKind ID.
+ DenseMap<unsigned, unsigned> MDKindMap;
// After the module header has been read, the FunctionsWithBodies list is
// reversed. This keeps track of whether we've done this yet.
Modified: llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Writer/BitcodeWriter.cpp Sat Jul 31 19:59:02 2010
@@ -509,7 +509,8 @@
Record.clear();
}
-static void WriteModuleMetadata(const ValueEnumerator &VE,
+static void WriteModuleMetadata(const Module *M,
+ const ValueEnumerator &VE,
BitstreamWriter &Stream) {
const ValueEnumerator::ValueList &Vals = VE.getMDValues();
bool StartedMetadataBlock = false;
@@ -544,29 +545,30 @@
// Emit the finished record.
Stream.EmitRecord(bitc::METADATA_STRING, Record, MDSAbbrev);
Record.clear();
- } else if (const NamedMDNode *NMD = dyn_cast<NamedMDNode>(Vals[i].first)) {
- if (!StartedMetadataBlock) {
- Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
- StartedMetadataBlock = true;
- }
-
- // Write name.
- StringRef Str = NMD->getName();
- for (unsigned i = 0, e = Str.size(); i != e; ++i)
- Record.push_back(Str[i]);
- Stream.EmitRecord(bitc::METADATA_NAME, Record, 0/*TODO*/);
- Record.clear();
+ }
+ }
- // Write named metadata operands.
- for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
- if (NMD->getOperand(i))
- Record.push_back(VE.getValueID(NMD->getOperand(i)));
- else
- Record.push_back(~0U);
- }
- Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0);
- Record.clear();
+ // Write named metadata.
+ for (Module::const_named_metadata_iterator I = M->named_metadata_begin(),
+ E = M->named_metadata_end(); I != E; ++I) {
+ const NamedMDNode *NMD = I;
+ if (!StartedMetadataBlock) {
+ Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
+ StartedMetadataBlock = true;
}
+
+ // Write name.
+ StringRef Str = NMD->getName();
+ for (unsigned i = 0, e = Str.size(); i != e; ++i)
+ Record.push_back(Str[i]);
+ Stream.EmitRecord(bitc::METADATA_NAME, Record, 0/*TODO*/);
+ Record.clear();
+
+ // Write named metadata operands.
+ for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
+ Record.push_back(VE.getValueID(NMD->getOperand(i)));
+ Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0);
+ Record.clear();
}
if (StartedMetadataBlock)
@@ -634,12 +636,11 @@
SmallVector<StringRef, 4> Names;
M->getMDKindNames(Names);
- assert(Names[0] == "" && "MDKind #0 is invalid");
- if (Names.size() == 1) return;
+ if (Names.empty()) return;
Stream.EnterSubblock(bitc::METADATA_BLOCK_ID, 3);
- for (unsigned MDKindID = 1, e = Names.size(); MDKindID != e; ++MDKindID) {
+ for (unsigned MDKindID = 0, e = Names.size(); MDKindID != e; ++MDKindID) {
Record.push_back(MDKindID);
StringRef KName = Names[MDKindID];
Record.append(KName.begin(), KName.end());
@@ -902,6 +903,9 @@
Record.push_back(VE.getValueID(BA->getFunction()));
Record.push_back(VE.getGlobalBasicBlockID(BA->getBasicBlock()));
} else {
+#ifndef NDEBUG
+ C->dump();
+#endif
llvm_unreachable("Unknown constant!");
}
Stream.EmitRecord(Code, Record, AbbrevToUse);
@@ -1549,7 +1553,7 @@
WriteModuleConstants(VE, Stream);
// Emit metadata.
- WriteModuleMetadata(VE, Stream);
+ WriteModuleMetadata(M, VE, Stream);
// Emit function bodies.
for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I)
Modified: llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.cpp Sat Jul 31 19:59:02 2010
@@ -75,7 +75,7 @@
// Insert constants and metadata that are named at module level into the slot
// pool so that the module symbol table can refer to them...
EnumerateValueSymbolTable(M->getValueSymbolTable());
- EnumerateMDSymbolTable(M->getMDSymbolTable());
+ EnumerateNamedMetadata(M);
SmallVector<std::pair<unsigned, MDNode*>, 8> MDs;
@@ -207,31 +207,18 @@
EnumerateValue(VI->getValue());
}
-/// EnumerateMDSymbolTable - Insert all of the values in the specified metadata
-/// table.
-void ValueEnumerator::EnumerateMDSymbolTable(const MDSymbolTable &MST) {
- for (MDSymbolTable::const_iterator MI = MST.begin(), ME = MST.end();
- MI != ME; ++MI)
- EnumerateValue(MI->getValue());
+/// EnumerateNamedMetadata - Insert all of the values referenced by
+/// named metadata in the specified module.
+void ValueEnumerator::EnumerateNamedMetadata(const Module *M) {
+ for (Module::const_named_metadata_iterator I = M->named_metadata_begin(),
+ E = M->named_metadata_end(); I != E; ++I)
+ EnumerateNamedMDNode(I);
}
void ValueEnumerator::EnumerateNamedMDNode(const NamedMDNode *MD) {
- // Check to see if it's already in!
- unsigned &MDValueID = MDValueMap[MD];
- if (MDValueID) {
- // Increment use count.
- MDValues[MDValueID-1].second++;
- return;
- }
-
- // Enumerate the type of this value.
- EnumerateType(MD->getType());
-
for (unsigned i = 0, e = MD->getNumOperands(); i != e; ++i)
if (MDNode *E = MD->getOperand(i))
EnumerateValue(E);
- MDValues.push_back(std::make_pair(MD, 1U));
- MDValueMap[MD] = Values.size();
}
void ValueEnumerator::EnumerateMetadata(const Value *MD) {
@@ -272,8 +259,6 @@
assert(!V->getType()->isVoidTy() && "Can't insert void values!");
if (isa<MDNode>(V) || isa<MDString>(V))
return EnumerateMetadata(V);
- else if (const NamedMDNode *NMD = dyn_cast<NamedMDNode>(V))
- return EnumerateNamedMDNode(NMD);
// Check to see if it's already in!
unsigned &ValueID = ValueMap[V];
@@ -388,8 +373,8 @@
NumModuleValues = Values.size();
// Adding function arguments to the value table.
- for(Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
- I != E; ++I)
+ for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
+ I != E; ++I)
EnumerateValue(I);
FirstFuncConstantID = Values.size();
Modified: llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.h (original)
+++ llvm/branches/wendling/eh/lib/Bitcode/Writer/ValueEnumerator.h Sat Jul 31 19:59:02 2010
@@ -141,7 +141,7 @@
void EnumerateTypeSymbolTable(const TypeSymbolTable &ST);
void EnumerateValueSymbolTable(const ValueSymbolTable &ST);
- void EnumerateMDSymbolTable(const MDSymbolTable &ST);
+ void EnumerateNamedMetadata(const Module *M);
};
} // End llvm namespace
Modified: llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.cpp Sat Jul 31 19:59:02 2010
@@ -41,8 +41,11 @@
AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
MachineBasicBlock *BB) :
- NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) {
-
+ NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
+ GroupNodeIndices(TargetRegs, 0),
+ KillIndices(TargetRegs, 0),
+ DefIndices(TargetRegs, 0)
+{
const unsigned BBSize = BB->size();
for (unsigned i = 0; i < NumTargetRegs; ++i) {
// Initialize all registers to be in their own group. Initially we
@@ -54,8 +57,7 @@
}
}
-unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
-{
+unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
unsigned Node = GroupNodeIndices[Reg];
while (GroupNodes[Node] != Node)
Node = GroupNodes[Node];
@@ -145,8 +147,8 @@
State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
- unsigned *KillIndices = State->GetKillIndices();
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &KillIndices = State->GetKillIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
// Determine the live-out physregs for this block.
if (IsReturnBlock) {
@@ -226,7 +228,7 @@
DEBUG(MI->dump());
DEBUG(dbgs() << "\tRegs:");
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
// If Reg is current live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it
@@ -328,8 +330,8 @@
const char *tag,
const char *header,
const char *footer) {
- unsigned *KillIndices = State->GetKillIndices();
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &KillIndices = State->GetKillIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
@@ -364,7 +366,7 @@
void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
unsigned Count,
std::set<unsigned>& PassthruRegs) {
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
@@ -560,8 +562,8 @@
unsigned AntiDepGroupIndex,
RenameOrderType& RenameOrder,
std::map<unsigned, unsigned> &RenameMap) {
- unsigned *KillIndices = State->GetKillIndices();
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &KillIndices = State->GetKillIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
@@ -733,8 +735,8 @@
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex) {
- unsigned *KillIndices = State->GetKillIndices();
- unsigned *DefIndices = State->GetDefIndices();
+ std::vector<unsigned> &KillIndices = State->GetKillIndices();
+ std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
Modified: llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AggressiveAntiDepBreaker.h Sat Jul 31 19:59:02 2010
@@ -59,27 +59,27 @@
/// currently representing the group that the register belongs to.
/// Register 0 is always represented by the 0 group, a group
/// composed of registers that are not eligible for anti-aliasing.
- unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> GroupNodeIndices;
/// RegRefs - Map registers to all their references within a live range.
std::multimap<unsigned, RegisterReference> RegRefs;
/// KillIndices - The index of the most recent kill (proceding bottom-up),
/// or ~0u if the register is not live.
- unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> KillIndices;
/// DefIndices - The index of the most recent complete def (proceding bottom
/// up), or ~0u if the register is live.
- unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> DefIndices;
public:
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
/// GetKillIndices - Return the kill indices.
- unsigned *GetKillIndices() { return KillIndices; }
+ std::vector<unsigned> &GetKillIndices() { return KillIndices; }
/// GetDefIndices - Return the define indices.
- unsigned *GetDefIndices() { return DefIndices; }
+ std::vector<unsigned> &GetDefIndices() { return DefIndices; }
/// GetRegRefs - Return the RegRefs map.
std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
Modified: llvm/branches/wendling/eh/lib/CodeGen/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/Analysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/Analysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/Analysis.cpp Sat Jul 31 19:59:02 2010
@@ -109,7 +109,7 @@
V = V->stripPointerCasts();
GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
- if (GV && GV->getName() == ".llvm.eh.catch.all.value") {
+ if (GV && GV->getName() == "llvm.eh.catch.all.value") {
assert(GV->hasInitializer() &&
"The EH catch-all value must have an initializer");
Value *Init = GV->getInitializer();
@@ -171,7 +171,7 @@
FOC = FPC = ISD::SETFALSE;
break;
}
- if (FiniteOnlyFPMath())
+ if (NoNaNsFPMath)
return FOC;
else
return FPC;
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -510,12 +510,8 @@
}
// Check for spill-induced copies
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (TM.getInstrInfo()->isMoveInstr(MI, SrcReg, DstReg,
- SrcSubIdx, DstSubIdx)) {
- if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
- CommentOS << " Reload Reuse\n";
- }
+ if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
+ CommentOS << " Reload Reuse\n";
}
/// EmitImplicitDef - This method emits the specified machine instruction
@@ -603,12 +599,15 @@
// Print out code for the function.
bool HasAnyRealCode = false;
+ const MachineInstr *LastMI = 0;
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
// Print a label for the basic block.
EmitBasicBlockStart(I);
for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
II != IE; ++II) {
+ LastMI = II;
+
// Print the assembly for the instruction.
if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() &&
!II->isDebugValue()) {
@@ -625,7 +624,7 @@
EmitComments(*II, OutStreamer.GetCommentOS());
switch (II->getOpcode()) {
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::GC_LABEL:
OutStreamer.EmitLabel(II->getOperand(0).getMCSymbol());
@@ -656,11 +655,18 @@
}
}
}
-
+
+ // If the last instruction was a prolog label, then we have a situation where
+ // we emitted a prolog but no function body. This results in the ending prolog
+ // label equaling the end of function label and an invalid "row" in the
+ // FDE. We need to emit a noop in this situation so that the FDE's rows are
+ // valid.
+ bool RequiresNoop = LastMI && LastMI->isPrologLabel();
+
// If the function is empty and the object file uses .subsections_via_symbols,
// then we need to emit *something* to the function body to prevent the
// labels from collapsing together. Just emit a noop.
- if (MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) {
+ if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) || RequiresNoop) {
MCInst Noop;
TM.getInstrInfo()->getNoopForMachoTarget(Noop);
if (Noop.getOpcode()) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sat Jul 31 19:59:02 2010
@@ -22,7 +22,6 @@
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCParser/AsmParser.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegistry.h"
@@ -72,16 +71,18 @@
// Tell SrcMgr about this buffer, it takes ownership of the buffer.
SrcMgr.AddNewSourceBuffer(Buffer, SMLoc());
- AsmParser Parser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI);
- OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(Parser));
+ OwningPtr<MCAsmParser> Parser(createMCAsmParser(TM.getTarget(), SrcMgr,
+ OutContext, OutStreamer,
+ *MAI));
+ OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*Parser, TM));
if (!TAP)
report_fatal_error("Inline asm not supported by this streamer because"
" we don't have an asm parser for this target\n");
- Parser.setTargetParser(*TAP.get());
+ Parser->setTargetParser(*TAP.get());
// Don't implicitly switch to the text section before the asm.
- int Res = Parser.Run(/*NoInitialTextSection*/ true,
- /*NoFinalize*/ true);
+ int Res = Parser->Run(/*NoInitialTextSection*/ true,
+ /*NoFinalize*/ true);
if (Res && !HasDiagHandler)
report_fatal_error("Error parsing inline asm\n");
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sat Jul 31 19:59:02 2010
@@ -44,7 +44,7 @@
static cl::opt<bool> PrintDbgScope("print-dbgscope", cl::Hidden,
cl::desc("Print DbgScope information for each machine instruction"));
-static cl::opt<bool> DisableDebugInfoPrinting("disable-debug-info-print",
+static cl::opt<bool> DisableDebugInfoPrinting("disable-debug-info-print",
cl::Hidden,
cl::desc("Disable debug info printing"));
@@ -116,8 +116,8 @@
/// addGlobalType - Add a new global type to the compile unit.
///
- void addGlobalType(StringRef Name, DIE *Die) {
- GlobalTypes[Name] = Die;
+ void addGlobalType(StringRef Name, DIE *Die) {
+ GlobalTypes[Name] = Die;
}
/// getDIE - Returns the debug information entry map slot for the
@@ -131,8 +131,9 @@
/// getDIEEntry - Returns the debug information entry for the speciefied
/// debug variable.
- DIEEntry *getDIEEntry(const MDNode *N) {
- DenseMap<const MDNode *, DIEEntry *>::iterator I = MDNodeToDIEEntryMap.find(N);
+ DIEEntry *getDIEEntry(const MDNode *N) {
+ DenseMap<const MDNode *, DIEEntry *>::iterator I =
+ MDNodeToDIEEntryMap.find(N);
if (I == MDNodeToDIEEntryMap.end())
return NULL;
return I->second;
@@ -194,7 +195,7 @@
DbgScope *Parent; // Parent to this scope.
DIDescriptor Desc; // Debug info descriptor for scope.
// Location at which this scope is inlined.
- AssertingVH<const MDNode> InlinedAtLocation;
+ AssertingVH<const MDNode> InlinedAtLocation;
bool AbstractScope; // Abstract Scope
const MachineInstr *LastInsn; // Last instruction of this scope.
const MachineInstr *FirstInsn; // First instruction of this scope.
@@ -225,14 +226,14 @@
/// openInsnRange - This scope covers instruction range starting from MI.
void openInsnRange(const MachineInstr *MI) {
- if (!FirstInsn)
+ if (!FirstInsn)
FirstInsn = MI;
-
+
if (Parent)
Parent->openInsnRange(MI);
}
- /// extendInsnRange - Extend the current instruction range covered by
+ /// extendInsnRange - Extend the current instruction range covered by
/// this scope.
void extendInsnRange(const MachineInstr *MI) {
assert (FirstInsn && "MI Range is not open!");
@@ -247,9 +248,9 @@
void closeInsnRange(DbgScope *NewScope = NULL) {
assert (LastInsn && "Last insn missing!");
Ranges.push_back(DbgRange(FirstInsn, LastInsn));
- FirstInsn = NULL;
+ FirstInsn = NULL;
LastInsn = NULL;
- // If Parent dominates NewScope then do not close Parent's instruction
+ // If Parent dominates NewScope then do not close Parent's instruction
// range.
if (Parent && (!NewScope || !Parent->dominates(NewScope)))
Parent->closeInsnRange(NewScope);
@@ -264,7 +265,7 @@
unsigned getDFSIn() const { return DFSIn; }
void setDFSIn(unsigned I) { DFSIn = I; }
bool dominates(const DbgScope *S) {
- if (S == this)
+ if (S == this)
return true;
if (DFSIn < S->getDFSIn() && DFSOut > S->getDFSOut())
return true;
@@ -313,13 +314,13 @@
DwarfDebug::DwarfDebug(AsmPrinter *A, Module *M)
: Asm(A), MMI(Asm->MMI), FirstCU(0),
- AbbreviationsSet(InitAbbreviationsSetSize),
+ AbbreviationsSet(InitAbbreviationsSetSize),
CurrentFnDbgScope(0), PrevLabel(NULL) {
NextStringPoolNumber = 0;
-
+
DwarfFrameSectionSym = DwarfInfoSectionSym = DwarfAbbrevSectionSym = 0;
DwarfStrSectionSym = TextSectionSym = 0;
- DwarfDebugRangeSectionSym = DwarfDebugLocSectionSym = 0;
+ DwarfDebugRangeSectionSym = DwarfDebugLocSectionSym = 0;
DwarfDebugLineSectionSym = CurrentLineSectionSym = 0;
FunctionBeginSym = FunctionEndSym = 0;
DIEIntegerOne = new (DIEValueAllocator) DIEInteger(1);
@@ -377,7 +378,7 @@
void DwarfDebug::addUInt(DIE *Die, unsigned Attribute,
unsigned Form, uint64_t Integer) {
if (!Form) Form = DIEInteger::BestForm(false, Integer);
- DIEValue *Value = Integer == 1 ?
+ DIEValue *Value = Integer == 1 ?
DIEIntegerOne : new (DIEValueAllocator) DIEInteger(Integer);
Die->addValue(Attribute, Form, Value);
}
@@ -392,7 +393,7 @@
}
/// addString - Add a string attribute data and value. DIEString only
-/// keeps string reference.
+/// keeps string reference.
void DwarfDebug::addString(DIE *Die, unsigned Attribute, unsigned Form,
StringRef String) {
DIEValue *Value = new (DIEValueAllocator) DIEString(String);
@@ -835,26 +836,26 @@
assert (MO.isFPImm() && "Invalid machine operand!");
DIEBlock *Block = new (DIEValueAllocator) DIEBlock();
APFloat FPImm = MO.getFPImm()->getValueAPF();
-
+
// Get the raw data form of the floating point.
const APInt FltVal = FPImm.bitcastToAPInt();
const char *FltPtr = (const char*)FltVal.getRawData();
-
+
int NumBytes = FltVal.getBitWidth() / 8; // 8 bits per byte.
bool LittleEndian = Asm->getTargetData().isLittleEndian();
int Incr = (LittleEndian ? 1 : -1);
int Start = (LittleEndian ? 0 : NumBytes - 1);
int Stop = (LittleEndian ? NumBytes : -1);
-
+
// Output the constant to DWARF one byte at a time.
for (; Start != Stop; Start += Incr)
addUInt(Block, 0, dwarf::DW_FORM_data1,
(unsigned char)0xFF & FltPtr[Start]);
-
+
addBlock(Die, dwarf::DW_AT_const_value, 0, Block);
if (VS)
addLabel(Die, dwarf::DW_AT_start_scope, dwarf::DW_FORM_addr, VS);
- return true;
+ return true;
}
@@ -872,7 +873,7 @@
ContextDIE->addChild(Die);
} else if (DIE *ContextDIE = getCompileUnit(Context)->getDIE(Context))
ContextDIE->addChild(Die);
- else
+ else
getCompileUnit(Context)->addDie(Die);
}
@@ -1057,7 +1058,7 @@
DICompositeType ContainingType = CTy.getContainingType();
if (DIDescriptor(ContainingType).isCompositeType())
- addDIEEntry(&Buffer, dwarf::DW_AT_containing_type, dwarf::DW_FORM_ref4,
+ addDIEEntry(&Buffer, dwarf::DW_AT_containing_type, dwarf::DW_FORM_ref4,
getOrCreateTypeDIE(DIType(ContainingType)));
else {
DIDescriptor Context = CTy.getContext();
@@ -1073,7 +1074,7 @@
if (!Name.empty())
addString(&Buffer, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
- if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
+ if (Tag == dwarf::DW_TAG_enumeration_type || Tag == dwarf::DW_TAG_class_type
|| Tag == dwarf::DW_TAG_structure_type || Tag == dwarf::DW_TAG_union_type)
{
// Add size if non-zero (derived types might be zero-sized.)
@@ -1149,7 +1150,7 @@
return Enumerator;
}
-/// getRealLinkageName - If special LLVM prefix that is used to inform the asm
+/// getRealLinkageName - If special LLVM prefix that is used to inform the asm
/// printer to not emit usual symbol prefix before the symbol name is used then
/// return linkage name after skipping this special LLVM prefix.
static StringRef getRealLinkageName(StringRef LinkageName) {
@@ -1189,7 +1190,7 @@
StringRef Name = DT.getName();
if (!Name.empty())
addString(MemberDie, dwarf::DW_AT_name, dwarf::DW_FORM_string, Name);
-
+
addType(MemberDie, DT.getTypeDerivedFrom());
addSourceLine(MemberDie, &DT);
@@ -1240,7 +1241,7 @@
addUInt(VBaseLocationDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_deref);
addUInt(VBaseLocationDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_plus);
- addBlock(MemberDie, dwarf::DW_AT_data_member_location, 0,
+ addBlock(MemberDie, dwarf::DW_AT_data_member_location, 0,
VBaseLocationDie);
} else
addBlock(MemberDie, dwarf::DW_AT_data_member_location, 0, MemLocationDie);
@@ -1302,7 +1303,7 @@
addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_constu);
addUInt(Block, 0, dwarf::DW_FORM_data1, SP.getVirtualIndex());
addBlock(SPDie, dwarf::DW_AT_vtable_elem_location, 0, Block);
- ContainingTypeMap.insert(std::make_pair(SPDie,
+ ContainingTypeMap.insert(std::make_pair(SPDie,
SP.getContainingType()));
}
@@ -1331,10 +1332,14 @@
if (!SP.isLocalToUnit())
addUInt(SPDie, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1);
-
+
if (SP.isOptimized())
addUInt(SPDie, dwarf::DW_AT_APPLE_optimized, dwarf::DW_FORM_flag, 1);
+ if (unsigned isa = Asm->getISAEncoding()) {
+ addUInt(SPDie, dwarf::DW_AT_APPLE_isa, dwarf::DW_FORM_flag, isa);
+ }
+
// DW_TAG_inlined_subroutine may refer to this DIE.
SPCU->insertDIE(SP, SPDie);
@@ -1394,18 +1399,18 @@
assert(SPDie && "Unable to find subprogram DIE!");
DISubprogram SP(SPNode);
-
+
// There is not any need to generate specification DIE for a function
// defined at compile unit level. If a function is defined inside another
// function then gdb prefers the definition at top level and but does not
- // expect specification DIE in parent function. So avoid creating
+ // expect specification DIE in parent function. So avoid creating
// specification DIE for a function defined inside a function.
if (SP.isDefinition() && !SP.getContext().isCompileUnit() &&
- !SP.getContext().isFile() &&
+ !SP.getContext().isFile() &&
!isSubprogramContext(SP.getContext())) {
addUInt(SPDie, dwarf::DW_AT_declaration, dwarf::DW_FORM_flag, 1);
-
- // Add arguments.
+
+ // Add arguments.
DICompositeType SPTy = SP.getType();
DIArray Args = SPTy.getTypeArray();
unsigned SPTag = SPTy.getTag();
@@ -1420,11 +1425,11 @@
}
DIE *SPDeclDie = SPDie;
SPDie = new DIE(dwarf::DW_TAG_subprogram);
- addDIEEntry(SPDie, dwarf::DW_AT_specification, dwarf::DW_FORM_ref4,
+ addDIEEntry(SPDie, dwarf::DW_AT_specification, dwarf::DW_FORM_ref4,
SPDeclDie);
SPCU->addDie(SPDie);
}
-
+
// Pick up abstract subprogram DIE.
if (DIE *AbsSPDIE = AbstractSPDies.lookup(SPNode)) {
SPDie = new DIE(dwarf::DW_TAG_subprogram);
@@ -1459,7 +1464,7 @@
SmallVector<DbgRange, 4>::const_iterator RI = Ranges.begin();
if (Ranges.size() > 1) {
// .debug_range section has not been laid out yet. Emit offset in
- // .debug_range as a uint, size 4, for now. emitDIE will handle
+ // .debug_range as a uint, size 4, for now. emitDIE will handle
// DW_AT_ranges appropriately.
addUInt(ScopeDIE, dwarf::DW_AT_ranges, dwarf::DW_FORM_data4,
DebugRangeSymbols.size() * Asm->getTargetData().getPointerSize());
@@ -1480,7 +1485,7 @@
assert(Start->isDefined() && "Invalid starting label for an inlined scope!");
assert(End->isDefined() && "Invalid end label for an inlined scope!");
-
+
addLabel(ScopeDIE, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr, Start);
addLabel(ScopeDIE, dwarf::DW_AT_high_pc, dwarf::DW_FORM_addr, End);
@@ -1493,7 +1498,7 @@
DIE *DwarfDebug::constructInlinedScopeDIE(DbgScope *Scope) {
const SmallVector<DbgRange, 4> &Ranges = Scope->getRanges();
- assert (Ranges.empty() == false
+ assert (Ranges.empty() == false
&& "DbgScope does not have instruction markers!");
// FIXME : .debug_inlined section specification does not clearly state how
@@ -1623,15 +1628,15 @@
const MachineInstr *DVInsn = DVI->second;
const MCSymbol *DVLabel = findVariableLabel(DV);
bool updated = false;
- // FIXME : Handle getNumOperands != 3
+ // FIXME : Handle getNumOperands != 3
if (DVInsn->getNumOperands() == 3) {
if (DVInsn->getOperand(0).isReg())
- updated =
+ updated =
addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0));
else if (DVInsn->getOperand(0).isImm())
updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0));
- else if (DVInsn->getOperand(0).isFPImm())
- updated =
+ else if (DVInsn->getOperand(0).isFPImm())
+ updated =
addConstantFPValue(VariableDie, DVLabel, DVInsn->getOperand(0));
} else {
MachineLocation Location = Asm->getDebugValueLocation(DVInsn);
@@ -1651,7 +1656,7 @@
}
DV->setDIE(VariableDie);
return VariableDie;
- }
+ }
// .. else use frame index, if available.
MachineLocation Location;
@@ -1661,7 +1666,7 @@
if (findVariableFrameIndex(DV, &FI)) {
int Offset = RI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
Location.set(FrameReg, Offset);
-
+
if (VD.hasComplexAddress())
addComplexAddress(DV, VariableDie, dwarf::DW_AT_location, Location);
else if (VD.isBlockByrefVariable())
@@ -1677,7 +1682,7 @@
void DwarfDebug::addPubTypes(DISubprogram SP) {
DICompositeType SPTy = SP.getType();
unsigned SPTag = SPTy.getTag();
- if (SPTag != dwarf::DW_TAG_subroutine_type)
+ if (SPTag != dwarf::DW_TAG_subroutine_type)
return;
DIArray Args = SPTy.getTypeArray();
@@ -1699,7 +1704,7 @@
DIE *DwarfDebug::constructScopeDIE(DbgScope *Scope) {
if (!Scope || !Scope->getScopeNode())
return NULL;
-
+
DIScope DS(Scope->getScopeNode());
DIE *ScopeDIE = NULL;
if (Scope->getInlinedAt())
@@ -1718,7 +1723,7 @@
else
ScopeDIE = constructLexicalScopeDIE(Scope);
if (!ScopeDIE) return NULL;
-
+
// Add variables to scope.
const SmallVector<DbgVariable *, 8> &Variables = Scope->getVariables();
for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
@@ -1736,9 +1741,9 @@
ScopeDIE->addChild(NestedDIE);
}
- if (DS.isSubprogram())
+ if (DS.isSubprogram())
addPubTypes(DISubprogram(DS));
-
+
return ScopeDIE;
}
@@ -1748,6 +1753,8 @@
/// maps as well.
unsigned DwarfDebug::GetOrCreateSourceID(StringRef DirName, StringRef FileName){
unsigned DId;
+ assert (DirName.empty() == false && "Invalid directory name!");
+
StringMap<unsigned>::iterator DI = DirectoryIdMap.find(DirName);
if (DI != DirectoryIdMap.end()) {
DId = DI->getValue();
@@ -1794,7 +1801,7 @@
return NDie;
}
-/// constructCompileUnit - Create new CompileUnit for the given
+/// constructCompileUnit - Create new CompileUnit for the given
/// metadata node with tag DW_TAG_compile_unit.
void DwarfDebug::constructCompileUnit(const MDNode *N) {
DICompileUnit DIUnit(N);
@@ -1812,7 +1819,7 @@
// simplifies debug range entries.
addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0);
// DW_AT_stmt_list is a offset of line number information for this
- // compile unit in debug_line section. This offset is calculated
+ // compile unit in debug_line section. This offset is calculated
// during endMoudle().
addLabel(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
@@ -1891,7 +1898,7 @@
// Do not create specification DIE if context is either compile unit
// or a subprogram.
if (DI_GV.isDefinition() && !GVContext.isCompileUnit() &&
- !GVContext.isFile() &&
+ !GVContext.isFile() &&
!isSubprogramContext(GVContext)) {
// Create specification DIE.
DIE *VariableSpecDIE = new DIE(dwarf::DW_TAG_variable);
@@ -1912,7 +1919,7 @@
addBlock(VariableDie, dwarf::DW_AT_location, 0, Block);
}
addToContextOwner(VariableDie, GVContext);
-
+
// Expose as global. FIXME - need to check external flag.
TheCU->addGlobal(DI_GV.getName(), VariableDie);
@@ -1965,7 +1972,7 @@
DbgFinder.processModule(*M);
bool HasDebugInfo = false;
-
+
// Scan all the compile-units to see if there are any marked as the main unit.
// if not, we do not generate debug info.
for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
@@ -1975,15 +1982,15 @@
break;
}
}
-
+
if (!HasDebugInfo) return;
// Tell MMI that we have debug info.
MMI->setDebugInfoAvailability(true);
-
+
// Emit initial sections.
EmitSectionLabels();
-
+
// Create all the compile unit DIEs.
for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
E = DbgFinder.compile_unit_end(); I != E; ++I)
@@ -2032,10 +2039,11 @@
if (!SP.Verify()) continue;
// Collect info for variables that were optimized out.
+ if (!SP.isDefinition()) continue;
StringRef FName = SP.getLinkageName();
if (FName.empty())
FName = SP.getName();
- NamedMDNode *NMD =
+ NamedMDNode *NMD =
M->getNamedMetadata(Twine("llvm.dbg.lv.", getRealLinkageName(FName)));
if (!NMD) continue;
unsigned E = NMD->getNumOperands();
@@ -2046,7 +2054,7 @@
if (!DV.Verify()) continue;
Scope->addVariable(new DbgVariable(DV));
}
-
+
// Construct subprogram DIE and add variables DIEs.
constructSubprogramDIE(SP);
DIE *ScopeDIE = getCompileUnit(SP)->getDIE(SP);
@@ -2131,7 +2139,7 @@
// Emit info into a debug str section.
emitDebugStr();
-
+
for (DenseMap<const MDNode *, CompileUnit *>::iterator I = CUMap.begin(),
E = CUMap.end(); I != E; ++I)
delete I->second;
@@ -2139,7 +2147,7 @@
}
/// findAbstractVariable - Find abstract variable, if any, associated with Var.
-DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &Var,
+DbgVariable *DwarfDebug::findAbstractVariable(DIVariable &Var,
DebugLoc ScopeLoc) {
DbgVariable *AbsDbgVariable = AbstractVariables.lookup(Var);
@@ -2159,7 +2167,7 @@
/// collectVariableInfoFromMMITable - Collect variable information from
/// side table maintained by MMI.
-void
+void
DwarfDebug::collectVariableInfoFromMMITable(const MachineFunction * MF,
SmallPtrSet<const MDNode *, 16> &Processed) {
const LLVMContext &Ctx = Asm->MF->getFunction()->getContext();
@@ -2177,7 +2185,7 @@
Scope = ConcreteScopes.lookup(IA);
if (Scope == 0)
Scope = DbgScopeMap.lookup(VP.second.getScope(Ctx));
-
+
// If variable scope is not found then skip this variable.
if (Scope == 0)
continue;
@@ -2193,7 +2201,7 @@
}
}
-/// isDbgValueInUndefinedReg - Return true if debug value, encoded by
+/// isDbgValueInUndefinedReg - Return true if debug value, encoded by
/// DBG_VALUE instruction, is in undefined reg.
static bool isDbgValueInUndefinedReg(const MachineInstr *MI) {
assert (MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
@@ -2202,7 +2210,7 @@
return false;
}
-/// isDbgValueInDefinedReg - Return true if debug value, encoded by
+/// isDbgValueInDefinedReg - Return true if debug value, encoded by
/// DBG_VALUE instruction, is in a defined reg.
static bool isDbgValueInDefinedReg(const MachineInstr *MI) {
assert (MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
@@ -2212,10 +2220,10 @@
}
/// collectVariableInfo - Populate DbgScope entries with variables' info.
-void
+void
DwarfDebug::collectVariableInfo(const MachineFunction *MF,
SmallPtrSet<const MDNode *, 16> &Processed) {
-
+
/// collection info from MMI table.
collectVariableInfoFromMMITable(MF, Processed);
@@ -2244,11 +2252,11 @@
continue;
const MachineInstr *PrevMI = MInsn;
- for (SmallVector<const MachineInstr *, 8>::iterator MI = I+1,
+ for (SmallVector<const MachineInstr *, 8>::iterator MI = I+1,
ME = DbgValues.end(); MI != ME; ++MI) {
- const MDNode *Var =
+ const MDNode *Var =
(*MI)->getOperand((*MI)->getNumOperands()-1).getMetadata();
- if (Var == DV && isDbgValueInDefinedReg(*MI) &&
+ if (Var == DV && isDbgValueInDefinedReg(*MI) &&
!PrevMI->isIdenticalTo(*MI))
MultipleValues.push_back(*MI);
PrevMI = *MI;
@@ -2269,7 +2277,7 @@
DbgVariable *RegVar = new DbgVariable(DV);
Scope->addVariable(RegVar);
if (!CurFnArg)
- DbgVariableLabelsMap[RegVar] = getLabelBeforeInsn(MInsn);
+ DbgVariableLabelsMap[RegVar] = getLabelBeforeInsn(MInsn);
if (DbgVariable *AbsVar = findAbstractVariable(DV, MInsn->getDebugLoc())) {
DbgVariableToDbgInstMap[AbsVar] = MInsn;
VarToAbstractVarMap[RegVar] = AbsVar;
@@ -2286,13 +2294,13 @@
RegVar->setDotDebugLocOffset(DotDebugLocEntries.size());
const MachineInstr *Begin = NULL;
const MachineInstr *End = NULL;
- for (SmallVector<const MachineInstr *, 4>::iterator
- MVI = MultipleValues.begin(), MVE = MultipleValues.end();
+ for (SmallVector<const MachineInstr *, 4>::iterator
+ MVI = MultipleValues.begin(), MVE = MultipleValues.end();
MVI != MVE; ++MVI) {
if (!Begin) {
Begin = *MVI;
continue;
- }
+ }
End = *MVI;
MachineLocation MLoc;
MLoc.set(Begin->getOperand(0).getReg(), 0);
@@ -2314,11 +2322,11 @@
// Collect info for variables that were optimized out.
const Function *F = MF->getFunction();
const Module *M = F->getParent();
- if (NamedMDNode *NMD =
- M->getNamedMetadata(Twine("llvm.dbg.lv.",
+ if (NamedMDNode *NMD =
+ M->getNamedMetadata(Twine("llvm.dbg.lv.",
getRealLinkageName(F->getName())))) {
for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
- DIVariable DV(cast_or_null<MDNode>(NMD->getOperand(i)));
+ DIVariable DV(cast<MDNode>(NMD->getOperand(i)));
if (!DV || !Processed.insert(DV))
continue;
DbgScope *Scope = DbgScopeMap.lookup(DV.getContext());
@@ -2364,7 +2372,7 @@
return;
}
- // If location is unknown then use temp label for this DBG_VALUE
+ // If location is unknown then use temp label for this DBG_VALUE
// instruction.
if (MI->isDebugValue()) {
PrevLabel = MMI->getContext().CreateTempSymbol();
@@ -2393,7 +2401,7 @@
}
/// getOrCreateDbgScope - Create DbgScope for the scope.
-DbgScope *DwarfDebug::getOrCreateDbgScope(const MDNode *Scope,
+DbgScope *DwarfDebug::getOrCreateDbgScope(const MDNode *Scope,
const MDNode *InlinedAt) {
if (!InlinedAt) {
DbgScope *WScope = DbgScopeMap.lookup(Scope);
@@ -2402,7 +2410,7 @@
WScope = new DbgScope(NULL, DIDescriptor(Scope), NULL);
DbgScopeMap.insert(std::make_pair(Scope, WScope));
if (DIDescriptor(Scope).isLexicalBlock()) {
- DbgScope *Parent =
+ DbgScope *Parent =
getOrCreateDbgScope(DILexicalBlock(Scope).getContext(), NULL);
WScope->setParent(Parent);
Parent->addScope(WScope);
@@ -2419,7 +2427,7 @@
DISubprogram(Scope).getFunction() == Asm->MF->getFunction())
CurrentFnDbgScope = WScope;
}
-
+
return WScope;
}
@@ -2448,14 +2456,14 @@
const MDNode *&Scope, const MDNode *&InlinedAt) {
DebugLoc DL = MInsn->getDebugLoc();
if (DL.isUnknown()) return false;
-
+
const MDNode *S = DL.getScope(Ctx);
-
+
// There is no need to create another DIE for compile unit. For all
// other scopes, create one DbgScope now. This will be translated
// into a scope DIE at the end.
if (DIScope(S).isCompileUnit()) return false;
-
+
Scope = S;
InlinedAt = DL.getInlinedAt(Ctx);
return true;
@@ -2490,7 +2498,7 @@
}
/// printDbgScopeInfo - Print DbgScope info for each machine instruction.
-static
+static
void printDbgScopeInfo(LLVMContext &Ctx, const MachineFunction *MF,
DenseMap<const MachineInstr *, DbgScope *> &MI2ScopeMap)
{
@@ -2507,9 +2515,9 @@
// Check if instruction has valid location information.
if (hasValidLocation(Ctx, MInsn, Scope, InlinedAt)) {
dbgs() << " [ ";
- if (InlinedAt)
+ if (InlinedAt)
dbgs() << "*";
- DenseMap<const MachineInstr *, DbgScope *>::iterator DI =
+ DenseMap<const MachineInstr *, DbgScope *>::iterator DI =
MI2ScopeMap.find(MInsn);
if (DI != MI2ScopeMap.end()) {
DbgScope *S = DI->second;
@@ -2517,7 +2525,7 @@
PrevDFSIn = S->getDFSIn();
} else
dbgs() << PrevDFSIn;
- } else
+ } else
dbgs() << " [ x" << PrevDFSIn;
dbgs() << " ]";
MInsn->dump();
@@ -2555,26 +2563,26 @@
PrevMI = MInsn;
continue;
}
-
+
// If scope has not changed then skip this instruction.
if (Scope == PrevScope && PrevInlinedAt == InlinedAt) {
PrevMI = MInsn;
continue;
}
- if (RangeBeginMI) {
- // If we have alread seen a beginning of a instruction range and
+ if (RangeBeginMI) {
+ // If we have alread seen a beginning of a instruction range and
// current instruction scope does not match scope of first instruction
// in this range then create a new instruction range.
DbgRange R(RangeBeginMI, PrevMI);
- MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevScope,
+ MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevScope,
PrevInlinedAt);
MIRanges.push_back(R);
- }
+ }
// This is a beginning of a new instruction range.
RangeBeginMI = MInsn;
-
+
// Reset previous markers.
PrevMI = MInsn;
PrevScope = Scope;
@@ -2588,7 +2596,7 @@
MIRanges.push_back(R);
MI2ScopeMap[RangeBeginMI] = getOrCreateDbgScope(PrevScope, PrevInlinedAt);
}
-
+
if (!CurrentFnDbgScope)
return false;
@@ -2618,7 +2626,7 @@
return !DbgScopeMap.empty();
}
-/// identifyScopeMarkers() -
+/// identifyScopeMarkers() -
/// Each DbgScope has first instruction and last instruction to mark beginning
/// and end of a scope respectively. Create an inverse map that list scopes
/// starts (and ends) with an instruction. One instruction may start (or end)
@@ -2628,23 +2636,23 @@
WorkList.push_back(CurrentFnDbgScope);
while (!WorkList.empty()) {
DbgScope *S = WorkList.pop_back_val();
-
+
const SmallVector<DbgScope *, 4> &Children = S->getScopes();
- if (!Children.empty())
+ if (!Children.empty())
for (SmallVector<DbgScope *, 4>::const_iterator SI = Children.begin(),
SE = Children.end(); SI != SE; ++SI)
WorkList.push_back(*SI);
if (S->isAbstractScope())
continue;
-
+
const SmallVector<DbgRange, 4> &Ranges = S->getRanges();
if (Ranges.empty())
continue;
for (SmallVector<DbgRange, 4>::const_iterator RI = Ranges.begin(),
RE = Ranges.end(); RI != RE; ++RI) {
- assert(RI->first && "DbgRange does not have first instruction!");
- assert(RI->second && "DbgRange does not have second instruction!");
+ assert(RI->first && "DbgRange does not have first instruction!");
+ assert(RI->second && "DbgRange does not have second instruction!");
InsnsEndScopeSet.insert(RI->second);
}
}
@@ -2680,20 +2688,23 @@
// function.
DebugLoc FDL = FindFirstDebugLoc(MF);
if (FDL.isUnknown()) return;
-
+
const MDNode *Scope = FDL.getScope(MF->getFunction()->getContext());
-
+ const MDNode *TheScope = 0;
+
DISubprogram SP = getDISubprogram(Scope);
unsigned Line, Col;
if (SP.Verify()) {
Line = SP.getLineNumber();
Col = 0;
+ TheScope = SP;
} else {
Line = FDL.getLine();
Col = FDL.getCol();
+ TheScope = Scope;
}
-
- recordSourceLine(Line, Col, Scope);
+
+ recordSourceLine(Line, Col, TheScope);
/// ProcessedArgs - Collection of arguments already processed.
SmallPtrSet<const MDNode *, 8> ProcessedArgs;
@@ -2710,7 +2721,7 @@
DIVariable DV(MI->getOperand(MI->getNumOperands() - 1).getMetadata());
if (!DV.Verify()) continue;
// If DBG_VALUE is for a local variable then it needs a label.
- if (DV.getTag() != dwarf::DW_TAG_arg_variable
+ if (DV.getTag() != dwarf::DW_TAG_arg_variable
&& isDbgValueInUndefinedReg(MI) == false)
InsnNeedsLabel.insert(MI);
// DBG_VALUE for inlined functions argument needs a label.
@@ -2718,10 +2729,11 @@
describes(MF->getFunction()))
InsnNeedsLabel.insert(MI);
// DBG_VALUE indicating argument location change needs a label.
- else if (isDbgValueInUndefinedReg(MI) == false && !ProcessedArgs.insert(DV))
+ else if (isDbgValueInUndefinedReg(MI) == false
+ && !ProcessedArgs.insert(DV))
InsnNeedsLabel.insert(MI);
} else {
- // If location is unknown then instruction needs a location only if
+ // If location is unknown then instruction needs a location only if
// UnknownLocations flag is set.
if (DL.isUnknown()) {
if (UnknownLocations && !PrevLoc.isUnknown())
@@ -2730,7 +2742,7 @@
// Otherwise, instruction needs a location only if it is new location.
InsnNeedsLabel.insert(MI);
}
-
+
if (!DL.isUnknown() || UnknownLocations)
PrevLoc = DL;
}
@@ -2750,7 +2762,7 @@
Asm->getFunctionNumber());
// Assumes in correct section after the entry point.
Asm->OutStreamer.EmitLabel(FunctionEndSym);
-
+
SmallPtrSet<const MDNode *, 16> ProcessedVars;
collectVariableInfo(MF, ProcessedVars);
@@ -2764,7 +2776,7 @@
SectionLineInfos.insert(SectionLineInfos.end(),
Lines.begin(), Lines.end());
}
-
+
// Construct abstract scopes.
for (SmallVector<DbgScope *, 4>::iterator AI = AbstractScopesList.begin(),
AE = AbstractScopesList.end(); AI != AE; ++AI) {
@@ -2775,11 +2787,11 @@
if (FName.empty())
FName = SP.getName();
const Module *M = MF->getFunction()->getParent();
- if (NamedMDNode *NMD =
- M->getNamedMetadata(Twine("llvm.dbg.lv.",
+ if (NamedMDNode *NMD =
+ M->getNamedMetadata(Twine("llvm.dbg.lv.",
getRealLinkageName(FName)))) {
for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
- DIVariable DV(cast_or_null<MDNode>(NMD->getOperand(i)));
+ DIVariable DV(cast<MDNode>(NMD->getOperand(i)));
if (!DV || !ProcessedVars.insert(DV))
continue;
DbgScope *Scope = AbstractScopes.lookup(DV.getContext());
@@ -2793,9 +2805,9 @@
}
DIE *CurFnDIE = constructScopeDIE(CurrentFnDbgScope);
-
+
if (!DisableFramePointerElim(*MF))
- addUInt(CurFnDIE, dwarf::DW_AT_APPLE_omit_frame_ptr,
+ addUInt(CurFnDIE, dwarf::DW_AT_APPLE_omit_frame_ptr,
dwarf::DW_FORM_flag, 1);
@@ -2849,22 +2861,22 @@
else return I->second;
}
-/// findDbgScope - Find DbgScope for the debug loc attached with an
+/// findDbgScope - Find DbgScope for the debug loc attached with an
/// instruction.
DbgScope *DwarfDebug::findDbgScope(const MachineInstr *MInsn) {
DbgScope *Scope = NULL;
- LLVMContext &Ctx =
+ LLVMContext &Ctx =
MInsn->getParent()->getParent()->getFunction()->getContext();
DebugLoc DL = MInsn->getDebugLoc();
- if (DL.isUnknown())
+ if (DL.isUnknown())
return Scope;
if (const MDNode *IA = DL.getInlinedAt(Ctx))
Scope = ConcreteScopes.lookup(IA);
if (Scope == 0)
Scope = DbgScopeMap.lookup(DL.getScope(Ctx));
-
+
return Scope;
}
@@ -2872,7 +2884,7 @@
/// recordSourceLine - Register a source line with debug info. Returns the
/// unique label that was emitted and which provides correspondence to
/// the source line list.
-MCSymbol *DwarfDebug::recordSourceLine(unsigned Line, unsigned Col,
+MCSymbol *DwarfDebug::recordSourceLine(unsigned Line, unsigned Col,
const MDNode *S) {
StringRef Dir;
StringRef Fn;
@@ -2899,16 +2911,6 @@
Src = GetOrCreateSourceID(Dir, Fn);
}
-#if 0
- if (!Lines.empty()) {
- SrcLineInfo lastSrcLineInfo = Lines.back();
- // Emitting sequential line records with the same line number (but
- // different addresses) seems to confuse GDB. Avoid this.
- if (lastSrcLineInfo.getLine() == Line)
- return NULL;
- }
-#endif
-
MCSymbol *Label = MMI->getContext().CreateTempSymbol();
Lines.push_back(SrcLineInfo(Line, Col, Src, Label));
@@ -2991,7 +2993,7 @@
const char *SymbolStem = 0) {
Asm->OutStreamer.SwitchSection(Section);
if (!SymbolStem) return 0;
-
+
MCSymbol *TmpSym = Asm->GetTempSymbol(SymbolStem);
Asm->OutStreamer.EmitLabel(TmpSym);
return TmpSym;
@@ -3008,21 +3010,21 @@
EmitSectionSym(Asm, TLOF.getDwarfFrameSection(), "section_debug_frame");
}
- DwarfInfoSectionSym =
+ DwarfInfoSectionSym =
EmitSectionSym(Asm, TLOF.getDwarfInfoSection(), "section_info");
- DwarfAbbrevSectionSym =
+ DwarfAbbrevSectionSym =
EmitSectionSym(Asm, TLOF.getDwarfAbbrevSection(), "section_abbrev");
EmitSectionSym(Asm, TLOF.getDwarfARangesSection());
-
+
if (const MCSection *MacroInfo = TLOF.getDwarfMacroInfoSection())
EmitSectionSym(Asm, MacroInfo);
- DwarfDebugLineSectionSym =
+ DwarfDebugLineSectionSym =
EmitSectionSym(Asm, TLOF.getDwarfLineSection(), "section_line");
EmitSectionSym(Asm, TLOF.getDwarfLocSection());
EmitSectionSym(Asm, TLOF.getDwarfPubNamesSection());
EmitSectionSym(Asm, TLOF.getDwarfPubTypesSection());
- DwarfStrSectionSym =
+ DwarfStrSectionSym =
EmitSectionSym(Asm, TLOF.getDwarfStrSection(), "section_str");
DwarfDebugRangeSectionSym = EmitSectionSym(Asm, TLOF.getDwarfRangesSection(),
"debug_range");
@@ -3060,7 +3062,7 @@
if (Asm->isVerbose())
Asm->OutStreamer.AddComment(dwarf::AttributeString(Attr));
-
+
switch (Attr) {
case dwarf::DW_AT_sibling:
Asm->EmitInt32(Die->getSiblingOffset());
@@ -3082,7 +3084,7 @@
break;
}
case dwarf::DW_AT_stmt_list: {
- Asm->EmitLabelDifference(CurrentLineSectionSym,
+ Asm->EmitLabelDifference(CurrentLineSectionSym,
DwarfDebugLineSectionSym, 4);
break;
}
@@ -3124,18 +3126,18 @@
E = CUMap.end(); I != E; ++I) {
CompileUnit *TheCU = I->second;
DIE *Die = TheCU->getCUDie();
-
+
// Emit the compile units header.
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("info_begin",
TheCU->getID()));
-
+
// Emit size of content not including length itself
unsigned ContentSize = Die->getSize() +
sizeof(int16_t) + // DWARF version number
sizeof(int32_t) + // Offset Into Abbrev. Section
sizeof(int8_t) + // Pointer Size (in bytes)
sizeof(int32_t); // FIXME - extra pad for gdb bug.
-
+
Asm->OutStreamer.AddComment("Length of Compilation Unit Info");
Asm->EmitInt32(ContentSize);
Asm->OutStreamer.AddComment("DWARF version number");
@@ -3145,7 +3147,7 @@
DwarfAbbrevSectionSym);
Asm->OutStreamer.AddComment("Address Size (in bytes)");
Asm->EmitInt8(Asm->getTargetData().getPointerSize());
-
+
emitDIE(Die);
// FIXME - extra padding for gdb bug.
Asm->OutStreamer.AddComment("4 extra padding bytes for GDB");
@@ -3194,7 +3196,7 @@
// Define last address of section.
Asm->OutStreamer.AddComment("Extended Op");
Asm->EmitInt8(0);
-
+
Asm->OutStreamer.AddComment("Op size");
Asm->EmitInt8(Asm->getTargetData().getPointerSize() + 1);
Asm->OutStreamer.AddComment("DW_LNE_set_address");
@@ -3239,7 +3241,7 @@
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("line_begin"));
Asm->OutStreamer.AddComment("DWARF version number");
- Asm->EmitInt16(dwarf::DWARF_VERSION);
+ Asm->EmitInt16(dwarf::DWARF_VERSION);
Asm->OutStreamer.AddComment("Prolog Length");
Asm->EmitLabelDifference(Asm->GetTempSymbol("line_prolog_end"),
@@ -3294,7 +3296,7 @@
const std::string &FN = getSourceFileName(Id.second);
if (Asm->isVerbose()) Asm->OutStreamer.AddComment("Source");
Asm->OutStreamer.EmitBytes(StringRef(FN.c_str(), FN.size()+1), 0);
-
+
Asm->EmitULEB128(Id.first, "Directory #");
Asm->EmitULEB128(0, "Mod date");
Asm->EmitULEB128(0, "File size");
@@ -3338,18 +3340,18 @@
Asm->EmitInt8(Asm->getTargetData().getPointerSize() + 1);
Asm->OutStreamer.AddComment("DW_LNE_set_address");
- Asm->EmitInt8(dwarf::DW_LNE_set_address);
+ Asm->EmitInt8(dwarf::DW_LNE_set_address);
Asm->OutStreamer.AddComment("Location label");
Asm->OutStreamer.EmitSymbolValue(Label,
Asm->getTargetData().getPointerSize(),
0/*AddrSpace*/);
-
+
// If change of source, then switch to the new source.
if (Source != LineInfo.getSourceID()) {
Source = LineInfo.getSourceID();
Asm->OutStreamer.AddComment("DW_LNS_set_file");
- Asm->EmitInt8(dwarf::DW_LNS_set_file);
+ Asm->EmitInt8(dwarf::DW_LNS_set_file);
Asm->EmitULEB128(Source, "New Source");
}
@@ -3457,7 +3459,7 @@
Asm->OutStreamer.EmitLabel(DebugFrameBegin);
Asm->OutStreamer.AddComment("FDE CIE offset");
- Asm->EmitSectionOffset(Asm->GetTempSymbol("debug_frame_common"),
+ Asm->EmitSectionOffset(Asm->GetTempSymbol("debug_frame_common"),
DwarfFrameSectionSym);
Asm->OutStreamer.AddComment("FDE initial location");
@@ -3466,8 +3468,8 @@
Asm->OutStreamer.EmitSymbolValue(FuncBeginSym,
Asm->getTargetData().getPointerSize(),
0/*AddrSpace*/);
-
-
+
+
Asm->OutStreamer.AddComment("FDE address range");
Asm->EmitLabelDifference(Asm->GetTempSymbol("func_end",DebugFrameInfo.Number),
FuncBeginSym, Asm->getTargetData().getPointerSize());
@@ -3487,41 +3489,41 @@
// Start the dwarf pubnames section.
Asm->OutStreamer.SwitchSection(
Asm->getObjFileLowering().getDwarfPubNamesSection());
-
+
Asm->OutStreamer.AddComment("Length of Public Names Info");
Asm->EmitLabelDifference(
Asm->GetTempSymbol("pubnames_end", TheCU->getID()),
Asm->GetTempSymbol("pubnames_begin", TheCU->getID()), 4);
-
+
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubnames_begin",
TheCU->getID()));
-
+
Asm->OutStreamer.AddComment("DWARF Version");
- Asm->EmitInt16(dwarf::DWARF_VERSION);
-
+ Asm->EmitInt16(dwarf::DWARF_VERSION);
+
Asm->OutStreamer.AddComment("Offset of Compilation Unit Info");
- Asm->EmitSectionOffset(Asm->GetTempSymbol("info_begin", TheCU->getID()),
+ Asm->EmitSectionOffset(Asm->GetTempSymbol("info_begin", TheCU->getID()),
DwarfInfoSectionSym);
-
+
Asm->OutStreamer.AddComment("Compilation Unit Length");
Asm->EmitLabelDifference(Asm->GetTempSymbol("info_end", TheCU->getID()),
Asm->GetTempSymbol("info_begin", TheCU->getID()),
4);
-
+
const StringMap<DIE*> &Globals = TheCU->getGlobals();
for (StringMap<DIE*>::const_iterator
GI = Globals.begin(), GE = Globals.end(); GI != GE; ++GI) {
const char *Name = GI->getKeyData();
DIE *Entity = GI->second;
-
+
Asm->OutStreamer.AddComment("DIE offset");
Asm->EmitInt32(Entity->getOffset());
-
+
if (Asm->isVerbose())
Asm->OutStreamer.AddComment("External Name");
Asm->OutStreamer.EmitBytes(StringRef(Name, strlen(Name)+1), 0);
}
-
+
Asm->OutStreamer.AddComment("End Mark");
Asm->EmitInt32(0);
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubnames_end",
@@ -3540,37 +3542,37 @@
Asm->EmitLabelDifference(
Asm->GetTempSymbol("pubtypes_end", TheCU->getID()),
Asm->GetTempSymbol("pubtypes_begin", TheCU->getID()), 4);
-
+
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubtypes_begin",
TheCU->getID()));
-
+
if (Asm->isVerbose()) Asm->OutStreamer.AddComment("DWARF Version");
Asm->EmitInt16(dwarf::DWARF_VERSION);
-
+
Asm->OutStreamer.AddComment("Offset of Compilation Unit Info");
Asm->EmitSectionOffset(Asm->GetTempSymbol("info_begin", TheCU->getID()),
DwarfInfoSectionSym);
-
+
Asm->OutStreamer.AddComment("Compilation Unit Length");
Asm->EmitLabelDifference(Asm->GetTempSymbol("info_end", TheCU->getID()),
Asm->GetTempSymbol("info_begin", TheCU->getID()),
4);
-
+
const StringMap<DIE*> &Globals = TheCU->getGlobalTypes();
for (StringMap<DIE*>::const_iterator
GI = Globals.begin(), GE = Globals.end(); GI != GE; ++GI) {
const char *Name = GI->getKeyData();
DIE * Entity = GI->second;
-
+
if (Asm->isVerbose()) Asm->OutStreamer.AddComment("DIE offset");
Asm->EmitInt32(Entity->getOffset());
-
+
if (Asm->isVerbose()) Asm->OutStreamer.AddComment("External Name");
Asm->OutStreamer.EmitBytes(StringRef(Name, GI->getKeyLength()+1), 0);
}
-
+
Asm->OutStreamer.AddComment("End Mark");
- Asm->EmitInt32(0);
+ Asm->EmitInt32(0);
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("pubtypes_end",
TheCU->getID()));
}
@@ -3581,26 +3583,26 @@
void DwarfDebug::emitDebugStr() {
// Check to see if it is worth the effort.
if (StringPool.empty()) return;
-
+
// Start the dwarf str section.
Asm->OutStreamer.SwitchSection(
Asm->getObjFileLowering().getDwarfStrSection());
// Get all of the string pool entries and put them in an array by their ID so
// we can sort them.
- SmallVector<std::pair<unsigned,
+ SmallVector<std::pair<unsigned,
StringMapEntry<std::pair<MCSymbol*, unsigned> >*>, 64> Entries;
-
+
for (StringMap<std::pair<MCSymbol*, unsigned> >::iterator
I = StringPool.begin(), E = StringPool.end(); I != E; ++I)
Entries.push_back(std::make_pair(I->second.second, &*I));
-
+
array_pod_sort(Entries.begin(), Entries.end());
-
+
for (unsigned i = 0, e = Entries.size(); i != e; ++i) {
// Emit a label for reference from debug information entries.
Asm->OutStreamer.EmitLabel(Entries[i].second->getValue().first);
-
+
// Emit the string itself.
Asm->OutStreamer.EmitBytes(Entries[i].second->getKey(), 0/*addrspace*/);
}
@@ -3618,8 +3620,8 @@
unsigned char Size = Asm->getTargetData().getPointerSize();
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("debug_loc", 0));
unsigned index = 1;
- for (SmallVector<DotDebugLocEntry, 4>::iterator
- I = DotDebugLocEntries.begin(), E = DotDebugLocEntries.end();
+ for (SmallVector<DotDebugLocEntry, 4>::iterator
+ I = DotDebugLocEntries.begin(), E = DotDebugLocEntries.end();
I != E; ++I, ++index) {
DotDebugLocEntry Entry = *I;
if (Entry.isEmpty()) {
@@ -3661,7 +3663,7 @@
Asm->getObjFileLowering().getDwarfRangesSection());
unsigned char Size = Asm->getTargetData().getPointerSize();
for (SmallVector<const MCSymbol *, 8>::iterator
- I = DebugRangeSymbols.begin(), E = DebugRangeSymbols.end();
+ I = DebugRangeSymbols.begin(), E = DebugRangeSymbols.end();
I != E; ++I) {
if (*I)
Asm->OutStreamer.EmitSymbolValue(const_cast<MCSymbol*>(*I), Size, 0);
@@ -3734,7 +3736,7 @@
if (LName.empty()) {
Asm->OutStreamer.EmitBytes(Name, 0);
Asm->OutStreamer.EmitIntValue(0, 1, 0); // nul terminator.
- } else
+ } else
Asm->EmitSectionOffset(getStringPoolEntry(getRealLinkageName(LName)),
DwarfStrSectionSym);
Modified: llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -57,6 +57,7 @@
RegAllocPBQP.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp
+ RenderMachineFunction.cpp
ScheduleDAG.cpp
ScheduleDAGEmit.cpp
ScheduleDAGInstrs.cpp
@@ -67,6 +68,8 @@
SjLjEHPrepare.cpp
SlotIndexes.cpp
Spiller.cpp
+ SplitKit.cpp
+ Splitter.cpp
StackProtector.cpp
StackSlotColoring.cpp
StrongPHIElimination.cpp
Modified: llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CalcSpillWeights.cpp Sat Jul 31 19:59:02 2010
@@ -25,8 +25,8 @@
using namespace llvm;
char CalculateSpillWeights::ID = 0;
-static RegisterPass<CalculateSpillWeights> X("calcspillweights",
- "Calculate spill weights");
+INITIALIZE_PASS(CalculateSpillWeights, "calcspillweights",
+ "Calculate spill weights", false, false);
void CalculateSpillWeights::getAnalysisUsage(AnalysisUsage &au) const {
au.addRequired<LiveIntervals>();
@@ -43,7 +43,6 @@
LiveIntervals *lis = &getAnalysis<LiveIntervals>();
MachineLoopInfo *loopInfo = &getAnalysis<MachineLoopInfo>();
- const TargetInstrInfo *tii = fn.getTarget().getInstrInfo();
MachineRegisterInfo *mri = &fn.getRegInfo();
SmallSet<unsigned, 4> processed;
@@ -58,7 +57,7 @@
for (MachineBasicBlock::const_iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ++mii) {
const MachineInstr *mi = mii;
- if (tii->isIdentityCopy(*mi) || mi->isImplicitDef() || mi->isDebugValue())
+ if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
continue;
for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.cpp Sat Jul 31 19:59:02 2010
@@ -32,21 +32,21 @@
MRI(MF.getRegInfo()),
TII(MF.getTarget().getInstrInfo()),
TRI(MF.getTarget().getRegisterInfo()),
- AllocatableSet(TRI->getAllocatableSet(MF))
-{
-}
+ AllocatableSet(TRI->getAllocatableSet(MF)),
+ Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
+ KillIndices(TRI->getNumRegs(), 0),
+ DefIndices(TRI->getNumRegs(), 0) {}
CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
}
void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
- // Clear out the register class data.
- std::fill(Classes, array_endof(Classes),
- static_cast<const TargetRegisterClass *>(0));
-
- // Initialize the indices to indicate that no registers are live.
const unsigned BBSize = BB->size();
- for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
+ for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
+ // Clear out the register class data.
+ Classes[i] = static_cast<const TargetRegisterClass *>(0);
+
+ // Initialize the indices to indicate that no registers are live.
KillIndices[i] = ~0u;
DefIndices[i] = BBSize;
}
@@ -65,6 +65,7 @@
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
DefIndices[Reg] = ~0u;
+
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
@@ -86,6 +87,7 @@
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
DefIndices[Reg] = ~0u;
+
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
@@ -106,6 +108,7 @@
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
KillIndices[Reg] = BB->size();
DefIndices[Reg] = ~0u;
+
// Repeat, for all aliases.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
@@ -134,8 +137,10 @@
for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
+
// Mark this register to be non-renamable.
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
+
// Move the def index to the end of the previous region, to reflect
// that the def could theoretically have been scheduled at the end.
DefIndices[Reg] = InsertPosIndex;
@@ -433,7 +438,7 @@
// fix that remaining critical edge too. This is a little more involved,
// because unlike the most recent register, less recent registers should
// still be considered, though only if no other registers are available.
- unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
+ std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
// Attempt to break anti-dependence edges on the critical path. Walk the
// instructions from the bottom up, tracking information about liveness
Modified: llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/CriticalAntiDepBreaker.h Sat Jul 31 19:59:02 2010
@@ -46,19 +46,18 @@
/// corresponding value is null. If the register is live but used in
/// multiple register classes, the corresponding value is -1 casted to a
/// pointer.
- const TargetRegisterClass *
- Classes[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<const TargetRegisterClass*> Classes;
/// RegRegs - Map registers to all their references within a live range.
std::multimap<unsigned, MachineOperand *> RegRefs;
/// KillIndices - The index of the most recent kill (proceding bottom-up),
/// or ~0u if the register is not live.
- unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> KillIndices;
/// DefIndices - The index of the most recent complete def (proceding bottom
/// up), or ~0u if the register is live.
- unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> DefIndices;
/// KeepRegs - A set of registers which are live and cannot be changed to
/// break anti-dependencies.
Modified: llvm/branches/wendling/eh/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/DeadMachineInstructionElim.cpp Sat Jul 31 19:59:02 2010
@@ -44,9 +44,8 @@
}
char DeadMachineInstructionElim::ID = 0;
-static RegisterPass<DeadMachineInstructionElim>
-Y("dead-mi-elimination",
- "Remove dead machine instructions");
+INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
+ "Remove dead machine instructions", false, false);
FunctionPass *llvm::createDeadMachineInstructionElimPass() {
return new DeadMachineInstructionElim();
Modified: llvm/branches/wendling/eh/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/DwarfEHPrepare.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/DwarfEHPrepare.cpp Sat Jul 31 19:59:02 2010
@@ -86,7 +86,7 @@
}
/// CleanupSelectors - Any remaining eh.selector intrinsic calls which still
- /// use the ".llvm.eh.catch.all.value" call need to convert to using its
+ /// use the "llvm.eh.catch.all.value" call need to convert to using its
/// initializer instead.
bool CleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels);
@@ -144,7 +144,7 @@
SI = 0;
for (Value::use_iterator
I = II->use_begin(), E = II->use_end(); I != E; ++I) {
- SI = dyn_cast<StoreInst>(I);
+ SI = dyn_cast<StoreInst>(*I);
if (SI) break;
}
@@ -207,7 +207,7 @@
for (Value::use_iterator
I = SelectorIntrinsic->use_begin(),
E = SelectorIntrinsic->use_end(); I != E; ++I) {
- IntrinsicInst *II = cast<IntrinsicInst>(I);
+ IntrinsicInst *II = cast<IntrinsicInst>(*I);
if (II->getParent()->getParent() != F)
continue;
@@ -225,13 +225,13 @@
for (Value::use_iterator
I = URoR->use_begin(),
E = URoR->use_end(); I != E; ++I) {
- if (InvokeInst *II = dyn_cast<InvokeInst>(I))
+ if (InvokeInst *II = dyn_cast<InvokeInst>(*I))
URoRInvokes.insert(II);
}
}
/// CleanupSelectors - Any remaining eh.selector intrinsic calls which still use
-/// the ".llvm.eh.catch.all.value" call need to convert to using its
+/// the "llvm.eh.catch.all.value" call need to convert to using its
/// initializer instead.
bool DwarfEHPrepare::CleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels) {
if (!EHCatchAllValue) return false;
@@ -247,7 +247,7 @@
I = Sels.begin(), E = Sels.end(); I != E; ++I) {
IntrinsicInst *Sel = *I;
- // Index of the ".llvm.eh.catch.all.value" variable.
+ // Index of the "llvm.eh.catch.all.value" variable.
unsigned OpIdx = Sel->getNumArgOperands() - 1;
GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx));
if (GV != EHCatchAllValue) continue;
@@ -271,7 +271,7 @@
restart:
for (Value::use_iterator
I = Inst->use_begin(), E = Inst->use_end(); I != E; ++I) {
- Instruction *II = dyn_cast<Instruction>(I);
+ Instruction *II = dyn_cast<Instruction>(*I);
if (!II || II->getParent()->getParent() != F) continue;
if (IntrinsicInst *Sel = dyn_cast<IntrinsicInst>(II)) {
@@ -304,7 +304,7 @@
bool DwarfEHPrepare::HandleURoRInvokes() {
if (!EHCatchAllValue) {
EHCatchAllValue =
- F->getParent()->getNamedGlobal(".llvm.eh.catch.all.value");
+ F->getParent()->getNamedGlobal("llvm.eh.catch.all.value");
if (!EHCatchAllValue) return false;
}
@@ -338,7 +338,7 @@
for (SmallPtrSet<InvokeInst*, 32>::iterator
UI = URoRInvokes.begin(), UE = URoRInvokes.end(); UI != UE; ++UI) {
const BasicBlock *URoRBB = (*UI)->getParent();
- if (SelBB == URoRBB || DT->dominates(SelBB, URoRBB)) {
+ if (DT->dominates(SelBB, URoRBB)) {
SelsToConvert.insert(*SI);
break;
}
@@ -360,7 +360,7 @@
for (Value::use_iterator
I = ExceptionValueIntrinsic->use_begin(),
E = ExceptionValueIntrinsic->use_end(); I != E; ++I) {
- IntrinsicInst *EHPtr = dyn_cast<IntrinsicInst>(I);
+ IntrinsicInst *EHPtr = dyn_cast<IntrinsicInst>(*I);
if (!EHPtr || EHPtr->getParent()->getParent() != F) continue;
Changed |= PromoteEHPtrStore(EHPtr);
Modified: llvm/branches/wendling/eh/lib/CodeGen/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ELF.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ELF.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ELF.h Sat Jul 31 19:59:02 2010
@@ -22,36 +22,12 @@
#include "llvm/CodeGen/BinaryObject.h"
#include "llvm/CodeGen/MachineRelocation.h"
+#include "llvm/Support/ELF.h"
#include "llvm/System/DataTypes.h"
namespace llvm {
class GlobalValue;
- // Identification Indexes
- enum {
- EI_MAG0 = 0,
- EI_MAG1 = 1,
- EI_MAG2 = 2,
- EI_MAG3 = 3
- };
-
- // File types
- enum {
- ET_NONE = 0, // No file type
- ET_REL = 1, // Relocatable file
- ET_EXEC = 2, // Executable file
- ET_DYN = 3, // Shared object file
- ET_CORE = 4, // Core file
- ET_LOPROC = 0xff00, // Beginning of processor-specific codes
- ET_HIPROC = 0xffff // Processor-specific
- };
-
- // Versioning
- enum {
- EV_NONE = 0,
- EV_CURRENT = 1
- };
-
/// ELFSym - This struct contains information about each symbol that is
/// added to logical symbol table for the module. This is eventually
/// turned into a real symbol table in the file.
@@ -108,9 +84,9 @@
static ELFSym *getExtSym(const char *Ext) {
ELFSym *Sym = new ELFSym();
Sym->Source.Ext = Ext;
- Sym->setBind(STB_GLOBAL);
- Sym->setType(STT_NOTYPE);
- Sym->setVisibility(STV_DEFAULT);
+ Sym->setBind(ELF::STB_GLOBAL);
+ Sym->setType(ELF::STT_NOTYPE);
+ Sym->setVisibility(ELF::STV_DEFAULT);
Sym->SourceType = isExtSym;
return Sym;
}
@@ -118,9 +94,9 @@
// getSectionSym - Returns a elf symbol to represent an elf section
static ELFSym *getSectionSym() {
ELFSym *Sym = new ELFSym();
- Sym->setBind(STB_LOCAL);
- Sym->setType(STT_SECTION);
- Sym->setVisibility(STV_DEFAULT);
+ Sym->setBind(ELF::STB_LOCAL);
+ Sym->setType(ELF::STT_SECTION);
+ Sym->setVisibility(ELF::STV_DEFAULT);
Sym->SourceType = isOther;
return Sym;
}
@@ -128,9 +104,9 @@
// getFileSym - Returns a elf symbol to represent the module identifier
static ELFSym *getFileSym() {
ELFSym *Sym = new ELFSym();
- Sym->setBind(STB_LOCAL);
- Sym->setType(STT_FILE);
- Sym->setVisibility(STV_DEFAULT);
+ Sym->setBind(ELF::STB_LOCAL);
+ Sym->setType(ELF::STT_FILE);
+ Sym->setVisibility(ELF::STV_DEFAULT);
Sym->SectionIdx = 0xfff1; // ELFSection::SHN_ABS;
Sym->SourceType = isOther;
return Sym;
@@ -141,8 +117,8 @@
ELFSym *Sym = new ELFSym();
Sym->Source.GV = GV;
Sym->setBind(Bind);
- Sym->setType(STT_NOTYPE);
- Sym->setVisibility(STV_DEFAULT);
+ Sym->setType(ELF::STT_NOTYPE);
+ Sym->setVisibility(ELF::STV_DEFAULT);
Sym->SectionIdx = 0; //ELFSection::SHN_UNDEF;
Sym->SourceType = isGV;
return Sym;
@@ -159,35 +135,14 @@
// Symbol index into the Symbol table
unsigned SymTabIdx;
- enum {
- STB_LOCAL = 0, // Local sym, not visible outside obj file containing def
- STB_GLOBAL = 1, // Global sym, visible to all object files being combined
- STB_WEAK = 2 // Weak symbol, like global but lower-precedence
- };
-
- enum {
- STT_NOTYPE = 0, // Symbol's type is not specified
- STT_OBJECT = 1, // Symbol is a data object (variable, array, etc.)
- STT_FUNC = 2, // Symbol is executable code (function, etc.)
- STT_SECTION = 3, // Symbol refers to a section
- STT_FILE = 4 // Local, absolute symbol that refers to a file
- };
-
- enum {
- STV_DEFAULT = 0, // Visibility is specified by binding type
- STV_INTERNAL = 1, // Defined by processor supplements
- STV_HIDDEN = 2, // Not visible to other components
- STV_PROTECTED = 3 // Visible in other components but not preemptable
- };
-
ELFSym() : SourceType(isOther), NameIdx(0), Value(0),
- Size(0), Info(0), Other(STV_DEFAULT), SectionIdx(0),
+ Size(0), Info(0), Other(ELF::STV_DEFAULT), SectionIdx(0),
SymTabIdx(0) {}
unsigned getBind() const { return (Info >> 4) & 0xf; }
unsigned getType() const { return Info & 0xf; }
- bool isLocalBind() const { return getBind() == STB_LOCAL; }
- bool isFileType() const { return getType() == STT_FILE; }
+ bool isLocalBind() const { return getBind() == ELF::STB_LOCAL; }
+ bool isFileType() const { return getType() == ELF::STT_FILE; }
void setBind(unsigned X) {
assert(X == (X & 0xF) && "Bind value out of range!");
@@ -222,51 +177,6 @@
unsigned Align; // sh_addralign - Alignment of section.
unsigned EntSize; // sh_entsize - Size of entries in the section e
- // Section Header Flags
- enum {
- SHF_WRITE = 1 << 0, // Writable
- SHF_ALLOC = 1 << 1, // Mapped into the process addr space
- SHF_EXECINSTR = 1 << 2, // Executable
- SHF_MERGE = 1 << 4, // Might be merged if equal
- SHF_STRINGS = 1 << 5, // Contains null-terminated strings
- SHF_INFO_LINK = 1 << 6, // 'sh_info' contains SHT index
- SHF_LINK_ORDER = 1 << 7, // Preserve order after combining
- SHF_OS_NONCONFORMING = 1 << 8, // nonstandard OS support required
- SHF_GROUP = 1 << 9, // Section is a member of a group
- SHF_TLS = 1 << 10 // Section holds thread-local data
- };
-
- // Section Types
- enum {
- SHT_NULL = 0, // No associated section (inactive entry).
- SHT_PROGBITS = 1, // Program-defined contents.
- SHT_SYMTAB = 2, // Symbol table.
- SHT_STRTAB = 3, // String table.
- SHT_RELA = 4, // Relocation entries; explicit addends.
- SHT_HASH = 5, // Symbol hash table.
- SHT_DYNAMIC = 6, // Information for dynamic linking.
- SHT_NOTE = 7, // Information about the file.
- SHT_NOBITS = 8, // Data occupies no space in the file.
- SHT_REL = 9, // Relocation entries; no explicit addends.
- SHT_SHLIB = 10, // Reserved.
- SHT_DYNSYM = 11, // Symbol table.
- SHT_LOPROC = 0x70000000, // Lowest processor arch-specific type.
- SHT_HIPROC = 0x7fffffff, // Highest processor arch-specific type.
- SHT_LOUSER = 0x80000000, // Lowest type reserved for applications.
- SHT_HIUSER = 0xffffffff // Highest type reserved for applications.
- };
-
- // Special section indices.
- enum {
- SHN_UNDEF = 0, // Undefined, missing, irrelevant
- SHN_LORESERVE = 0xff00, // Lowest reserved index
- SHN_LOPROC = 0xff00, // Lowest processor-specific index
- SHN_HIPROC = 0xff1f, // Highest processor-specific index
- SHN_ABS = 0xfff1, // Symbol has absolute value; no relocation
- SHN_COMMON = 0xfff2, // FORTRAN COMMON or C external global variables
- SHN_HIRESERVE = 0xffff // Highest reserved index
- };
-
/// SectionIdx - The number of the section in the Section Table.
unsigned short SectionIdx;
Modified: llvm/branches/wendling/eh/lib/CodeGen/ELFCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ELFCodeEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ELFCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ELFCodeEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -71,7 +71,7 @@
bool ELFCodeEmitter::finishFunction(MachineFunction &MF) {
// Add a symbol to represent the function.
const Function *F = MF.getFunction();
- ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELFSym::STT_FUNC,
+ ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELF::STT_FUNC,
EW.getGlobalELFVisibility(F));
FnSym->SectionIdx = ES->SectionIdx;
FnSym->Size = ES->getCurrentPCOffset()-FnStartOff;
Modified: llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.cpp Sat Jul 31 19:59:02 2010
@@ -129,12 +129,12 @@
ElfHdr.emitByte(TEW->getEIClass()); // e_ident[EI_CLASS]
ElfHdr.emitByte(TEW->getEIData()); // e_ident[EI_DATA]
- ElfHdr.emitByte(EV_CURRENT); // e_ident[EI_VERSION]
+ ElfHdr.emitByte(ELF::EV_CURRENT); // e_ident[EI_VERSION]
ElfHdr.emitAlignment(16); // e_ident[EI_NIDENT-EI_PAD]
- ElfHdr.emitWord16(ET_REL); // e_type
+ ElfHdr.emitWord16(ELF::ET_REL); // e_type
ElfHdr.emitWord16(TEW->getEMachine()); // e_machine = target
- ElfHdr.emitWord32(EV_CURRENT); // e_version
+ ElfHdr.emitWord32(ELF::EV_CURRENT); // e_version
ElfHdr.emitWord(0); // e_entry, no entry point in .o file
ElfHdr.emitWord(0); // e_phoff, no program header for .o
ELFHdr_e_shoff_Offset = ElfHdr.size();
@@ -252,7 +252,7 @@
// is true if the relocation section contains entries with addends.
ELFSection &ELFWriter::getRelocSection(ELFSection &S) {
unsigned SectionType = TEW->hasRelocationAddend() ?
- ELFSection::SHT_RELA : ELFSection::SHT_REL;
+ ELF::SHT_RELA : ELF::SHT_REL;
std::string SectionName(".rel");
if (TEW->hasRelocationAddend())
@@ -268,11 +268,11 @@
default:
llvm_unreachable("unknown visibility type");
case GlobalValue::DefaultVisibility:
- return ELFSym::STV_DEFAULT;
+ return ELF::STV_DEFAULT;
case GlobalValue::HiddenVisibility:
- return ELFSym::STV_HIDDEN;
+ return ELF::STV_HIDDEN;
case GlobalValue::ProtectedVisibility:
- return ELFSym::STV_PROTECTED;
+ return ELF::STV_PROTECTED;
}
return 0;
}
@@ -280,23 +280,23 @@
// getGlobalELFBinding - Returns the ELF specific binding type
unsigned ELFWriter::getGlobalELFBinding(const GlobalValue *GV) {
if (GV->hasInternalLinkage())
- return ELFSym::STB_LOCAL;
+ return ELF::STB_LOCAL;
if (GV->isWeakForLinker() && !GV->hasCommonLinkage())
- return ELFSym::STB_WEAK;
+ return ELF::STB_WEAK;
- return ELFSym::STB_GLOBAL;
+ return ELF::STB_GLOBAL;
}
// getGlobalELFType - Returns the ELF specific type for a global
unsigned ELFWriter::getGlobalELFType(const GlobalValue *GV) {
if (GV->isDeclaration())
- return ELFSym::STT_NOTYPE;
+ return ELF::STT_NOTYPE;
if (isa<Function>(GV))
- return ELFSym::STT_FUNC;
+ return ELF::STT_FUNC;
- return ELFSym::STT_OBJECT;
+ return ELF::STT_OBJECT;
}
// IsELFUndefSym - True if the global value must be marked as a symbol
@@ -364,7 +364,7 @@
GblSym->Size = Size;
if (S->HasCommonSymbols()) { // Symbol must go to a common section
- GblSym->SectionIdx = ELFSection::SHN_COMMON;
+ GblSym->SectionIdx = ELF::SHN_COMMON;
// A new linkonce section is created for each global in the
// common section, the default alignment is 1 and the symbol
Modified: llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ELFWriter.h Sat Jul 31 19:59:02 2010
@@ -160,29 +160,29 @@
SN->SectionIdx = NumSections++;
SN->Type = Type;
SN->Flags = Flags;
- SN->Link = ELFSection::SHN_UNDEF;
+ SN->Link = ELF::SHN_UNDEF;
SN->Align = Align;
return *SN;
}
ELFSection &getNonExecStackSection() {
- return getSection(".note.GNU-stack", ELFSection::SHT_PROGBITS, 0, 1);
+ return getSection(".note.GNU-stack", ELF::SHT_PROGBITS, 0, 1);
}
ELFSection &getSymbolTableSection() {
- return getSection(".symtab", ELFSection::SHT_SYMTAB, 0);
+ return getSection(".symtab", ELF::SHT_SYMTAB, 0);
}
ELFSection &getStringTableSection() {
- return getSection(".strtab", ELFSection::SHT_STRTAB, 0, 1);
+ return getSection(".strtab", ELF::SHT_STRTAB, 0, 1);
}
ELFSection &getSectionHeaderStringTableSection() {
- return getSection(".shstrtab", ELFSection::SHT_STRTAB, 0, 1);
+ return getSection(".shstrtab", ELF::SHT_STRTAB, 0, 1);
}
ELFSection &getNullSection() {
- return getSection("", ELFSection::SHT_NULL, 0);
+ return getSection("", ELF::SHT_NULL, 0);
}
ELFSection &getDataSection();
Modified: llvm/branches/wendling/eh/lib/CodeGen/GCMetadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/GCMetadata.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/GCMetadata.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/GCMetadata.cpp Sat Jul 31 19:59:02 2010
@@ -55,8 +55,8 @@
}
-static RegisterPass<GCModuleInfo>
-X("collector-metadata", "Create Garbage Collector Module Metadata");
+INITIALIZE_PASS(GCModuleInfo, "collector-metadata",
+ "Create Garbage Collector Module Metadata", false, false);
// -----------------------------------------------------------------------------
Modified: llvm/branches/wendling/eh/lib/CodeGen/GCStrategy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/GCStrategy.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/GCStrategy.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/GCStrategy.cpp Sat Jul 31 19:59:02 2010
@@ -260,7 +260,7 @@
bool LowerRd = !S.customReadBarrier();
bool InitRoots = S.initializeRoots();
- SmallVector<AllocaInst*,32> Roots;
+ SmallVector<AllocaInst*, 32> Roots;
bool MadeChange = false;
for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) {
@@ -271,7 +271,8 @@
case Intrinsic::gcwrite:
if (LowerWr) {
// Replace a write barrier with a simple store.
- Value *St = new StoreInst(CI->getArgOperand(0), CI->getArgOperand(2), CI);
+ Value *St = new StoreInst(CI->getArgOperand(0),
+ CI->getArgOperand(2), CI);
CI->replaceAllUsesWith(St);
CI->eraseFromParent();
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/IfConversion.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/IfConversion.cpp Sat Jul 31 19:59:02 2010
@@ -230,8 +230,7 @@
char IfConverter::ID = 0;
}
-static RegisterPass<IfConverter>
-X("if-converter", "If Converter");
+INITIALIZE_PASS(IfConverter, "if-converter", "If Converter", false, false);
FunctionPass *llvm::createIfConverterPass() { return new IfConverter(); }
Modified: llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/InlineSpiller.cpp Sat Jul 31 19:59:02 2010
@@ -14,10 +14,12 @@
#define DEBUG_TYPE "spiller"
#include "Spiller.h"
+#include "SplitKit.h"
#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -30,6 +32,7 @@
class InlineSpiller : public Spiller {
MachineFunction &mf_;
LiveIntervals &lis_;
+ MachineLoopInfo &loops_;
VirtRegMap &vrm_;
MachineFrameInfo &mfi_;
MachineRegisterInfo &mri_;
@@ -37,6 +40,8 @@
const TargetRegisterInfo &tri_;
const BitVector reserved_;
+ SplitAnalysis splitAnalysis_;
+
// Variables that are valid during spill(), but used by multiple methods.
LiveInterval *li_;
std::vector<LiveInterval*> *newIntervals_;
@@ -53,13 +58,19 @@
~InlineSpiller() {}
public:
- InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
- : mf_(*mf), lis_(*lis), vrm_(*vrm),
- mfi_(*mf->getFrameInfo()),
- mri_(mf->getRegInfo()),
- tii_(*mf->getTarget().getInstrInfo()),
- tri_(*mf->getTarget().getRegisterInfo()),
- reserved_(tri_.getReservedRegs(mf_)) {}
+ InlineSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm)
+ : mf_(mf),
+ lis_(pass.getAnalysis<LiveIntervals>()),
+ loops_(pass.getAnalysis<MachineLoopInfo>()),
+ vrm_(vrm),
+ mfi_(*mf.getFrameInfo()),
+ mri_(mf.getRegInfo()),
+ tii_(*mf.getTarget().getInstrInfo()),
+ tri_(*mf.getTarget().getRegisterInfo()),
+ reserved_(tri_.getReservedRegs(mf_)),
+ splitAnalysis_(mf, lis_, loops_) {}
void spill(LiveInterval *li,
std::vector<LiveInterval*> &newIntervals,
@@ -67,6 +78,8 @@
SlotIndex *earliestIndex);
private:
+ bool split();
+
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
SlotIndex UseIdx);
bool reMaterializeFor(MachineBasicBlock::iterator MI);
@@ -80,14 +93,29 @@
}
namespace llvm {
-Spiller *createInlineSpiller(MachineFunction *mf,
- LiveIntervals *lis,
- const MachineLoopInfo *mli,
- VirtRegMap *vrm) {
- return new InlineSpiller(mf, lis, vrm);
+Spiller *createInlineSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm) {
+ return new InlineSpiller(pass, mf, vrm);
}
}
+/// split - try splitting the current interval into pieces that may allocate
+/// separately. Return true if successful.
+bool InlineSpiller::split() {
+ // FIXME: Add intra-MBB splitting.
+ if (lis_.intervalIsInOneMBB(*li_))
+ return false;
+
+ splitAnalysis_.analyze(li_);
+
+ if (const MachineLoop *loop = splitAnalysis_.getBestSplitLoop()) {
+ SplitEditor(splitAnalysis_, lis_, vrm_).splitAroundLoop(loop);
+ return true;
+ }
+ return false;
+}
+
/// allUsesAvailableAt - Return true if all registers used by OrigMI at
/// OrigIdx are also available with the same value at UseIdx.
bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
@@ -335,6 +363,9 @@
rc_ = mri_.getRegClass(li->reg);
spillIs_ = &spillIs;
+ if (split())
+ return;
+
reMaterializeAll();
// Remat may handle everything.
Modified: llvm/branches/wendling/eh/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/IntrinsicLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/IntrinsicLowering.cpp Sat Jul 31 19:59:02 2010
@@ -481,7 +481,8 @@
Value *Ops[3];
Ops[0] = CI->getArgOperand(0);
// Extend the amount to i32.
- Ops[1] = Builder.CreateIntCast(CI->getArgOperand(1), Type::getInt32Ty(Context),
+ Ops[1] = Builder.CreateIntCast(CI->getArgOperand(1),
+ Type::getInt32Ty(Context),
/* isSigned */ false);
Ops[2] = Size;
ReplaceCallWith("memset", CI, Ops, Ops+3, CI->getArgOperand(0)->getType());
Modified: llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LLVMTargetMachine.cpp Sat Jul 31 19:59:02 2010
@@ -139,8 +139,6 @@
getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
// Create a code emitter if asked to show the encoding.
- //
- // FIXME: These are currently leaked.
MCCodeEmitter *MCE = 0;
if (ShowMCEncoding)
MCE = getTarget().createCodeEmitter(*this, *Context);
@@ -154,8 +152,6 @@
case CGFT_ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file
// emission fails.
- //
- // FIXME: These are currently leaked.
MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
if (MCE == 0 || TAB == 0)
@@ -216,6 +212,24 @@
return false; // success!
}
+/// addPassesToEmitMC - Add passes to the specified pass manager to get
+/// machine code emitted with the MCJIT. This method returns true if machine
+/// code is not supported. It fills the MCContext Ctx pointer which can be
+/// used to build custom MCStreamer.
+///
+bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
+ MCContext *&Ctx,
+ CodeGenOpt::Level OptLevel,
+ bool DisableVerify) {
+ // Add common CodeGen passes.
+ if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
+ return true;
+ // Make sure the code model is set.
+ setCodeModelForJIT();
+
+ return false; // success!
+}
+
static void printNoVerify(PassManagerBase &PM, const char *Banner) {
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
@@ -290,6 +304,8 @@
PM.add(createStackProtectorPass(getTargetLowering()));
+ addPreISel(PM, OptLevel);
+
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveInterval.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveInterval.cpp Sat Jul 31 19:59:02 2010
@@ -166,6 +166,20 @@
return I != begin() && (--I)->end > Start;
}
+
+/// ValNo is dead, remove it. If it is the largest value number, just nuke it
+/// (and any other deleted values neighboring it), otherwise mark it as ~1U so
+/// it can be nuked later.
+void LiveInterval::markValNoForDeletion(VNInfo *ValNo) {
+ if (ValNo->id == getNumValNums()-1) {
+ do {
+ valnos.pop_back();
+ } while (!valnos.empty() && valnos.back()->isUnused());
+ } else {
+ ValNo->setIsUnused(true);
+ }
+}
+
/// extendIntervalEndTo - This method is used when we want to extend the range
/// specified by I to end at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with. The iterator is
@@ -314,16 +328,8 @@
break;
}
if (isDead) {
- // Now that ValNo is dead, remove it. If it is the largest value
- // number, just nuke it (and any other deleted values neighboring it),
- // otherwise mark it as ~1U so it can be nuked later.
- if (ValNo->id == getNumValNums()-1) {
- do {
- valnos.pop_back();
- } while (!valnos.empty() && valnos.back()->isUnused());
- } else {
- ValNo->setIsUnused(true);
- }
+ // Now that ValNo is dead, remove it.
+ markValNoForDeletion(ValNo);
}
}
@@ -359,16 +365,8 @@
if (I->valno == ValNo)
ranges.erase(I);
} while (I != E);
- // Now that ValNo is dead, remove it. If it is the largest value
- // number, just nuke it (and any other deleted values neighboring it),
- // otherwise mark it as ~1U so it can be nuked later.
- if (ValNo->id == getNumValNums()-1) {
- do {
- valnos.pop_back();
- } while (!valnos.empty() && valnos.back()->isUnused());
- } else {
- ValNo->setIsUnused(true);
- }
+ // Now that ValNo is dead, remove it.
+ markValNoForDeletion(ValNo);
}
/// getLiveRangeContaining - Return the live range that contains the
@@ -586,16 +584,8 @@
break;
}
if (isDead) {
- // Now that V1 is dead, remove it. If it is the largest value number,
- // just nuke it (and any other deleted values neighboring it), otherwise
- // mark it as ~1U so it can be nuked later.
- if (V1->id == getNumValNums()-1) {
- do {
- valnos.pop_back();
- } while (!valnos.empty() && valnos.back()->isUnused());
- } else {
- V1->setIsUnused(true);
- }
+ // Now that V1 is dead, remove it.
+ markValNoForDeletion(V1);
}
}
}
@@ -753,16 +743,8 @@
}
}
- // Now that V1 is dead, remove it. If it is the largest value number, just
- // nuke it (and any other deleted values neighboring it), otherwise mark it as
- // ~1U so it can be nuked later.
- if (V1->id == getNumValNums()-1) {
- do {
- valnos.pop_back();
- } while (valnos.back()->isUnused());
- } else {
- V1->setIsUnused(true);
- }
+ // Now that V1 is dead, remove it.
+ markValNoForDeletion(V1);
return V2;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveIntervalAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -55,7 +55,8 @@
STATISTIC(numSplits , "Number of intervals split");
char LiveIntervals::ID = 0;
-static RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
+INITIALIZE_PASS(LiveIntervals, "liveintervals",
+ "Live Interval Analysis", false, false);
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@@ -188,10 +189,6 @@
const MachineInstr &MI = *I;
// Allow copies to and from li.reg
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
- if (SrcReg == li.reg || DstReg == li.reg)
- continue;
if (MI.isCopy())
if (MI.getOperand(0).getReg() == li.reg ||
MI.getOperand(1).getReg() == li.reg)
@@ -324,9 +321,7 @@
mi->addRegisterDefined(interval.reg);
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (mi->isCopyLike() ||
- tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
+ if (mi->isCopyLike()) {
CopyMI = mi;
}
@@ -454,9 +449,7 @@
OldValNo->setCopy(0);
// A re-def may be a copy. e.g. %reg1030:6<def> = VMOVD %reg1026, ...
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (PartReDef && (mi->isCopyLike() ||
- tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)))
+ if (PartReDef && mi->isCopyLike())
OldValNo->setCopy(&*mi);
// Add the new live interval which replaces the range for the input copy.
@@ -485,9 +478,7 @@
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (mi->isCopyLike() ||
- tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ if (mi->isCopyLike())
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
@@ -602,9 +593,7 @@
getOrCreateInterval(MO.getReg()));
else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (MI->isCopyLike() ||
- tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+ if (MI->isCopyLike())
CopyMI = MI;
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()), CopyMI);
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveStackAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveStackAnalysis.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveStackAnalysis.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveStackAnalysis.cpp Sat Jul 31 19:59:02 2010
@@ -25,7 +25,8 @@
using namespace llvm;
char LiveStacks::ID = 0;
-static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
+INITIALIZE_PASS(LiveStacks, "livestacks",
+ "Live Stack Slot Analysis", false, false);
void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
Modified: llvm/branches/wendling/eh/lib/CodeGen/LiveVariables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/LiveVariables.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/LiveVariables.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/LiveVariables.cpp Sat Jul 31 19:59:02 2010
@@ -42,7 +42,8 @@
using namespace llvm;
char LiveVariables::ID = 0;
-static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
+INITIALIZE_PASS(LiveVariables, "livevars",
+ "Live Variable Analysis", false, false);
void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineCSE.cpp Sat Jul 31 19:59:02 2010
@@ -85,8 +85,8 @@
} // end anonymous namespace
char MachineCSE::ID = 0;
-static RegisterPass<MachineCSE>
-X("machine-cse", "Machine Common Subexpression Elimination");
+INITIALIZE_PASS(MachineCSE, "machine-cse",
+ "Machine Common Subexpression Elimination", false, false);
FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
@@ -107,29 +107,9 @@
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (DefMI->getParent() != MBB)
continue;
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- TargetRegisterInfo::isVirtualRegister(SrcReg) &&
- !SrcSubIdx && !DstSubIdx) {
- const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
- const TargetRegisterClass *RC = MRI->getRegClass(Reg);
- const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
- if (!NewRC)
- continue;
- DEBUG(dbgs() << "Coalescing: " << *DefMI);
- DEBUG(dbgs() << "*** to: " << *MI);
- MO.setReg(SrcReg);
- MRI->clearKillFlags(SrcReg);
- if (NewRC != SRC)
- MRI->setRegClass(SrcReg, NewRC);
- DefMI->eraseFromParent();
- ++NumCoalesces;
- Changed = true;
- }
-
if (!DefMI->isCopy())
continue;
- SrcReg = DefMI->getOperand(1).getReg();
+ unsigned SrcReg = DefMI->getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
continue;
if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
@@ -261,19 +241,13 @@
return false;
}
-static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- return MI->isCopyLike() ||
- TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
-}
-
bool MachineCSE::isCSECandidate(MachineInstr *MI) {
if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
return false;
// Ignore copies.
- if (isCopy(MI, TII))
+ if (MI->isCopyLike())
return false;
// Ignore stuff that we obviously can't move.
@@ -329,7 +303,7 @@
E = MRI->use_nodbg_end(); I != E; ++I) {
MachineInstr *Use = &*I;
// Ignore copies.
- if (!isCopy(Use, TII)) {
+ if (!Use->isCopyLike()) {
HasNonCopyUse = true;
break;
}
@@ -385,7 +359,7 @@
// Look for trivial copy coalescing opportunities.
if (PerformTrivialCoalescing(MI, MBB)) {
// After coalescing MI itself may become a copy.
- if (isCopy(MI, TII))
+ if (MI->isCopyLike())
continue;
FoundCSE = VNT.count(MI);
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineFunction.cpp Sat Jul 31 19:59:02 2010
@@ -414,7 +414,6 @@
/// create a corresponding virtual register for it.
unsigned MachineFunction::addLiveIn(unsigned PReg,
const TargetRegisterClass *RC) {
- assert(RC->contains(PReg) && "Not the correct regclass!");
MachineRegisterInfo &MRI = getRegInfo();
unsigned VReg = MRI.getLiveInVirtReg(PReg);
if (VReg) {
@@ -464,7 +463,7 @@
unsigned StackAlign = TFI.getStackAlignment();
unsigned Align = MinAlign(SPOffset, StackAlign);
Objects.insert(Objects.begin(), StackObject(Size, Align, SPOffset, Immutable,
- /*isSS*/false));
+ /*isSS*/false, false));
return -++NumFixedObjects;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineInstr.cpp Sat Jul 31 19:59:02 2010
@@ -1236,12 +1236,18 @@
void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
// We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
const MachineFunction *MF = 0;
+ const MachineRegisterInfo *MRI = 0;
if (const MachineBasicBlock *MBB = getParent()) {
MF = MBB->getParent();
if (!TM && MF)
TM = &MF->getTarget();
+ if (MF)
+ MRI = &MF->getRegInfo();
}
+ // Save a list of virtual registers.
+ SmallVector<unsigned, 8> VirtRegs;
+
// Print explicitly defined operands on the left of an assignment syntax.
unsigned StartOp = 0, e = getNumOperands();
for (; StartOp < e && getOperand(StartOp).isReg() &&
@@ -1250,6 +1256,9 @@
++StartOp) {
if (StartOp != 0) OS << ", ";
getOperand(StartOp).print(OS, TM);
+ unsigned Reg = getOperand(StartOp).getReg();
+ if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
+ VirtRegs.push_back(Reg);
}
if (StartOp != 0)
@@ -1264,6 +1273,10 @@
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
+ if (MO.isReg() && MO.getReg() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
+ VirtRegs.push_back(MO.getReg());
+
// Omit call-clobbered registers which aren't used anywhere. This makes
// call instructions much less noisy on targets where calls clobber lots
// of registers. Don't rely on MO.isDead() because we may be called before
@@ -1330,6 +1343,24 @@
}
}
+ // Print the regclass of any virtual registers encountered.
+ if (MRI && !VirtRegs.empty()) {
+ if (!HaveSemi) OS << ";"; HaveSemi = true;
+ for (unsigned i = 0; i != VirtRegs.size(); ++i) {
+ const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
+ OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
+ for (unsigned j = i+1; j != VirtRegs.size();) {
+ if (MRI->getRegClass(VirtRegs[j]) != RC) {
+ ++j;
+ continue;
+ }
+ if (VirtRegs[i] != VirtRegs[j])
+ OS << "," << VirtRegs[j];
+ VirtRegs.erase(VirtRegs.begin()+j);
+ }
+ }
+ }
+
if (!debugLoc.isUnknown() && MF) {
if (!HaveSemi) OS << ";";
OS << " dbg:";
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineLICM.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineLICM.cpp Sat Jul 31 19:59:02 2010
@@ -68,7 +68,7 @@
BitVector AllocatableSet;
- // For each opcode, keep a list of potentail CSE instructions.
+ // For each opcode, keep a list of potential CSE instructions.
DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap;
public:
@@ -189,8 +189,8 @@
} // end anonymous namespace
char MachineLICM::ID = 0;
-static RegisterPass<MachineLICM>
-X("machinelicm", "Machine Loop Invariant Code Motion");
+INITIALIZE_PASS(MachineLICM, "machinelicm",
+ "Machine Loop Invariant Code Motion", false, false);
FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) {
return new MachineLICM(PreRegAlloc);
@@ -488,9 +488,14 @@
MII = NextMII;
}
- const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
- for (unsigned I = 0, E = Children.size(); I != E; ++I)
- HoistRegion(Children[I]);
+ // Don't hoist things out of a large switch statement. This often causes
+ // code to be hoisted that wasn't going to be executed, and increases
+ // register pressure in a situation where it's likely to matter.
+ if (BB->succ_size() < 25) {
+ const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
+ for (unsigned I = 0, E = Children.size(); I != E; ++I)
+ HoistRegion(Children[I]);
+ }
}
/// IsLICMCandidate - Returns true if the instruction may be a suitable
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineModuleInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineModuleInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineModuleInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineModuleInfo.cpp Sat Jul 31 19:59:02 2010
@@ -28,8 +28,8 @@
using namespace llvm::dwarf;
// Handle the Pass registration stuff necessary to use TargetData's.
-static RegisterPass<MachineModuleInfo>
-X("machinemoduleinfo", "Machine Module Information");
+INITIALIZE_PASS(MachineModuleInfo, "machinemoduleinfo",
+ "Machine Module Information", false, false);
char MachineModuleInfo::ID = 0;
// Out of line virtual method.
@@ -579,10 +579,3 @@
}
};
}
-
-MachineModuleInfo::VariableDbgInfoMapTy &
-MachineModuleInfo::getVariableDbgInfo() {
- std::stable_sort(VariableDbgInfo.begin(), VariableDbgInfo.end(),
- VariableDebugSorter());
- return VariableDbgInfo;
-}
Modified: llvm/branches/wendling/eh/lib/CodeGen/MachineSink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/MachineSink.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/MachineSink.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/MachineSink.cpp Sat Jul 31 19:59:02 2010
@@ -65,8 +65,8 @@
} // end anonymous namespace
char MachineSinking::ID = 0;
-static RegisterPass<MachineSinking>
-X("machine-sink", "Machine code sinking");
+INITIALIZE_PASS(MachineSinking, "machine-sink",
+ "Machine code sinking", false, false);
FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); }
Modified: llvm/branches/wendling/eh/lib/CodeGen/OptimizeExts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/OptimizeExts.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/OptimizeExts.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/OptimizeExts.cpp Sat Jul 31 19:59:02 2010
@@ -63,8 +63,8 @@
}
char OptimizeExts::ID = 0;
-static RegisterPass<OptimizeExts>
-X("opt-exts", "Optimize sign / zero extensions");
+INITIALIZE_PASS(OptimizeExts, "opt-exts",
+ "Optimize sign / zero extensions", false, false);
FunctionPass *llvm::createOptimizeExtsPass() { return new OptimizeExts(); }
Modified: llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/OptimizePHIs.cpp Sat Jul 31 19:59:02 2010
@@ -54,8 +54,8 @@
}
char OptimizePHIs::ID = 0;
-static RegisterPass<OptimizePHIs>
-X("opt-phis", "Optimize machine instruction PHIs");
+INITIALIZE_PASS(OptimizePHIs, "opt-phis",
+ "Optimize machine instruction PHIs", false, false);
FunctionPass *llvm::createOptimizePHIsPass() { return new OptimizePHIs(); }
@@ -101,16 +101,10 @@
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
// Skip over register-to-register moves.
- unsigned MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx;
- if (SrcMI &&
- TII->isMoveInstr(*SrcMI, MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx) &&
- SrcSubIdx == 0 && DstSubIdx == 0 &&
- TargetRegisterInfo::isVirtualRegister(MvSrcReg))
- SrcMI = MRI->getVRegDef(MvSrcReg);
- else if (SrcMI && SrcMI->isCopy() &&
- !SrcMI->getOperand(0).getSubReg() &&
- !SrcMI->getOperand(1).getSubReg() &&
- TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+ if (SrcMI && SrcMI->isCopy() &&
+ !SrcMI->getOperand(0).getSubReg() &&
+ !SrcMI->getOperand(1).getSubReg() &&
+ TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
if (!SrcMI)
return false;
Modified: llvm/branches/wendling/eh/lib/CodeGen/PBQP/Heuristics/Briggs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PBQP/Heuristics/Briggs.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PBQP/Heuristics/Briggs.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PBQP/Heuristics/Briggs.h Sat Jul 31 19:59:02 2010
@@ -52,9 +52,7 @@
bool operator()(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr) const {
if (s->getSolverDegree(n1Itr) > s->getSolverDegree(n2Itr))
return true;
- if (s->getSolverDegree(n1Itr) < s->getSolverDegree(n2Itr))
- return false;
- return (&*n1Itr < &*n2Itr);
+ return false;
}
private:
HeuristicSolverImpl<Briggs> *s;
@@ -69,9 +67,7 @@
cost2 = g->getNodeCosts(n2Itr)[0] / s->getSolverDegree(n2Itr);
if (cost1 < cost2)
return true;
- if (cost1 > cost2)
- return false;
- return (&*n1Itr < &*n2Itr);
+ return false;
}
private:
Modified: llvm/branches/wendling/eh/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PostRASchedulerList.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PostRASchedulerList.cpp Sat Jul 31 19:59:02 2010
@@ -130,7 +130,7 @@
/// KillIndices - The index of the most recent kill (proceding bottom-up),
/// or ~0u if the register is not live.
- unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<unsigned> KillIndices;
public:
SchedulePostRATDList(MachineFunction &MF,
@@ -140,7 +140,8 @@
AntiDepBreaker *ADB,
AliasAnalysis *aa)
: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
- HazardRec(HR), AntiDepBreak(ADB), AA(aa) {}
+ HazardRec(HR), AntiDepBreak(ADB), AA(aa),
+ KillIndices(TRI->getNumRegs()) {}
~SchedulePostRATDList() {
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PreAllocSplitting.cpp Sat Jul 31 19:59:02 2010
@@ -676,11 +676,7 @@
VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
// If the def is a move, set the copy field.
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- if (DstReg == LI->reg)
- NewVN->setCopy(&*DI);
- } else if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
+ if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
NewVN->setCopy(&*DI);
NewVNs[&*DI] = NewVN;
Modified: llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ProcessImplicitDefs.cpp Sat Jul 31 19:59:02 2010
@@ -26,8 +26,8 @@
using namespace llvm;
char ProcessImplicitDefs::ID = 0;
-static RegisterPass<ProcessImplicitDefs> X("processimpdefs",
- "Process Implicit Definitions.");
+INITIALIZE_PASS(ProcessImplicitDefs, "processimpdefs",
+ "Process Implicit Definitions.", false, false);
void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@@ -46,12 +46,6 @@
unsigned Reg, unsigned OpIdx,
const TargetInstrInfo *tii_,
SmallSet<unsigned, 8> &ImpDefRegs) {
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- Reg == SrcReg &&
- (DstSubReg == 0 || ImpDefRegs.count(DstReg)))
- return true;
-
switch(OpIdx) {
case 1:
return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
@@ -75,14 +69,6 @@
return true;
return false;
}
-
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
- if (Reg != SrcReg)
- return false;
- if (DstSubReg == 0 || ImpDefRegs.count(DstReg))
- return true;
- }
return false;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/PrologEpilogInserter.cpp Sat Jul 31 19:59:02 2010
@@ -33,6 +33,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/STLExtras.h"
#include <climits>
@@ -40,8 +41,8 @@
char PEI::ID = 0;
-static RegisterPass<PEI>
-X("prologepilog", "Prologue/Epilogue Insertion");
+INITIALIZE_PASS(PEI, "prologepilog",
+ "Prologue/Epilogue Insertion", false, false);
/// createPrologEpilogCodeInserter - This function returns a pass that inserts
/// prolog and epilog code, and eliminates abstract frame references.
@@ -549,10 +550,29 @@
// Make sure that the stack protector comes before the local variables on the
// stack.
- if (MFI->getStackProtectorIndex() >= 0)
+ SmallSet<int, 16> LargeStackObjs;
+ if (MFI->getStackProtectorIndex() >= 0) {
AdjustStackOffset(MFI, MFI->getStackProtectorIndex(), StackGrowsDown,
Offset, MaxAlign);
+ // Assign large stack objects first.
+ for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
+ if (i >= MinCSFrameIndex && i <= MaxCSFrameIndex)
+ continue;
+ if (RS && (int)i == RS->getScavengingFrameIndex())
+ continue;
+ if (MFI->isDeadObjectIndex(i))
+ continue;
+ if (MFI->getStackProtectorIndex() == (int)i)
+ continue;
+ if (!MFI->MayNeedStackProtector(i))
+ continue;
+
+ AdjustStackOffset(MFI, i, StackGrowsDown, Offset, MaxAlign);
+ LargeStackObjs.insert(i);
+ }
+ }
+
// Then assign frame offsets to stack objects that are not used to spill
// callee saved registers.
for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
@@ -564,6 +584,8 @@
continue;
if (MFI->getStackProtectorIndex() == (int)i)
continue;
+ if (LargeStackObjs.count(i))
+ continue;
AdjustStackOffset(MFI, i, StackGrowsDown, Offset, MaxAlign);
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegAllocFast.cpp Sat Jul 31 19:59:02 2010
@@ -520,12 +520,9 @@
if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
MRI->hasOneNonDBGUse(VirtReg)) {
const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
// It's a copy, use the destination register as a hint.
if (UseMI.isCopyLike())
Hint = UseMI.getOperand(0).getReg();
- else if (TII->isMoveInstr(UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
- Hint = DstReg;
}
allocVirtReg(MI, *LRI, Hint);
} else if (LR.LastUse) {
@@ -756,31 +753,39 @@
// Debug values are not allowed to change codegen in any way.
if (MI->isDebugValue()) {
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
- if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
- LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
- if (LRI != LiveVirtRegs.end())
- setPhysReg(MI, i, LRI->second.PhysReg);
- else {
- int SS = StackSlotForVirtReg[Reg];
- if (SS == -1)
- MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
+ bool ScanDbgValue = true;
+ while (ScanDbgValue) {
+ ScanDbgValue = false;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (!MO.isReg()) continue;
+ unsigned Reg = MO.getReg();
+ if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+ LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
+ if (LRI != LiveVirtRegs.end())
+ setPhysReg(MI, i, LRI->second.PhysReg);
else {
- // Modify DBG_VALUE now that the value is in a spill slot.
- uint64_t Offset = MI->getOperand(1).getImm();
- const MDNode *MDPtr =
- MI->getOperand(MI->getNumOperands()-1).getMetadata();
- DebugLoc DL = MI->getDebugLoc();
- if (MachineInstr *NewDV =
- TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
- DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
- MachineBasicBlock *MBB = MI->getParent();
- MBB->insert(MBB->erase(MI), NewDV);
- } else
+ int SS = StackSlotForVirtReg[Reg];
+ if (SS == -1)
MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
+ else {
+ // Modify DBG_VALUE now that the value is in a spill slot.
+ uint64_t Offset = MI->getOperand(1).getImm();
+ const MDNode *MDPtr =
+ MI->getOperand(MI->getNumOperands()-1).getMetadata();
+ DebugLoc DL = MI->getDebugLoc();
+ if (MachineInstr *NewDV =
+ TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
+ DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
+ MachineBasicBlock *MBB = MI->getParent();
+ MBB->insert(MBB->erase(MI), NewDV);
+ // Scan NewDV operands from the beginning.
+ MI = NewDV;
+ ScanDbgValue = true;
+ break;
+ } else
+ MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
+ }
}
}
}
@@ -789,14 +794,13 @@
}
// If this is a copy, we may be able to coalesce.
- unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
+ unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
if (MI->isCopy()) {
CopyDst = MI->getOperand(0).getReg();
CopySrc = MI->getOperand(1).getReg();
CopyDstSub = MI->getOperand(0).getSubReg();
CopySrcSub = MI->getOperand(1).getSubReg();
- } else if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
- CopySrc = CopyDst = 0;
+ }
// Track registers used by instruction.
UsedInInstr.reset();
@@ -843,13 +847,18 @@
// operands. If there are also physical defs, these registers must avoid
// both physical defs and uses, making them more constrained than normal
// operands.
+ // Similarly, if there are multiple defs and tied operands, we must make sure
+ // the same register is allocated to uses and defs.
// We didn't detect inline asm tied operands above, so just make this extra
// pass for all inline asm.
if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
- (hasTiedOps && hasPhysDefs)) {
+ (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) {
handleThroughOperands(MI, VirtDead);
// Don't attempt coalescing when we have funny stuff going on.
CopyDst = 0;
+ // Pretend we have early clobbers so the use operands get marked below.
+ // This is not necessary for the common case of a single tied use.
+ hasEarlyClobbers = true;
}
// Second scan.
@@ -870,14 +879,17 @@
MRI->addPhysRegsUsed(UsedInInstr);
- // Track registers defined by instruction - early clobbers at this point.
+ // Track registers defined by instruction - early clobbers and tied uses at
+ // this point.
UsedInInstr.reset();
if (hasEarlyClobbers) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (!MO.isReg() || !MO.isDef()) continue;
+ if (!MO.isReg()) continue;
unsigned Reg = MO.getReg();
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+ // Look for physreg defs and tied uses.
+ if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
UsedInInstr.set(Reg);
for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
UsedInInstr.set(*AS);
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegAllocLinearScan.cpp Sat Jul 31 19:59:02 2010
@@ -127,7 +127,7 @@
BitVector allocatableRegs_;
LiveIntervals* li_;
LiveStacks* ls_;
- const MachineLoopInfo *loopInfo;
+ MachineLoopInfo *loopInfo;
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
@@ -255,9 +255,9 @@
SmallVector<LiveInterval*, 8> &SpillIntervals);
/// attemptTrivialCoalescing - If a simple interval is defined by a copy,
- /// try allocate the definition the same register as the source register
- /// if the register is not defined during live time of the interval. This
- /// eliminate a copy. This is used to coalesce copies which were not
+ /// try to allocate the definition to the same register as the source,
+ /// if the register is not defined during the life time of the interval.
+ /// This eliminates a copy, and is used to coalesce copies which were not
/// coalesced away before allocation either due to dest and src being in
/// different register classes or because the coalescer was overly
/// conservative.
@@ -358,8 +358,8 @@
char RALinScan::ID = 0;
}
-static RegisterPass<RALinScan>
-X("linearscan-regalloc", "Linear Scan Register Allocator");
+INITIALIZE_PASS(RALinScan, "linearscan-regalloc",
+ "Linear Scan Register Allocator", false, false);
void RALinScan::ComputeRelatedRegClasses() {
// First pass, add all reg classes to the union, and determine at least one
@@ -419,20 +419,15 @@
unsigned CandReg;
{
MachineInstr *CopyMI;
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (vni->def != SlotIndex() && vni->isDefAccurate() &&
- (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
- (CopyMI->isCopy() ||
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)))
+ (CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
// Defined by a copy, try to extend SrcReg forward
- CandReg = CopyMI->isCopy() ? CopyMI->getOperand(1).getReg() : SrcReg;
+ CandReg = CopyMI->getOperand(1).getReg();
else if (TrivCoalesceEnds &&
- (CopyMI =
- li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
- cur.reg == SrcReg)
+ (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
+ CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
// Only used by a copy, try to extend DstReg backwards
- CandReg = DstReg;
+ CandReg = CopyMI->getOperand(0).getReg();
else
return Reg;
}
@@ -488,7 +483,7 @@
vrm_ = &getAnalysis<VirtRegMap>();
if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
- spiller_.reset(createSpiller(mf_, li_, loopInfo, vrm_));
+ spiller_.reset(createSpiller(*this, *mf_, *vrm_));
initIntervalSets();
@@ -804,7 +799,7 @@
static
float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
MachineRegisterInfo *mri_,
- const MachineLoopInfo *loopInfo) {
+ MachineLoopInfo *loopInfo) {
float Conflicts = 0;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
E = mri_->reg_end(); I != E; ++I) {
@@ -978,27 +973,10 @@
if ((vni->def != SlotIndex()) && !vni->isUnused() &&
vni->isDefAccurate()) {
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
- unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
- if (CopyMI &&
- tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
- unsigned Reg = 0;
- if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
- Reg = SrcReg;
- else if (vrm_->isAssignedReg(SrcReg))
- Reg = vrm_->getPhys(SrcReg);
- if (Reg) {
- if (SrcSubReg)
- Reg = tri_->getSubReg(Reg, SrcSubReg);
- if (DstSubReg)
- Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
- if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
- mri_->setRegAllocationHint(cur->reg, 0, Reg);
- }
- } else if (CopyMI && CopyMI->isCopy()) {
- DstReg = CopyMI->getOperand(0).getReg();
- DstSubReg = CopyMI->getOperand(0).getSubReg();
- SrcReg = CopyMI->getOperand(1).getReg();
- SrcSubReg = CopyMI->getOperand(1).getSubReg();
+ if (CopyMI && CopyMI->isCopy()) {
+ unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
+ unsigned SrcReg = CopyMI->getOperand(1).getReg();
+ unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
unsigned Reg = 0;
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegAllocPBQP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegAllocPBQP.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegAllocPBQP.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegAllocPBQP.cpp Sat Jul 31 19:59:02 2010
@@ -34,6 +34,8 @@
#include "PBQP/HeuristicSolver.h"
#include "PBQP/Graph.h"
#include "PBQP/Heuristics/Briggs.h"
+#include "RenderMachineFunction.h"
+#include "Splitter.h"
#include "VirtRegMap.h"
#include "VirtRegRewriter.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
@@ -65,6 +67,11 @@
cl::desc("Attempt coalescing during PBQP register allocation."),
cl::init(false), cl::Hidden);
+static cl::opt<bool>
+pbqpPreSplitting("pbqp-pre-splitting",
+ cl::desc("Pre-splite before PBQP register allocation."),
+ cl::init(false), cl::Hidden);
+
namespace {
///
@@ -96,7 +103,10 @@
au.addPreserved<LiveStacks>();
au.addRequired<MachineLoopInfo>();
au.addPreserved<MachineLoopInfo>();
+ if (pbqpPreSplitting)
+ au.addRequired<LoopSplitter>();
au.addRequired<VirtRegMap>();
+ au.addRequired<RenderMachineFunction>();
MachineFunctionPass::getAnalysisUsage(au);
}
@@ -104,7 +114,15 @@
virtual bool runOnMachineFunction(MachineFunction &MF);
private:
- typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
+
+ class LIOrdering {
+ public:
+ bool operator()(const LiveInterval *li1, const LiveInterval *li2) const {
+ return li1->reg < li2->reg;
+ }
+ };
+
+ typedef std::map<const LiveInterval*, unsigned, LIOrdering> LI2NodeMap;
typedef std::vector<const LiveInterval*> Node2LIMap;
typedef std::vector<unsigned> AllowedSet;
typedef std::vector<AllowedSet> AllowedSetMap;
@@ -112,7 +130,7 @@
typedef std::pair<unsigned, unsigned> RegPair;
typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
- typedef std::set<LiveInterval*> LiveIntervalSet;
+ typedef std::set<LiveInterval*, LIOrdering> LiveIntervalSet;
typedef std::vector<PBQP::Graph::NodeItr> NodeVector;
@@ -379,12 +397,14 @@
iItr != iEnd; ++iItr) {
const MachineInstr *instr = &*iItr;
- unsigned srcReg, dstReg, srcSubReg, dstSubReg;
// If this isn't a copy then continue to the next instruction.
- if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
+ if (!instr->isCopy())
continue;
+ unsigned srcReg = instr->getOperand(1).getReg();
+ unsigned dstReg = instr->getOperand(0).getReg();
+
// If the registers are already the same our job is nice and easy.
if (dstReg == srcReg)
continue;
@@ -845,9 +865,11 @@
lis = &getAnalysis<LiveIntervals>();
lss = &getAnalysis<LiveStacks>();
loopInfo = &getAnalysis<MachineLoopInfo>();
+ RenderMachineFunction *rmf = &getAnalysis<RenderMachineFunction>();
vrm = &getAnalysis<VirtRegMap>();
+
DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n");
// Allocator main loop:
@@ -884,6 +906,8 @@
// Finalise allocation, allocate empty ranges.
finalizeAlloc();
+ rmf->renderMachineFunction("After PBQP register allocation.", vrm);
+
vregIntervalsToAlloc.clear();
emptyVRegIntervals.clear();
li2Node.clear();
Modified: llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/RegisterCoalescer.cpp Sat Jul 31 19:59:02 2010
@@ -54,9 +54,8 @@
DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
Src = MI->getOperand(2).getReg();
SrcSub = MI->getOperand(2).getSubReg();
- } else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) {
+ } else
return false;
- }
return true;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.cpp Sat Jul 31 19:59:02 2010
@@ -32,7 +32,8 @@
ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
const MachineLoopInfo &mli,
const MachineDominatorTree &mdt)
- : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {
+ : ScheduleDAG(mf), MLI(mli), MDT(mdt), Defs(TRI->getNumRegs()),
+ Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) {
MFI = mf.getFrameInfo();
DbgValueVec.clear();
}
@@ -159,8 +160,9 @@
std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
// Keep track of dangling debug references to registers.
- std::pair<MachineInstr*, unsigned>
- DanglingDebugValue[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<std::pair<MachineInstr*, unsigned> >
+ DanglingDebugValue(TRI->getNumRegs(),
+ std::make_pair(static_cast<MachineInstr*>(0), 0));
// Check to see if the scheduler cares about latencies.
bool UnitLatencies = ForceUnitLatencies();
@@ -172,7 +174,6 @@
// Remove any stale debug info; sometimes BuildSchedGraph is called again
// without emitting the info from the previous call.
DbgValueVec.clear();
- std::memset(DanglingDebugValue, 0, sizeof(DanglingDebugValue));
// Walk the list of instructions, from bottom moving up.
for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
Modified: llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/ScheduleDAGInstrs.h Sat Jul 31 19:59:02 2010
@@ -106,8 +106,8 @@
/// are as we iterate upward through the instructions. This is allocated
/// here instead of inside BuildSchedGraph to avoid the need for it to be
/// initialized and destructed for each block.
- std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister];
- std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister];
+ std::vector<std::vector<SUnit *> > Defs;
+ std::vector<std::vector<SUnit *> > Uses;
/// DbgValueVec - Remember DBG_VALUEs that refer to a particular
/// register.
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jul 31 19:59:02 2010
@@ -4489,6 +4489,16 @@
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP<->INT cases.
if (SrcBitSize == DstBitSize) {
+ EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
+ BV->getValueType(0).getVectorNumElements());
+
+ // Due to the FP element handling below calling this routine recursively,
+ // we can end up with a scalar-to-vector node here.
+ if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
+ return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
+ DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
+ DstEltVT, BV->getOperand(0)));
+
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
SDValue Op = BV->getOperand(i);
@@ -4500,8 +4510,6 @@
DstEltVT, Op));
AddToWorkList(Ops.back().getNode());
}
- EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
- BV->getValueType(0).getVectorNumElements());
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FastISel.cpp Sat Jul 31 19:59:02 2010
@@ -94,7 +94,7 @@
!(I->getOpcode() == Instruction::BitCast ||
I->getOpcode() == Instruction::PtrToInt ||
I->getOpcode() == Instruction::IntToPtr) &&
- cast<Instruction>(I->use_begin())->getParent() == I->getParent();
+ cast<Instruction>(*I->use_begin())->getParent() == I->getParent();
}
unsigned FastISel::getRegForValue(const Value *V) {
@@ -276,6 +276,7 @@
void FastISel::recomputeInsertPt() {
if (getLastLocalValue()) {
FuncInfo.InsertPt = getLastLocalValue();
+ FuncInfo.MBB = FuncInfo.InsertPt->getParent();
++FuncInfo.InsertPt;
} else
FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
@@ -472,17 +473,7 @@
return true;
const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
// Don't handle byval struct arguments or VLAs, for example.
- // Note that if we have a byval struct argument, fast ISel is turned off;
- // those are handled in SelectionDAGBuilder.
- if (AI) {
- DenseMap<const AllocaInst*, int>::iterator SI =
- FuncInfo.StaticAllocaMap.find(AI);
- if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs.
- int FI = SI->second;
- if (!DI->getDebugLoc().isUnknown())
- FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(),
- FI, DI->getDebugLoc());
- } else
+ if (!AI)
// Building the map above is target independent. Generating DBG_VALUE
// inline is target dependent; do this now.
(void)TargetSelectInstruction(cast<Instruction>(I));
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Sat Jul 31 19:59:02 2010
@@ -20,6 +20,7 @@
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
+#include "llvm/Analysis/DebugInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -111,17 +112,56 @@
TySize *= CUI->getZExtValue(); // Get total allocated size.
if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
+
+ // The object may need to be placed onto the stack near the stack
+ // protector if one exists. Determine here if this object is a suitable
+ // candidate. I.e., it would trigger the creation of a stack protector.
+ bool MayNeedSP =
+ (AI->isArrayAllocation() ||
+ (TySize > 8 && isa<ArrayType>(Ty) &&
+ cast<ArrayType>(Ty)->getElementType()->isIntegerTy(8)));
StaticAllocaMap[AI] =
- MF->getFrameInfo()->CreateStackObject(TySize, Align, false);
+ MF->getFrameInfo()->CreateStackObject(TySize, Align, false, MayNeedSP);
}
for (; BB != EB; ++BB)
- for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
+ for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
+ // Mark values used outside their block as exported, by allocating
+ // a virtual register for them.
if (isUsedOutsideOfDefiningBlock(I))
if (!isa<AllocaInst>(I) ||
!StaticAllocaMap.count(cast<AllocaInst>(I)))
InitializeRegForValue(I);
+ // Collect llvm.dbg.declare information. This is done now instead of
+ // during the initial isel pass through the IR so that it is done
+ // in a predictable order.
+ if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
+ MachineModuleInfo &MMI = MF->getMMI();
+ if (MMI.hasDebugInfo() &&
+ DIVariable(DI->getVariable()).Verify() &&
+ !DI->getDebugLoc().isUnknown()) {
+ // Don't handle byval struct arguments or VLAs, for example.
+ // Non-byval arguments are handled here (they refer to the stack
+ // temporary alloca at this point).
+ const Value *Address = DI->getAddress();
+ if (Address) {
+ if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
+ Address = BCI->getOperand(0);
+ if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
+ DenseMap<const AllocaInst *, int>::iterator SI =
+ StaticAllocaMap.find(AI);
+ if (SI != StaticAllocaMap.end()) { // Check for VLAs.
+ int FI = SI->second;
+ MMI.setVariableDbgInfo(DI->getVariable(),
+ FI, DI->getDebugLoc());
+ }
+ }
+ }
+ }
+ }
+ }
+
// Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
// also creates the initial PHI MachineInstrs, though none of the input
// operands are populated.
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sat Jul 31 19:59:02 2010
@@ -234,8 +234,9 @@
// The pair element type may be legal, or may not promote to the same type as
// the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
- TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
- JoinIntegers(N->getOperand(0), N->getOperand(1)));
+ TLI.getTypeToTransformTo(*DAG.getContext(),
+ N->getValueType(0)), JoinIntegers(N->getOperand(0),
+ N->getOperand(1)));
}
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
@@ -245,7 +246,8 @@
// Zero extend things like i1, sign extend everything else. It shouldn't
// matter in theory which one we pick, but this tends to give better code?
unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
- SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
+ SDValue Result = DAG.getNode(Opc, dl,
+ TLI.getTypeToTransformTo(*DAG.getContext(), VT),
SDValue(N, 0));
assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
return Result;
@@ -310,8 +312,8 @@
// If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
// not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
- // and SINT conversions are Custom, there is no way to tell which is preferable.
- // We choose SINT because that's the right thing on PPC.)
+ // and SINT conversions are Custom, there is no way to tell which is
+ // preferable. We choose SINT because that's the right thing on PPC.)
if (N->getOpcode() == ISD::FP_TO_UINT &&
!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
@@ -1030,7 +1032,7 @@
Hi = InL;
} else if (Amt == 1 &&
TLI.isOperationLegalOrCustom(ISD::ADDC,
- TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
+ TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
// Emit this X << 1 as X+X.
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
SDValue LoOps[2] = { InL, InL };
@@ -1926,7 +1928,8 @@
unsigned ExcessBits =
EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
- DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
+ DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
+ ExcessBits)));
}
}
@@ -2046,7 +2049,8 @@
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getZeroExtendInReg(Hi, dl,
- EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
+ EVT::getIntegerVT(*DAG.getContext(),
+ ExcessBits));
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Sat Jul 31 19:59:02 2010
@@ -24,6 +24,7 @@
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetLowering.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
@@ -54,10 +55,16 @@
static RegisterScheduler
hybridListDAGScheduler("list-hybrid",
- "Bottom-up rr list scheduling which avoid stalls for "
- "long latency instructions",
+ "Bottom-up register pressure aware list scheduling "
+ "which tries to balance latency and register pressure",
createHybridListDAGScheduler);
+static RegisterScheduler
+ ILPListDAGScheduler("list-ilp",
+ "Bottom-up register pressure aware list scheduling "
+ "which tries to balance ILP and register pressure",
+ createILPListDAGScheduler);
+
namespace {
//===----------------------------------------------------------------------===//
/// ScheduleDAGRRList - The actual register reduction list scheduler
@@ -181,7 +188,9 @@
/// Schedule - Schedule the DAG using list scheduling.
void ScheduleDAGRRList::Schedule() {
- DEBUG(dbgs() << "********** List Scheduling **********\n");
+ DEBUG(dbgs()
+ << "********** List Scheduling BB#" << BB->getNumber()
+ << " **********\n");
NumLiveRegs = 0;
LiveRegDefs.resize(TRI->getNumRegs(), NULL);
@@ -273,6 +282,8 @@
SU->setHeightToAtLeast(CurCycle);
Sequence.push_back(SU);
+ AvailableQueue->ScheduledNode(SU);
+
ReleasePredecessors(SU, CurCycle);
// Release all the implicit physical register defs that are live.
@@ -291,7 +302,6 @@
}
SU->isScheduled = true;
- AvailableQueue->ScheduledNode(SU);
}
/// CapturePred - This does the opposite of ReleasePred. Since SU is being
@@ -315,8 +325,6 @@
DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: ");
DEBUG(SU->dump(this));
- AvailableQueue->UnscheduledNode(SU);
-
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) {
CapturePred(&*I);
@@ -346,6 +354,7 @@
SU->isScheduled = false;
SU->isAvailable = true;
AvailableQueue->push(SU);
+ AvailableQueue->UnscheduledNode(SU);
}
/// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
@@ -956,7 +965,8 @@
template<class SF>
class RegReductionPriorityQueue;
- /// Sorting functions for the Available queue.
+ /// bu_ls_rr_sort - Priority function for bottom up register pressure
+ // reduction scheduler.
struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
@@ -965,6 +975,8 @@
bool operator()(const SUnit* left, const SUnit* right) const;
};
+ // td_ls_rr_sort - Priority function for top down register pressure reduction
+ // scheduler.
struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
@@ -973,6 +985,7 @@
bool operator()(const SUnit* left, const SUnit* right) const;
};
+ // src_ls_rr_sort - Priority function for source order scheduler.
struct src_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
RegReductionPriorityQueue<src_ls_rr_sort> *SPQ;
src_ls_rr_sort(RegReductionPriorityQueue<src_ls_rr_sort> *spq)
@@ -983,13 +996,26 @@
bool operator()(const SUnit* left, const SUnit* right) const;
};
+ // hybrid_ls_rr_sort - Priority function for hybrid scheduler.
struct hybrid_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
RegReductionPriorityQueue<hybrid_ls_rr_sort> *SPQ;
hybrid_ls_rr_sort(RegReductionPriorityQueue<hybrid_ls_rr_sort> *spq)
: SPQ(spq) {}
hybrid_ls_rr_sort(const hybrid_ls_rr_sort &RHS)
: SPQ(RHS.SPQ) {}
-
+
+ bool operator()(const SUnit* left, const SUnit* right) const;
+ };
+
+ // ilp_ls_rr_sort - Priority function for ILP (instruction level parallelism)
+ // scheduler.
+ struct ilp_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
+ RegReductionPriorityQueue<ilp_ls_rr_sort> *SPQ;
+ ilp_ls_rr_sort(RegReductionPriorityQueue<ilp_ls_rr_sort> *spq)
+ : SPQ(spq) {}
+ ilp_ls_rr_sort(const ilp_ls_rr_sort &RHS)
+ : SPQ(RHS.SPQ) {}
+
bool operator()(const SUnit* left, const SUnit* right) const;
};
} // end anonymous namespace
@@ -1029,23 +1055,48 @@
std::vector<SUnit*> Queue;
SF Picker;
unsigned CurQueueId;
+ bool TracksRegPressure;
protected:
// SUnits - The SUnits for the current graph.
std::vector<SUnit> *SUnits;
-
+
+ MachineFunction &MF;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
+ const TargetLowering *TLI;
ScheduleDAGRRList *scheduleDAG;
// SethiUllmanNumbers - The SethiUllman number for each node.
std::vector<unsigned> SethiUllmanNumbers;
+ /// RegPressure - Tracking current reg pressure per register class.
+ ///
+ std::vector<unsigned> RegPressure;
+
+ /// RegLimit - Tracking the number of allocatable registers per register
+ /// class.
+ std::vector<unsigned> RegLimit;
+
public:
- RegReductionPriorityQueue(const TargetInstrInfo *tii,
- const TargetRegisterInfo *tri)
- : Picker(this), CurQueueId(0),
- TII(tii), TRI(tri), scheduleDAG(NULL) {}
+ RegReductionPriorityQueue(MachineFunction &mf,
+ bool tracksrp,
+ const TargetInstrInfo *tii,
+ const TargetRegisterInfo *tri,
+ const TargetLowering *tli)
+ : Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
+ MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
+ if (TracksRegPressure) {
+ unsigned NumRC = TRI->getNumRegClasses();
+ RegLimit.resize(NumRC);
+ RegPressure.resize(NumRC);
+ std::fill(RegLimit.begin(), RegLimit.end(), 0);
+ std::fill(RegPressure.begin(), RegPressure.end(), 0);
+ for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+ E = TRI->regclass_end(); I != E; ++I)
+ RegLimit[(*I)->getID()] = tli->getRegPressureLimit(*I, MF);
+ }
+ }
void initNodes(std::vector<SUnit> &sunits) {
SUnits = &sunits;
@@ -1072,6 +1123,7 @@
void releaseState() {
SUnits = 0;
SethiUllmanNumbers.clear();
+ std::fill(RegPressure.begin(), RegPressure.end(), 0);
}
unsigned getNodePriority(const SUnit *SU) const {
@@ -1139,10 +1191,244 @@
SU->NodeQueueId = 0;
}
+ bool HighRegPressure(const SUnit *SU) const {
+ if (!TLI)
+ return false;
+
+ for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl())
+ continue;
+ SUnit *PredSU = I->getSUnit();
+ const SDNode *PN = PredSU->getNode();
+ if (!PN->isMachineOpcode()) {
+ if (PN->getOpcode() == ISD::CopyFromReg) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ unsigned Cost = TLI->getRepRegClassCostFor(VT);
+ if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
+ return true;
+ }
+ continue;
+ }
+ unsigned POpc = PN->getMachineOpcode();
+ if (POpc == TargetOpcode::IMPLICIT_DEF)
+ continue;
+ if (POpc == TargetOpcode::EXTRACT_SUBREG) {
+ EVT VT = PN->getOperand(0).getValueType();
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ unsigned Cost = TLI->getRepRegClassCostFor(VT);
+ // Check if this increases register pressure of the specific register
+ // class to the point where it would cause spills.
+ if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
+ return true;
+ continue;
+ } else if (POpc == TargetOpcode::INSERT_SUBREG ||
+ POpc == TargetOpcode::SUBREG_TO_REG) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ unsigned Cost = TLI->getRepRegClassCostFor(VT);
+ // Check if this increases register pressure of the specific register
+ // class to the point where it would cause spills.
+ if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
+ return true;
+ continue;
+ }
+ unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
+ for (unsigned i = 0; i != NumDefs; ++i) {
+ EVT VT = PN->getValueType(i);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ if (RegPressure[RCId] >= RegLimit[RCId])
+ return true; // Reg pressure already high.
+ unsigned Cost = TLI->getRepRegClassCostFor(VT);
+ if (!PN->hasAnyUseOfValue(i))
+ continue;
+ // Check if this increases register pressure of the specific register
+ // class to the point where it would cause spills.
+ if ((RegPressure[RCId] + Cost) >= RegLimit[RCId])
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+ void ScheduledNode(SUnit *SU) {
+ if (!TracksRegPressure)
+ return;
+
+ const SDNode *N = SU->getNode();
+ if (!N->isMachineOpcode()) {
+ if (N->getOpcode() != ISD::CopyToReg)
+ return;
+ } else {
+ unsigned Opc = N->getMachineOpcode();
+ if (Opc == TargetOpcode::EXTRACT_SUBREG ||
+ Opc == TargetOpcode::INSERT_SUBREG ||
+ Opc == TargetOpcode::SUBREG_TO_REG ||
+ Opc == TargetOpcode::REG_SEQUENCE ||
+ Opc == TargetOpcode::IMPLICIT_DEF)
+ return;
+ }
+
+ for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl())
+ continue;
+ SUnit *PredSU = I->getSUnit();
+ if (PredSU->NumSuccsLeft != PredSU->NumSuccs)
+ continue;
+ const SDNode *PN = PredSU->getNode();
+ if (!PN->isMachineOpcode()) {
+ if (PN->getOpcode() == ISD::CopyFromReg) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ }
+ continue;
+ }
+ unsigned POpc = PN->getMachineOpcode();
+ if (POpc == TargetOpcode::IMPLICIT_DEF)
+ continue;
+ if (POpc == TargetOpcode::EXTRACT_SUBREG) {
+ EVT VT = PN->getOperand(0).getValueType();
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ continue;
+ } else if (POpc == TargetOpcode::INSERT_SUBREG ||
+ POpc == TargetOpcode::SUBREG_TO_REG) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ continue;
+ }
+ unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
+ for (unsigned i = 0; i != NumDefs; ++i) {
+ EVT VT = PN->getValueType(i);
+ if (!PN->hasAnyUseOfValue(i))
+ continue;
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ }
+ }
+
+ // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
+ // may transfer data dependencies to CopyToReg.
+ if (SU->NumSuccs && N->isMachineOpcode()) {
+ unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
+ for (unsigned i = 0; i != NumDefs; ++i) {
+ EVT VT = N->getValueType(i);
+ if (!N->hasAnyUseOfValue(i))
+ continue;
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
+ // Register pressure tracking is imprecise. This can happen.
+ RegPressure[RCId] = 0;
+ else
+ RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
+ }
+ }
+
+ dumpRegPressure();
+ }
+
+ void UnscheduledNode(SUnit *SU) {
+ if (!TracksRegPressure)
+ return;
+
+ const SDNode *N = SU->getNode();
+ if (!N->isMachineOpcode()) {
+ if (N->getOpcode() != ISD::CopyToReg)
+ return;
+ } else {
+ unsigned Opc = N->getMachineOpcode();
+ if (Opc == TargetOpcode::EXTRACT_SUBREG ||
+ Opc == TargetOpcode::INSERT_SUBREG ||
+ Opc == TargetOpcode::SUBREG_TO_REG ||
+ Opc == TargetOpcode::REG_SEQUENCE ||
+ Opc == TargetOpcode::IMPLICIT_DEF)
+ return;
+ }
+
+ for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
+ I != E; ++I) {
+ if (I->isCtrl())
+ continue;
+ SUnit *PredSU = I->getSUnit();
+ if (PredSU->NumSuccsLeft != PredSU->NumSuccs)
+ continue;
+ const SDNode *PN = PredSU->getNode();
+ if (!PN->isMachineOpcode()) {
+ if (PN->getOpcode() == ISD::CopyFromReg) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ }
+ continue;
+ }
+ unsigned POpc = PN->getMachineOpcode();
+ if (POpc == TargetOpcode::IMPLICIT_DEF)
+ continue;
+ if (POpc == TargetOpcode::EXTRACT_SUBREG) {
+ EVT VT = PN->getOperand(0).getValueType();
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ continue;
+ } else if (POpc == TargetOpcode::INSERT_SUBREG ||
+ POpc == TargetOpcode::SUBREG_TO_REG) {
+ EVT VT = PN->getValueType(0);
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ continue;
+ }
+ unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
+ for (unsigned i = 0; i != NumDefs; ++i) {
+ EVT VT = PN->getValueType(i);
+ if (!PN->hasAnyUseOfValue(i))
+ continue;
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
+ // Register pressure tracking is imprecise. This can happen.
+ RegPressure[RCId] = 0;
+ else
+ RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
+ }
+ }
+
+ // Check for isMachineOpcode() as PrescheduleNodesWithMultipleUses()
+ // may transfer data dependencies to CopyToReg.
+ if (SU->NumSuccs && N->isMachineOpcode()) {
+ unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
+ for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
+ EVT VT = N->getValueType(i);
+ if (VT == MVT::Flag || VT == MVT::Other)
+ continue;
+ if (!N->hasAnyUseOfValue(i))
+ continue;
+ unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
+ RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
+ }
+ }
+
+ dumpRegPressure();
+ }
+
void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
scheduleDAG = scheduleDag;
}
+ void dumpRegPressure() const {
+ for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
+ E = TRI->regclass_end(); I != E; ++I) {
+ const TargetRegisterClass *RC = *I;
+ unsigned Id = RC->getID();
+ unsigned RP = RegPressure[Id];
+ if (!RP) continue;
+ DEBUG(dbgs() << RC->getName() << ": " << RP << " / " << RegLimit[Id]
+ << '\n');
+ }
+ }
+
protected:
bool canClobber(const SUnit *SU, const SUnit *Op);
void AddPseudoTwoAddrDeps();
@@ -1161,6 +1447,9 @@
typedef RegReductionPriorityQueue<hybrid_ls_rr_sort>
HybridBURRPriorityQueue;
+
+ typedef RegReductionPriorityQueue<ilp_ls_rr_sort>
+ ILPBURRPriorityQueue;
}
/// closestSucc - Returns the scheduled cycle of the successor which is
@@ -1260,30 +1549,63 @@
}
bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
- bool LStall = left->SchedulingPref == Sched::Latency &&
- SPQ->getCurCycle() < left->getHeight();
- bool RStall = right->SchedulingPref == Sched::Latency &&
- SPQ->getCurCycle() < right->getHeight();
- // If scheduling one of the node will cause a pipeline stall, delay it.
- // If scheduling either one of the node will cause a pipeline stall, sort them
- // according to their height.
- // If neither will cause a pipeline stall, try to reduce register pressure.
- if (LStall) {
- if (!RStall)
- return true;
- if (left->getHeight() != right->getHeight())
- return left->getHeight() > right->getHeight();
- } else if (RStall)
+ bool LHigh = SPQ->HighRegPressure(left);
+ bool RHigh = SPQ->HighRegPressure(right);
+ // Avoid causing spills. If register pressure is high, schedule for
+ // register pressure reduction.
+ if (LHigh && !RHigh)
+ return true;
+ else if (!LHigh && RHigh)
+ return false;
+ else if (!LHigh && !RHigh) {
+ // Low register pressure situation, schedule for latency if possible.
+ bool LStall = left->SchedulingPref == Sched::Latency &&
+ SPQ->getCurCycle() < left->getHeight();
+ bool RStall = right->SchedulingPref == Sched::Latency &&
+ SPQ->getCurCycle() < right->getHeight();
+ // If scheduling one of the node will cause a pipeline stall, delay it.
+ // If scheduling either one of the node will cause a pipeline stall, sort
+ // them according to their height.
+ // If neither will cause a pipeline stall, try to reduce register pressure.
+ if (LStall) {
+ if (!RStall)
+ return true;
+ if (left->getHeight() != right->getHeight())
+ return left->getHeight() > right->getHeight();
+ } else if (RStall)
return false;
- // If either node is scheduling for latency, sort them by height and latency
- // first.
- if (left->SchedulingPref == Sched::Latency ||
- right->SchedulingPref == Sched::Latency) {
- if (left->getHeight() != right->getHeight())
- return left->getHeight() > right->getHeight();
- if (left->Latency != right->Latency)
- return left->Latency > right->Latency;
+ // If either node is scheduling for latency, sort them by height and latency
+ // first.
+ if (left->SchedulingPref == Sched::Latency ||
+ right->SchedulingPref == Sched::Latency) {
+ if (left->getHeight() != right->getHeight())
+ return left->getHeight() > right->getHeight();
+ if (left->Latency != right->Latency)
+ return left->Latency > right->Latency;
+ }
+ }
+
+ return BURRSort(left, right, SPQ);
+}
+
+bool ilp_ls_rr_sort::operator()(const SUnit *left,
+ const SUnit *right) const {
+ bool LHigh = SPQ->HighRegPressure(left);
+ bool RHigh = SPQ->HighRegPressure(right);
+ // Avoid causing spills. If register pressure is high, schedule for
+ // register pressure reduction.
+ if (LHigh && !RHigh)
+ return true;
+ else if (!LHigh && RHigh)
+ return false;
+ else if (!LHigh && !RHigh) {
+ // Low register pressure situation, schedule to maximize instruction level
+ // parallelism.
+ if (left->NumPreds > right->NumPreds)
+ return false;
+ else if (left->NumPreds < right->NumPreds)
+ return false;
}
return BURRSort(left, right, SPQ);
@@ -1635,8 +1957,8 @@
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
- BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
-
+ BURegReductionPriorityQueue *PQ =
+ new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
@@ -1648,8 +1970,8 @@
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
- TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI);
-
+ TDRegReductionPriorityQueue *PQ =
+ new TDRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, false, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
@@ -1661,8 +1983,8 @@
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
- SrcRegReductionPriorityQueue *PQ = new SrcRegReductionPriorityQueue(TII, TRI);
-
+ SrcRegReductionPriorityQueue *PQ =
+ new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
@@ -1673,9 +1995,24 @@
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ const TargetLowering *TLI = &IS->getTargetLowering();
- HybridBURRPriorityQueue *PQ = new HybridBURRPriorityQueue(TII, TRI);
+ HybridBURRPriorityQueue *PQ =
+ new HybridBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
+ ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
+ PQ->setScheduleDAG(SD);
+ return SD;
+}
+llvm::ScheduleDAGSDNodes *
+llvm::createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
+ const TargetMachine &TM = IS->TM;
+ const TargetInstrInfo *TII = TM.getInstrInfo();
+ const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ const TargetLowering *TLI = &IS->getTargetLowering();
+
+ ILPBURRPriorityQueue *PQ =
+ new ILPBURRPriorityQueue(*IS->MF, true, TII, TRI, TLI);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, true, PQ);
PQ->setScheduleDAG(SD);
return SD;
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jul 31 19:59:02 2010
@@ -2236,7 +2236,7 @@
bool SelectionDAG::isKnownNeverNaN(SDValue Op) const {
// If we're told that NaNs won't happen, assume they won't.
- if (FiniteOnlyFPMath())
+ if (NoNaNsFPMath)
return true;
// If the value is a constant, we can obviously see if it is a NaN or not.
@@ -2624,7 +2624,8 @@
// one big BUILD_VECTOR.
if (N1.getOpcode() == ISD::BUILD_VECTOR &&
N2.getOpcode() == ISD::BUILD_VECTOR) {
- SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
+ SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
+ N1.getNode()->op_end());
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
}
@@ -3021,7 +3022,8 @@
if (N1.getOpcode() == ISD::BUILD_VECTOR &&
N2.getOpcode() == ISD::BUILD_VECTOR &&
N3.getOpcode() == ISD::BUILD_VECTOR) {
- SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
+ SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(),
+ N1.getNode()->op_end());
Elts.append(N2.getNode()->op_begin(), N2.getNode()->op_end());
Elts.append(N3.getNode()->op_begin(), N3.getNode()->op_end());
return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
@@ -5872,6 +5874,7 @@
void SDNode::dump() const { dump(0); }
void SDNode::dump(const SelectionDAG *G) const {
print(dbgs(), G);
+ dbgs() << '\n';
}
void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jul 31 19:59:02 2010
@@ -530,6 +530,10 @@
FunctionLoweringInfo &FuncInfo,
DebugLoc dl,
SDValue &Chain, SDValue *Flag) const {
+ // A Value with type {} or [0 x %t] needs no registers.
+ if (ValueVTs.empty())
+ return SDValue();
+
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// Assemble the legal parts into the final values.
@@ -701,6 +705,7 @@
UnusedArgNodeMap.clear();
PendingLoads.clear();
PendingExports.clear();
+ DanglingDebugInfoMap.clear();
CurDebugLoc = DebugLoc();
HasTailCall = false;
}
@@ -805,6 +810,33 @@
}
}
+// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
+// generate the debug data structures now that we've seen its definition.
+void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
+ SDValue Val) {
+ DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
+ if (DDI.getDI()) {
+ const DbgValueInst *DI = DDI.getDI();
+ DebugLoc dl = DDI.getdl();
+ unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
+ MDNode *Variable = DI->getVariable();
+ uint64_t Offset = DI->getOffset();
+ SDDbgValue *SDV;
+ if (Val.getNode()) {
+ if (!EmitFuncArgumentDbgValue(*DI, V, Variable, Offset, Val)) {
+ SDV = DAG.getDbgValue(Variable, Val.getNode(),
+ Val.getResNo(), Offset, dl, DbgSDNodeOrder);
+ DAG.AddDbgValue(SDV, Val.getNode(), false);
+ }
+ } else {
+ SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
+ Offset, dl, SDNodeOrder);
+ DAG.AddDbgValue(SDV, 0, false);
+ }
+ DanglingDebugInfoMap[V] = DanglingDebugInfo();
+ }
+}
+
// getValue - Return an SDValue for the given Value.
SDValue SelectionDAGBuilder::getValue(const Value *V) {
// If we already have an SDValue for this value, use it. It's important
@@ -826,6 +858,7 @@
// Otherwise create a new SDValue and remember it.
SDValue Val = getValueImpl(V);
NodeMap[V] = Val;
+ resolveDanglingDebugInfo(V, Val);
return Val;
}
@@ -839,10 +872,11 @@
// Otherwise create a new SDValue and remember it.
SDValue Val = getValueImpl(V);
NodeMap[V] = Val;
+ resolveDanglingDebugInfo(V, Val);
return Val;
}
-/// getValueImpl - Helper function for getValue and getMaterializedValue.
+/// getValueImpl - Helper function for getValue and getNonRegisterValue.
/// Create an SDValue for the given value.
SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
if (const Constant *C = dyn_cast<Constant>(V)) {
@@ -2824,7 +2858,7 @@
// Inform the Frame Information that we have just allocated a variable-sized
// object.
- FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
+ FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
}
void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
@@ -3985,20 +4019,6 @@
if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
Address = BCI->getOperand(0);
const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
- if (AI) {
- // Don't handle byval arguments or VLAs, for example.
- // Non-byval arguments are handled here (they refer to the stack temporary
- // alloca at this point).
- DenseMap<const AllocaInst*, int>::iterator SI =
- FuncInfo.StaticAllocaMap.find(AI);
- if (SI == FuncInfo.StaticAllocaMap.end())
- return 0; // VLAs.
- int FI = SI->second;
-
- MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
- if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
- MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
- }
// Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
// but do not always have a corresponding SDNode built. The SDNodeOrder
@@ -4055,7 +4075,8 @@
DAG.AddDbgValue(SDV, 0, false);
} else {
bool createUndef = false;
- // FIXME : Why not use getValue() directly ?
+ // Do not use getValue() in here; we don't want to generate code at
+ // this point if it hasn't been done yet.
SDValue N = NodeMap[V];
if (!N.getNode() && isa<Argument>(V))
// Check unused arguments map.
@@ -4066,16 +4087,11 @@
N.getResNo(), Offset, dl, SDNodeOrder);
DAG.AddDbgValue(SDV, N.getNode(), false);
}
- } else if (isa<PHINode>(V) && !V->use_empty()) {
- SDValue N = getValue(V);
- if (N.getNode()) {
- if (!EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N)) {
- SDV = DAG.getDbgValue(Variable, N.getNode(),
- N.getResNo(), Offset, dl, SDNodeOrder);
- DAG.AddDbgValue(SDV, N.getNode(), false);
- }
- } else
- createUndef = true;
+ } else if (isa<PHINode>(V) && !V->use_empty() ) {
+ // Do not call getValue(V) yet, as we don't want to generate code.
+ // Remember it for later.
+ DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
+ DanglingDebugInfoMap[V] = DDI;
} else
createUndef = true;
if (createUndef) {
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Sat Jul 31 19:59:02 2010
@@ -64,6 +64,7 @@
class PtrToIntInst;
class ReturnInst;
class SDISelAsmOperandInfo;
+class SDDbgValue;
class SExtInst;
class SelectInst;
class ShuffleVectorInst;
@@ -93,6 +94,24 @@
/// to preserve debug information for incoming arguments.
DenseMap<const Value*, SDValue> UnusedArgNodeMap;
+ /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
+ class DanglingDebugInfo {
+ const DbgValueInst* DI;
+ DebugLoc dl;
+ unsigned SDNodeOrder;
+ public:
+ DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
+ DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
+ DI(di), dl(DL), SDNodeOrder(SDNO) { }
+ const DbgValueInst* getDI() { return DI; }
+ DebugLoc getdl() { return dl; }
+ unsigned getSDNodeOrder() { return SDNodeOrder; }
+ };
+
+ /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
+ /// yet seen the referent. We defer handling these until we do see it.
+ DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
+
public:
/// PendingLoads - Loads are not emitted to the program immediately. We bunch
/// them up and then emit token factor nodes when possible. This allows us to
@@ -345,6 +364,9 @@
void visit(unsigned Opcode, const User &I);
+ // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
+ // generate the debug data structures now that we've seen its definition.
+ void resolveDanglingDebugInfo(const Value *V, SDValue Val);
SDValue getValue(const Value *V);
SDValue getNonRegisterValue(const Value *V);
SDValue getValueImpl(const Value *V);
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Jul 31 19:59:02 2010
@@ -132,14 +132,16 @@
const TargetLowering &TLI = IS->getTargetLowering();
if (OptLevel == CodeGenOpt::None)
- return createFastDAGScheduler(IS, OptLevel);
+ return createSourceListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::Latency)
return createTDListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::RegPressure)
return createBURRListDAGScheduler(IS, OptLevel);
- assert(TLI.getSchedulingPreference() == Sched::Hybrid &&
+ if (TLI.getSchedulingPreference() == Sched::Hybrid)
+ return createHybridListDAGScheduler(IS, OptLevel);
+ assert(TLI.getSchedulingPreference() == Sched::ILP &&
"Unknown sched type!");
- return createHybridListDAGScheduler(IS, OptLevel);
+ return createILPListDAGScheduler(IS, OptLevel);
}
}
@@ -216,7 +218,7 @@
for (Value::const_use_iterator
I = Callee->use_begin(), E = Callee->use_end();
I != E; ++I)
- if (const CallInst *CI = dyn_cast<CallInst>(I))
+ if (const CallInst *CI = dyn_cast<CallInst>(*I))
if (CI->getParent()->getParent() == F)
return true;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jul 31 19:59:02 2010
@@ -651,6 +651,52 @@
return NumVectorRegs;
}
+/// isLegalRC - Return true if the value types that can be represented by the
+/// specified register class are all legal.
+bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
+ for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
+ I != E; ++I) {
+ if (isTypeLegal(*I))
+ return true;
+ }
+ return false;
+}
+
+/// hasLegalSuperRegRegClasses - Return true if the specified register class
+/// has one or more super-reg register classes that are legal.
+bool
+TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
+ if (*RC->superregclasses_begin() == 0)
+ return false;
+ for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
+ E = RC->superregclasses_end(); I != E; ++I) {
+ const TargetRegisterClass *RRC = *I;
+ if (isLegalRC(RRC))
+ return true;
+ }
+ return false;
+}
+
+/// findRepresentativeClass - Return the largest legal super-reg register class
+/// of the register class for the specified type and its associated "cost".
+std::pair<const TargetRegisterClass*, uint8_t>
+TargetLowering::findRepresentativeClass(EVT VT) const {
+ const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
+ if (!RC)
+ return std::make_pair(RC, 0);
+ const TargetRegisterClass *BestRC = RC;
+ for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
+ E = RC->superregclasses_end(); I != E; ++I) {
+ const TargetRegisterClass *RRC = *I;
+ if (RRC->isASubClass() || !isLegalRC(RRC))
+ continue;
+ if (!hasLegalSuperRegRegClasses(RRC))
+ return std::make_pair(RRC, 1);
+ BestRC = RRC;
+ }
+ return std::make_pair(BestRC, 1);
+}
+
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
@@ -770,6 +816,19 @@
}
}
}
+
+ // Determine the 'representative' register class for each value type.
+ // An representative register class is the largest (meaning one which is
+ // not a sub-register class / subreg register class) legal register class for
+ // a group of value types. For example, on i386, i8, i16, and i32
+ // representative would be GR32; while on x86_64 it's GR64.
+ for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
+ const TargetRegisterClass* RRC;
+ uint8_t Cost;
+ tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
+ RepRegClassForVT[i] = RRC;
+ RepRegClassCostForVT[i] = Cost;
+ }
}
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -1308,9 +1367,32 @@
}
}
- if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
+ if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
KnownZero, KnownOne, TLO, Depth+1))
return true;
+
+ // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
+ // are not demanded. This will likely allow the anyext to be folded away.
+ if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
+ SDValue InnerOp = InOp.getNode()->getOperand(0);
+ EVT InnerVT = InnerOp.getValueType();
+ if ((APInt::getHighBitsSet(BitWidth,
+ BitWidth - InnerVT.getSizeInBits()) &
+ DemandedMask) == 0 &&
+ isTypeDesirableForOp(ISD::SHL, InnerVT)) {
+ EVT ShTy = getShiftAmountTy();
+ if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
+ ShTy = InnerVT;
+ SDValue NarrowShl =
+ TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
+ TLO.DAG.getConstant(ShAmt, ShTy));
+ return
+ TLO.CombineTo(Op,
+ TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
+ NarrowShl));
+ }
+ }
+
KnownZero <<= SA->getZExtValue();
KnownOne <<= SA->getZExtValue();
// low bits known zero.
@@ -1886,12 +1968,9 @@
EVT ExtDstTy = N0.getValueType();
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
- // If the extended part has any inconsistent bits, it cannot ever
- // compare equal. In other words, they have to be all ones or all
- // zeros.
- APInt ExtBits =
- APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
- if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
+ // If the constant doesn't fit into the number of bits for the source of
+ // the sign extension, it is impossible for both sides to be equal.
+ if (C1.getMinSignedBits() > ExtSrcTyBits)
return DAG.getConstant(Cond == ISD::SETNE, VT);
SDValue ZextOp;
@@ -2476,7 +2555,7 @@
int64_t Offs = GA->getOffset();
if (C) Offs += C->getZExtValue();
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
- C->getDebugLoc(),
+ C ? C->getDebugLoc() : DebugLoc(),
Op.getValueType(), Offs));
return;
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SimpleRegisterCoalescing.cpp Sat Jul 31 19:59:02 2010
@@ -470,16 +470,12 @@
if (Extended)
UseMO.setIsKill(false);
}
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (UseMI->isCopy()) {
- if (UseMI->getOperand(0).getReg() != IntB.reg ||
- UseMI->getOperand(0).getSubReg())
- continue;
- } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
- if (DstReg != IntB.reg || DstSubIdx)
- continue;
- } else
+ if (!UseMI->isCopy())
+ continue;
+ if (UseMI->getOperand(0).getReg() != IntB.reg ||
+ UseMI->getOperand(0).getSubReg())
continue;
+
// This copy will become a noop. If it's defining a new val#,
// remove that val# as well. However this live range is being
// extended to the end of the existing live range defined by the copy.
@@ -628,14 +624,6 @@
if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
DefMO.setIsDead();
}
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- DstReg == li.reg && DstSubIdx == 0) {
- // Last use is itself an identity code.
- int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
- false, false, tri_);
- LastUseMI->getOperand(DeadIdx).setIsDead();
- }
return true;
}
@@ -772,16 +760,6 @@
// A PhysReg copy that won't be coalesced can perhaps be rematerialized
// instead.
if (DstIsPhys) {
- unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
- if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
- CopySrcSubIdx, CopyDstSubIdx) &&
- CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
- CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
- CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
- ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
- UseMI))
- continue;
-
if (UseMI->isCopy() &&
!UseMI->getOperand(1).getSubReg() &&
!UseMI->getOperand(0).getSubReg() &&
@@ -834,28 +812,6 @@
dbgs() << li_->getInstructionIndex(UseMI) << "\t";
dbgs() << *UseMI;
});
-
-
- // After updating the operand, check if the machine instruction has
- // become a copy. If so, update its val# information.
- const TargetInstrDesc &TID = UseMI->getDesc();
- if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
- continue;
-
- unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
- if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
- CopySrcSubIdx, CopyDstSubIdx) &&
- CopySrcReg != CopyDstReg &&
- (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
- allocatableRegs_[CopyDstReg])) {
- LiveInterval &LI = li_->getInterval(CopyDstReg);
- SlotIndex DefIdx =
- li_->getInstructionIndex(UseMI).getDefIndex();
- if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
- if (DLR->valno->def == DefIdx)
- DLR->valno->setCopy(UseMI);
- }
- }
}
}
@@ -1543,21 +1499,19 @@
MachineInstr *Inst = MII++;
// If this isn't a copy nor a extract_subreg, we can't join intervals.
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- bool isInsUndef = false;
+ unsigned SrcReg, DstReg;
if (Inst->isCopy()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(1).getReg();
} else if (Inst->isSubregToReg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(2).getReg();
- } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+ } else
continue;
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
- if (isInsUndef ||
- (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
+ if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
ImpDefCopies.push_back(CopyRec(Inst, 0));
else if (SrcIsPhys || DstIsPhys)
PhysCopies.push_back(CopyRec(Inst, 0));
@@ -1679,11 +1633,6 @@
MachineInstr *UseMI = Use.getParent();
if (UseMI->isIdentityCopy())
continue;
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- SrcReg == DstReg && SrcSubIdx == DstSubIdx)
- // Ignore identity copies.
- continue;
SlotIndex Idx = li_->getInstructionIndex(UseMI);
// FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
// that compares higher than any other interval.
@@ -1708,10 +1657,7 @@
return NULL;
// Ignore identity copies.
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (!MI->isIdentityCopy() &&
- !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- SrcReg == DstReg && SrcSubIdx == DstSubIdx))
+ if (!MI->isIdentityCopy())
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &Use = MI->getOperand(i);
if (Use.isReg() && Use.isUse() && Use.getReg() &&
@@ -1775,21 +1721,19 @@
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) {
MachineInstr *MI = mii;
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (JoinedCopies.count(MI)) {
// Delete all coalesced copies.
bool DoDelete = true;
- if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- assert(MI->isCopyLike() && "Unrecognized copy instruction");
- SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
- if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
- // Do not delete extract_subreg, insert_subreg of physical
- // registers unless the definition is dead. e.g.
- // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
- // or else the scavenger may complain. LowerSubregs will
- // delete them later.
- DoDelete = false;
- }
+ assert(MI->isCopyLike() && "Unrecognized copy instruction");
+ unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
+ if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
+ // Do not delete extract_subreg, insert_subreg of physical
+ // registers unless the definition is dead. e.g.
+ // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
+ // or else the scavenger may complain. LowerSubregs will
+ // delete them later.
+ DoDelete = false;
+
if (MI->allDefsAreDead()) {
LiveInterval &li = li_->getInterval(SrcReg);
if (!ShortenDeadCopySrcLiveRange(li, MI))
@@ -1840,9 +1784,8 @@
}
// If the move will be an identity move delete it
- bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
- if (MI->isIdentityCopy() ||
- (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
+ if (MI->isIdentityCopy()) {
+ unsigned SrcReg = MI->getOperand(1).getReg();
if (li_->hasInterval(SrcReg)) {
LiveInterval &RegInt = li_->getInterval(SrcReg);
// If def of this move instruction is dead, remove its live range
Modified: llvm/branches/wendling/eh/lib/CodeGen/SlotIndexes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/SlotIndexes.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/SlotIndexes.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/SlotIndexes.cpp Sat Jul 31 19:59:02 2010
@@ -40,7 +40,8 @@
}
char SlotIndexes::ID = 0;
-static RegisterPass<SlotIndexes> X("slotindexes", "Slot index numbering");
+INITIALIZE_PASS(SlotIndexes, "slotindexes",
+ "Slot index numbering", false, false);
IndexListEntry* IndexListEntry::getEmptyKeyEntry() {
return &*IndexListEntryEmptyKey;
Modified: llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/Spiller.cpp Sat Jul 31 19:59:02 2010
@@ -15,6 +15,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
@@ -49,22 +50,24 @@
/// Utility class for spillers.
class SpillerBase : public Spiller {
protected:
+ MachineFunctionPass *pass;
MachineFunction *mf;
+ VirtRegMap *vrm;
LiveIntervals *lis;
MachineFrameInfo *mfi;
MachineRegisterInfo *mri;
const TargetInstrInfo *tii;
const TargetRegisterInfo *tri;
- VirtRegMap *vrm;
/// Construct a spiller base.
- SpillerBase(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
- : mf(mf), lis(lis), vrm(vrm)
+ SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
+ : pass(&pass), mf(&mf), vrm(&vrm)
{
- mfi = mf->getFrameInfo();
- mri = &mf->getRegInfo();
- tii = mf->getTarget().getInstrInfo();
- tri = mf->getTarget().getRegisterInfo();
+ lis = &pass.getAnalysis<LiveIntervals>();
+ mfi = mf.getFrameInfo();
+ mri = &mf.getRegInfo();
+ tii = mf.getTarget().getInstrInfo();
+ tri = mf.getTarget().getRegisterInfo();
}
/// Add spill ranges for every use/def of the live interval, inserting loads
@@ -173,8 +176,9 @@
class TrivialSpiller : public SpillerBase {
public:
- TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
- : SpillerBase(mf, lis, vrm) {}
+ TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
+ VirtRegMap &vrm)
+ : SpillerBase(pass, mf, vrm) {}
void spill(LiveInterval *li,
std::vector<LiveInterval*> &newIntervals,
@@ -193,12 +197,14 @@
class StandardSpiller : public Spiller {
protected:
LiveIntervals *lis;
- const MachineLoopInfo *loopInfo;
+ MachineLoopInfo *loopInfo;
VirtRegMap *vrm;
public:
- StandardSpiller(LiveIntervals *lis, const MachineLoopInfo *loopInfo,
- VirtRegMap *vrm)
- : lis(lis), loopInfo(loopInfo), vrm(vrm) {}
+ StandardSpiller(MachineFunctionPass &pass, MachineFunction &mf,
+ VirtRegMap &vrm)
+ : lis(&pass.getAnalysis<LiveIntervals>()),
+ loopInfo(pass.getAnalysisIfAvailable<MachineLoopInfo>()),
+ vrm(&vrm) {}
/// Falls back on LiveIntervals::addIntervalsForSpills.
void spill(LiveInterval *li,
@@ -221,13 +227,12 @@
/// then the spiller falls back on the standard spilling mechanism.
class SplittingSpiller : public StandardSpiller {
public:
- SplittingSpiller(MachineFunction *mf, LiveIntervals *lis,
- const MachineLoopInfo *loopInfo, VirtRegMap *vrm)
- : StandardSpiller(lis, loopInfo, vrm) {
-
- mri = &mf->getRegInfo();
- tii = mf->getTarget().getInstrInfo();
- tri = mf->getTarget().getRegisterInfo();
+ SplittingSpiller(MachineFunctionPass &pass, MachineFunction &mf,
+ VirtRegMap &vrm)
+ : StandardSpiller(pass, mf, vrm) {
+ mri = &mf.getRegInfo();
+ tii = mf.getTarget().getInstrInfo();
+ tri = mf.getTarget().getRegisterInfo();
}
void spill(LiveInterval *li,
@@ -506,20 +511,19 @@
namespace llvm {
-Spiller *createInlineSpiller(MachineFunction*,
- LiveIntervals*,
- const MachineLoopInfo*,
- VirtRegMap*);
+Spiller *createInlineSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm);
}
-llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
- const MachineLoopInfo *loopInfo,
- VirtRegMap *vrm) {
+llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm) {
switch (spillerOpt) {
default: assert(0 && "unknown spiller");
- case trivial: return new TrivialSpiller(mf, lis, vrm);
- case standard: return new StandardSpiller(lis, loopInfo, vrm);
- case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);
- case inline_: return createInlineSpiller(mf, lis, loopInfo, vrm);
+ case trivial: return new TrivialSpiller(pass, mf, vrm);
+ case standard: return new StandardSpiller(pass, mf, vrm);
+ case splitting: return new SplittingSpiller(pass, mf, vrm);
+ case inline_: return createInlineSpiller(pass, mf, vrm);
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/Spiller.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/Spiller.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/Spiller.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/Spiller.h Sat Jul 31 19:59:02 2010
@@ -16,14 +16,10 @@
namespace llvm {
class LiveInterval;
- class LiveIntervals;
- class LiveStacks;
class MachineFunction;
- class MachineInstr;
- class MachineLoopInfo;
+ class MachineFunctionPass;
class SlotIndex;
class VirtRegMap;
- class VNInfo;
/// Spiller interface.
///
@@ -50,8 +46,9 @@
};
/// Create and return a spiller object, as specified on the command line.
- Spiller* createSpiller(MachineFunction *mf, LiveIntervals *li,
- const MachineLoopInfo *loopInfo, VirtRegMap *vrm);
+ Spiller* createSpiller(MachineFunctionPass &pass,
+ MachineFunction &mf,
+ VirtRegMap &vrm);
}
#endif
Modified: llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/StackProtector.cpp Sat Jul 31 19:59:02 2010
@@ -71,8 +71,8 @@
} // end anonymous namespace
char StackProtector::ID = 0;
-static RegisterPass<StackProtector>
-X("stack-protector", "Insert stack protectors");
+INITIALIZE_PASS(StackProtector, "stack-protector",
+ "Insert stack protectors", false, false);
FunctionPass *llvm::createStackProtectorPass(const TargetLowering *tli) {
return new StackProtector(tli);
Modified: llvm/branches/wendling/eh/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/StackSlotColoring.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/StackSlotColoring.cpp Sat Jul 31 19:59:02 2010
@@ -146,8 +146,8 @@
char StackSlotColoring::ID = 0;
-static RegisterPass<StackSlotColoring>
-X("stack-slot-coloring", "Stack Slot Coloring");
+INITIALIZE_PASS(StackSlotColoring, "stack-slot-coloring",
+ "Stack Slot Coloring", false, false);
FunctionPass *llvm::createStackSlotColoringPass(bool RegColor) {
return new StackSlotColoring(RegColor);
Modified: llvm/branches/wendling/eh/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TailDuplication.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TailDuplication.cpp Sat Jul 31 19:59:02 2010
@@ -254,14 +254,15 @@
// SSA form.
for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
MachineInstr *Copy = Copies[i];
- unsigned Src, Dst, SrcSR, DstSR;
- if (TII->isMoveInstr(*Copy, Src, Dst, SrcSR, DstSR)) {
- MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
- if (++UI == MRI->use_end()) {
- // Copy is the only use. Do trivial copy propagation here.
- MRI->replaceRegWith(Dst, Src);
- Copy->eraseFromParent();
- }
+ if (!Copy->isCopy())
+ continue;
+ unsigned Dst = Copy->getOperand(0).getReg();
+ unsigned Src = Copy->getOperand(1).getReg();
+ MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
+ if (++UI == MRI->use_end()) {
+ // Copy is the only use. Do trivial copy propagation here.
+ MRI->replaceRegWith(Dst, Src);
+ Copy->eraseFromParent();
}
}
Modified: llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TargetInstrInfoImpl.cpp Sat Jul 31 19:59:02 2010
@@ -178,19 +178,6 @@
return MF.CloneMachineInstr(Orig);
}
-unsigned
-TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
- unsigned FnSize = 0;
- for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
- MBBI != E; ++MBBI) {
- const MachineBasicBlock &MBB = *MBBI;
- for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
- I != E; ++I)
- FnSize += GetInstSizeInBytes(I);
- }
- return FnSize;
-}
-
// If the COPY instruction in MI can be folded to a stack operation, return
// the register class to use.
static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
Modified: llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sat Jul 31 19:59:02 2010
@@ -518,12 +518,13 @@
SectionKind::getText());
ConstTextCoalSection
= getContext().getMachOSection("__TEXT", "__const_coal",
- MCSectionMachO::S_COALESCED,
+ MCSectionMachO::S_COALESCED |
+ MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
SectionKind::getText());
ConstDataCoalSection
= getContext().getMachOSection("__DATA","__const_coal",
MCSectionMachO::S_COALESCED,
- SectionKind::getText());
+ SectionKind::getReadOnly());
ConstDataSection // .const_data
= getContext().getMachOSection("__DATA", "__const", 0,
SectionKind::getReadOnlyWithRel());
Modified: llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/TwoAddressInstructionPass.cpp Sat Jul 31 19:59:02 2010
@@ -380,26 +380,18 @@
bool &IsSrcPhys, bool &IsDstPhys) {
SrcReg = 0;
DstReg = 0;
- unsigned SrcSubIdx, DstSubIdx;
- if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- if (MI.isCopy()) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- } else if (MI.isInsertSubreg()) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(2).getReg();
- } else if (MI.isSubregToReg()) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(2).getReg();
- }
- }
+ if (MI.isCopy()) {
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
+ } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(2).getReg();
+ } else
+ return false;
- if (DstReg) {
- IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
- IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
- return true;
- }
- return false;
+ IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
+ IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
+ return true;
}
/// isKilled - Test if the given register value, which is used by the given
Modified: llvm/branches/wendling/eh/lib/CodeGen/UnreachableBlockElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/UnreachableBlockElim.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/UnreachableBlockElim.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/UnreachableBlockElim.cpp Sat Jul 31 19:59:02 2010
@@ -51,8 +51,8 @@
};
}
char UnreachableBlockElim::ID = 0;
-static RegisterPass<UnreachableBlockElim>
-X("unreachableblockelim", "Remove unreachable blocks from the CFG");
+INITIALIZE_PASS(UnreachableBlockElim, "unreachableblockelim",
+ "Remove unreachable blocks from the CFG", false, false);
FunctionPass *llvm::createUnreachableBlockEliminationPass() {
return new UnreachableBlockElim();
Modified: llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.cpp Sat Jul 31 19:59:02 2010
@@ -48,8 +48,7 @@
char VirtRegMap::ID = 0;
-static RegisterPass<VirtRegMap>
-X("virtregmap", "Virtual Register Map");
+INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false);
bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
MRI = &mf.getRegInfo();
Modified: llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.h (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/VirtRegMap.h Sat Jul 31 19:59:02 2010
@@ -152,6 +152,11 @@
MachineFunctionPass::getAnalysisUsage(AU);
}
+ MachineFunction &getMachineFunction() const {
+ assert(MF && "getMachineFunction called before runOnMAchineFunction");
+ return *MF;
+ }
+
void grow();
/// @brief returns true if the specified virtual register is
Modified: llvm/branches/wendling/eh/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CodeGen/VirtRegRewriter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/CodeGen/VirtRegRewriter.cpp Sat Jul 31 19:59:02 2010
@@ -460,7 +460,7 @@
/// blocks each of which is a successor of the specified BB and has no other
/// predecessor.
static void findSinglePredSuccessor(MachineBasicBlock *MBB,
- SmallVectorImpl<MachineBasicBlock *> &Succs) {
+ SmallVectorImpl<MachineBasicBlock *> &Succs){
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
SE = MBB->succ_end(); SI != SE; ++SI) {
MachineBasicBlock *SuccMBB = *SI;
@@ -852,8 +852,8 @@
// Yup, use the reload register that we didn't use before.
unsigned NewReg = Op.AssignedPhysReg;
Rejected.insert(PhysReg);
- return GetRegForReload(RC, NewReg, MF, MI, Spills, MaybeDeadStores, Rejected,
- RegKills, KillOps, VRM);
+ return GetRegForReload(RC, NewReg, MF, MI, Spills, MaybeDeadStores,
+ Rejected, RegKills, KillOps, VRM);
} else {
// Otherwise, we might also have a problem if a previously reused
// value aliases the new register. If so, codegen the previous reload
@@ -1864,7 +1864,7 @@
/// rewriteMBB - Keep track of which spills are available even after the
-/// register allocator is done with them. If possible, avid reloading vregs.
+/// register allocator is done with them. If possible, avoid reloading vregs.
void
LocalRewriter::RewriteMBB(LiveIntervals *LIs,
AvailableSpills &Spills, BitVector &RegKills,
@@ -2302,7 +2302,7 @@
unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
SmallVector<MachineInstr*, 4> NewMIs;
if (PhysReg &&
- TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
+ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)){
MBB->insert(MII, NewMIs[0]);
InvalidateKills(MI, TRI, RegKills, KillOps);
VRM->RemoveMachineInstrFromMaps(&MI);
@@ -2442,28 +2442,6 @@
Spills.disallowClobberPhysReg(VirtReg);
goto ProcessNextInst;
}
- unsigned Src, Dst, SrcSR, DstSR;
- if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) &&
- Src == Dst && SrcSR == DstSR &&
- !MI.findRegisterUseOperand(Src)->isUndef()) {
- ++NumDCE;
- DEBUG(dbgs() << "Removing now-noop copy: " << MI);
- SmallVector<unsigned, 2> KillRegs;
- InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs);
- if (MO.isDead() && !KillRegs.empty()) {
- // Source register or an implicit super/sub-register use is killed.
- assert(KillRegs[0] == Dst ||
- TRI->isSubRegister(KillRegs[0], Dst) ||
- TRI->isSuperRegister(KillRegs[0], Dst));
- // Last def is now dead.
- TransferDeadness(Src, RegKills, KillOps);
- }
- VRM->RemoveMachineInstrFromMaps(&MI);
- MBB->erase(&MI);
- Erased = true;
- Spills.disallowClobberPhysReg(VirtReg);
- goto ProcessNextInst;
- }
// If it's not a no-op copy, it clobbers the value in the destreg.
Spills.ClobberPhysReg(VirtReg);
@@ -2541,20 +2519,6 @@
UpdateKills(*LastStore, TRI, RegKills, KillOps);
goto ProcessNextInst;
}
- {
- unsigned Src, Dst, SrcSR, DstSR;
- if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) &&
- Src == Dst && SrcSR == DstSR) {
- ++NumDCE;
- DEBUG(dbgs() << "Removing now-noop copy: " << MI);
- InvalidateKills(MI, TRI, RegKills, KillOps);
- VRM->RemoveMachineInstrFromMaps(&MI);
- MBB->erase(&MI);
- Erased = true;
- UpdateKills(*LastStore, TRI, RegKills, KillOps);
- goto ProcessNextInst;
- }
- }
}
}
ProcessNextInst:
Modified: llvm/branches/wendling/eh/lib/CompilerDriver/Action.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CompilerDriver/Action.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CompilerDriver/Action.cpp (original)
+++ llvm/branches/wendling/eh/lib/CompilerDriver/Action.cpp Sat Jul 31 19:59:02 2010
@@ -13,6 +13,7 @@
#include "llvm/CompilerDriver/Action.h"
#include "llvm/CompilerDriver/BuiltinOptions.h"
+#include "llvm/CompilerDriver/Error.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/SystemUtils.h"
@@ -58,11 +59,15 @@
if (prog.isEmpty()) {
prog = FindExecutable(name, ProgramName, (void *)(intptr_t)&Main);
- if (prog.isEmpty())
- throw std::runtime_error("Can't find program '" + name + "'");
+ if (prog.isEmpty()) {
+ PrintError("Can't find program '" + name + "'");
+ return -1;
+ }
+ }
+ if (!prog.canExecute()) {
+ PrintError("Program '" + name + "' is not executable.");
+ return -1;
}
- if (!prog.canExecute())
- throw std::runtime_error("Program '" + name + "' is not executable.");
// Build the command line vector and the redirects array.
const sys::Path* redirects[3] = {0,0,0};
Modified: llvm/branches/wendling/eh/lib/CompilerDriver/CompilationGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CompilerDriver/CompilationGraph.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CompilerDriver/CompilationGraph.cpp (original)
+++ llvm/branches/wendling/eh/lib/CompilerDriver/CompilationGraph.cpp Sat Jul 31 19:59:02 2010
@@ -25,21 +25,22 @@
#include <iterator>
#include <limits>
#include <queue>
-#include <stdexcept>
using namespace llvm;
using namespace llvmc;
namespace llvmc {
- const std::string& LanguageMap::GetLanguage(const sys::Path& File) const {
+ const std::string* LanguageMap::GetLanguage(const sys::Path& File) const {
StringRef suf = File.getSuffix();
LanguageMap::const_iterator Lang =
this->find(suf.empty() ? "*empty*" : suf);
- if (Lang == this->end())
- throw std::runtime_error("File '" + File.str() +
- "' has unknown suffix '" + suf.str() + '\'');
- return Lang->second;
+ if (Lang == this->end()) {
+ PrintError("File '" + File.str() + "' has unknown suffix '"
+ + suf.str() + '\'');
+ return 0;
+ }
+ return &Lang->second;
}
}
@@ -67,14 +68,16 @@
}
}
- if (!SingleMax)
- throw std::runtime_error("Node " + NodeName +
- ": multiple maximal outward edges found!"
- " Most probably a specification error.");
- if (!MaxEdge)
- throw std::runtime_error("Node " + NodeName +
- ": no maximal outward edge found!"
- " Most probably a specification error.");
+ if (!SingleMax) {
+ PrintError("Node " + NodeName + ": multiple maximal outward edges found!"
+ " Most probably a specification error.");
+ return 0;
+ }
+ if (!MaxEdge) {
+ PrintError("Node " + NodeName + ": no maximal outward edge found!"
+ " Most probably a specification error.");
+ return 0;
+ }
return MaxEdge;
}
@@ -98,29 +101,34 @@
NodesMap["root"] = Node(this);
}
-Node& CompilationGraph::getNode(const std::string& ToolName) {
+Node* CompilationGraph::getNode(const std::string& ToolName) {
nodes_map_type::iterator I = NodesMap.find(ToolName);
- if (I == NodesMap.end())
- throw std::runtime_error("Node " + ToolName + " is not in the graph");
- return I->second;
+ if (I == NodesMap.end()) {
+ PrintError("Node " + ToolName + " is not in the graph");
+ return 0;
+ }
+ return &I->second;
}
-const Node& CompilationGraph::getNode(const std::string& ToolName) const {
+const Node* CompilationGraph::getNode(const std::string& ToolName) const {
nodes_map_type::const_iterator I = NodesMap.find(ToolName);
- if (I == NodesMap.end())
- throw std::runtime_error("Node " + ToolName + " is not in the graph!");
- return I->second;
+ if (I == NodesMap.end()) {
+ PrintError("Node " + ToolName + " is not in the graph!");
+ return 0;
+ }
+ return &I->second;
}
// Find the tools list corresponding to the given language name.
-const CompilationGraph::tools_vector_type&
+const CompilationGraph::tools_vector_type*
CompilationGraph::getToolsVector(const std::string& LangName) const
{
tools_map_type::const_iterator I = ToolsMap.find(LangName);
- if (I == ToolsMap.end())
- throw std::runtime_error("No tool corresponding to the language "
- + LangName + " found");
- return I->second;
+ if (I == ToolsMap.end()) {
+ PrintError("No tool corresponding to the language " + LangName + " found");
+ return 0;
+ }
+ return &I->second;
}
void CompilationGraph::insertNode(Tool* V) {
@@ -128,29 +136,37 @@
NodesMap[V->Name()] = Node(this, V);
}
-void CompilationGraph::insertEdge(const std::string& A, Edge* Edg) {
- Node& B = getNode(Edg->ToolName());
+int CompilationGraph::insertEdge(const std::string& A, Edge* Edg) {
+ Node* B = getNode(Edg->ToolName());
+ if (B == 0)
+ return 1;
+
if (A == "root") {
- const char** InLangs = B.ToolPtr->InputLanguages();
+ const char** InLangs = B->ToolPtr->InputLanguages();
for (;*InLangs; ++InLangs)
ToolsMap[*InLangs].push_back(IntrusiveRefCntPtr<Edge>(Edg));
NodesMap["root"].AddEdge(Edg);
}
else {
- Node& N = getNode(A);
- N.AddEdge(Edg);
+ Node* N = getNode(A);
+ if (N == 0)
+ return 1;
+
+ N->AddEdge(Edg);
}
// Increase the inward edge counter.
- B.IncrInEdges();
+ B->IncrInEdges();
+
+ return 0;
}
// Pass input file through the chain until we bump into a Join node or
// a node that says that it is the last.
-void CompilationGraph::PassThroughGraph (const sys::Path& InFile,
- const Node* StartNode,
- const InputLanguagesSet& InLangs,
- const sys::Path& TempDir,
- const LanguageMap& LangMap) const {
+int CompilationGraph::PassThroughGraph (const sys::Path& InFile,
+ const Node* StartNode,
+ const InputLanguagesSet& InLangs,
+ const sys::Path& TempDir,
+ const LanguageMap& LangMap) const {
sys::Path In = InFile;
const Node* CurNode = StartNode;
@@ -158,25 +174,35 @@
Tool* CurTool = CurNode->ToolPtr.getPtr();
if (CurTool->IsJoin()) {
- JoinTool& JT = dynamic_cast<JoinTool&>(*CurTool);
+ JoinTool& JT = static_cast<JoinTool&>(*CurTool);
JT.AddToJoinList(In);
break;
}
- Action CurAction = CurTool->GenerateAction(In, CurNode->HasChildren(),
- TempDir, InLangs, LangMap);
+ Action CurAction;
+ if (int ret = CurTool->GenerateAction(CurAction, In, CurNode->HasChildren(),
+ TempDir, InLangs, LangMap)) {
+ return ret;
+ }
if (int ret = CurAction.Execute())
- throw error_code(ret);
+ return ret;
if (CurAction.StopCompilation())
- return;
+ return 0;
+
+ const Edge* Edg = ChooseEdge(CurNode->OutEdges, InLangs, CurNode->Name());
+ if (Edg == 0)
+ return 1;
+
+ CurNode = getNode(Edg->ToolName());
+ if (CurNode == 0)
+ return 1;
- CurNode = &getNode(ChooseEdge(CurNode->OutEdges,
- InLangs,
- CurNode->Name())->ToolName());
In = CurAction.OutFile();
}
+
+ return 0;
}
// Find the head of the toolchain corresponding to the given file.
@@ -186,26 +212,39 @@
InputLanguagesSet& InLangs, const LanguageMap& LangMap) const {
// Determine the input language.
- const std::string& InLanguage =
- ForceLanguage ? *ForceLanguage : LangMap.GetLanguage(In);
+ const std::string* InLang = LangMap.GetLanguage(In);
+ if (InLang == 0)
+ return 0;
+ const std::string& InLanguage = (ForceLanguage ? *ForceLanguage : *InLang);
// Add the current input language to the input language set.
InLangs.insert(InLanguage);
// Find the toolchain for the input language.
- const tools_vector_type& TV = getToolsVector(InLanguage);
- if (TV.empty())
- throw std::runtime_error("No toolchain corresponding to language "
- + InLanguage + " found");
- return &getNode(ChooseEdge(TV, InLangs)->ToolName());
+ const tools_vector_type* pTV = getToolsVector(InLanguage);
+ if (pTV == 0)
+ return 0;
+
+ const tools_vector_type& TV = *pTV;
+ if (TV.empty()) {
+ PrintError("No toolchain corresponding to language "
+ + InLanguage + " found");
+ return 0;
+ }
+
+ const Edge* Edg = ChooseEdge(TV, InLangs);
+ if (Edg == 0)
+ return 0;
+
+ return getNode(Edg->ToolName());
}
// Helper function used by Build().
// Traverses initial portions of the toolchains (up to the first Join node).
// This function is also responsible for handling the -x option.
-void CompilationGraph::BuildInitial (InputLanguagesSet& InLangs,
- const sys::Path& TempDir,
- const LanguageMap& LangMap) {
+int CompilationGraph::BuildInitial (InputLanguagesSet& InLangs,
+ const sys::Path& TempDir,
+ const LanguageMap& LangMap) {
// This is related to -x option handling.
cl::list<std::string>::const_iterator xIter = Languages.begin(),
xBegin = xIter, xEnd = Languages.end();
@@ -255,15 +294,25 @@
// Find the toolchain corresponding to this file.
const Node* N = FindToolChain(In, xLanguage, InLangs, LangMap);
+ if (N == 0)
+ return 1;
// Pass file through the chain starting at head.
- PassThroughGraph(In, N, InLangs, TempDir, LangMap);
+ if (int ret = PassThroughGraph(In, N, InLangs, TempDir, LangMap))
+ return ret;
}
+
+ return 0;
}
// Sort the nodes in topological order.
-void CompilationGraph::TopologicalSort(std::vector<const Node*>& Out) {
+int CompilationGraph::TopologicalSort(std::vector<const Node*>& Out) {
std::queue<const Node*> Q;
- Q.push(&getNode("root"));
+
+ Node* Root = getNode("root");
+ if (Root == 0)
+ return 1;
+
+ Q.push(Root);
while (!Q.empty()) {
const Node* A = Q.front();
@@ -271,12 +320,17 @@
Out.push_back(A);
for (Node::const_iterator EB = A->EdgesBegin(), EE = A->EdgesEnd();
EB != EE; ++EB) {
- Node* B = &getNode((*EB)->ToolName());
+ Node* B = getNode((*EB)->ToolName());
+ if (B == 0)
+ return 1;
+
B->DecrInEdges();
if (B->HasNoInEdges())
Q.push(B);
}
}
+
+ return 0;
}
namespace {
@@ -287,49 +341,71 @@
// Call TopologicalSort and filter the resulting list to include
// only Join nodes.
-void CompilationGraph::
+int CompilationGraph::
TopologicalSortFilterJoinNodes(std::vector<const Node*>& Out) {
std::vector<const Node*> TopSorted;
- TopologicalSort(TopSorted);
+ if (int ret = TopologicalSort(TopSorted))
+ return ret;
std::remove_copy_if(TopSorted.begin(), TopSorted.end(),
std::back_inserter(Out), NotJoinNode);
+
+ return 0;
}
int CompilationGraph::Build (const sys::Path& TempDir,
const LanguageMap& LangMap) {
-
InputLanguagesSet InLangs;
+ bool WasSomeActionGenerated = !InputFilenames.empty();
// Traverse initial parts of the toolchains and fill in InLangs.
- BuildInitial(InLangs, TempDir, LangMap);
+ if (int ret = BuildInitial(InLangs, TempDir, LangMap))
+ return ret;
std::vector<const Node*> JTV;
- TopologicalSortFilterJoinNodes(JTV);
+ if (int ret = TopologicalSortFilterJoinNodes(JTV))
+ return ret;
// For all join nodes in topological order:
for (std::vector<const Node*>::iterator B = JTV.begin(), E = JTV.end();
B != E; ++B) {
const Node* CurNode = *B;
- JoinTool* JT = &dynamic_cast<JoinTool&>(*CurNode->ToolPtr.getPtr());
+ JoinTool* JT = &static_cast<JoinTool&>(*CurNode->ToolPtr.getPtr());
// Are there any files in the join list?
if (JT->JoinListEmpty() && !(JT->WorksOnEmpty() && InputFilenames.empty()))
continue;
- Action CurAction = JT->GenerateAction(CurNode->HasChildren(),
- TempDir, InLangs, LangMap);
+ WasSomeActionGenerated = true;
+ Action CurAction;
+ if (int ret = JT->GenerateAction(CurAction, CurNode->HasChildren(),
+ TempDir, InLangs, LangMap)) {
+ return ret;
+ }
if (int ret = CurAction.Execute())
- throw error_code(ret);
+ return ret;
if (CurAction.StopCompilation())
return 0;
- const Node* NextNode = &getNode(ChooseEdge(CurNode->OutEdges, InLangs,
- CurNode->Name())->ToolName());
- PassThroughGraph(sys::Path(CurAction.OutFile()), NextNode,
- InLangs, TempDir, LangMap);
+ const Edge* Edg = ChooseEdge(CurNode->OutEdges, InLangs, CurNode->Name());
+ if (Edg == 0)
+ return 1;
+
+ const Node* NextNode = getNode(Edg->ToolName());
+ if (NextNode == 0)
+ return 1;
+
+ if (int ret = PassThroughGraph(sys::Path(CurAction.OutFile()), NextNode,
+ InLangs, TempDir, LangMap)) {
+ return ret;
+ }
+ }
+
+ if (!WasSomeActionGenerated) {
+ PrintError("no input files");
+ return 1;
}
return 0;
@@ -337,6 +413,7 @@
int CompilationGraph::CheckLanguageNames() const {
int ret = 0;
+
// Check that names for output and input languages on all edges do match.
for (const_nodes_iterator B = this->NodesMap.begin(),
E = this->NodesMap.end(); B != E; ++B) {
@@ -345,9 +422,11 @@
if (N1.ToolPtr) {
for (Node::const_iterator EB = N1.EdgesBegin(), EE = N1.EdgesEnd();
EB != EE; ++EB) {
- const Node& N2 = this->getNode((*EB)->ToolName());
+ const Node* N2 = this->getNode((*EB)->ToolName());
+ if (N2 == 0)
+ return 1;
- if (!N2.ToolPtr) {
+ if (!N2->ToolPtr) {
++ret;
errs() << "Error: there is an edge from '" << N1.ToolPtr->Name()
<< "' back to the root!\n\n";
@@ -355,7 +434,7 @@
}
const char* OutLang = N1.ToolPtr->OutputLanguage();
- const char** InLangs = N2.ToolPtr->InputLanguages();
+ const char** InLangs = N2->ToolPtr->InputLanguages();
bool eq = false;
for (;*InLangs; ++InLangs) {
if (std::strcmp(OutLang, *InLangs) == 0) {
@@ -367,11 +446,11 @@
if (!eq) {
++ret;
errs() << "Error: Output->input language mismatch in the edge '"
- << N1.ToolPtr->Name() << "' -> '" << N2.ToolPtr->Name()
+ << N1.ToolPtr->Name() << "' -> '" << N2->ToolPtr->Name()
<< "'!\n"
<< "Expected one of { ";
- InLangs = N2.ToolPtr->InputLanguages();
+ InLangs = N2->ToolPtr->InputLanguages();
for (;*InLangs; ++InLangs) {
errs() << '\'' << *InLangs << (*(InLangs+1) ? "', " : "'");
}
@@ -422,7 +501,12 @@
int CompilationGraph::CheckCycles() {
unsigned deleted = 0;
std::queue<Node*> Q;
- Q.push(&getNode("root"));
+
+ Node* Root = getNode("root");
+ if (Root == 0)
+ return 1;
+
+ Q.push(Root);
// Try to delete all nodes that have no ingoing edges, starting from the
// root. If there are any nodes left after this operation, then we have a
@@ -434,7 +518,10 @@
for (Node::iterator EB = A->EdgesBegin(), EE = A->EdgesEnd();
EB != EE; ++EB) {
- Node* B = &getNode((*EB)->ToolName());
+ Node* B = getNode((*EB)->ToolName());
+ if (B == 0)
+ return 1;
+
B->DecrInEdges();
if (B->HasNoInEdges())
Q.push(B);
@@ -453,18 +540,28 @@
int CompilationGraph::Check () {
// We try to catch as many errors as we can in one go.
+ int errs = 0;
int ret = 0;
// Check that output/input language names match.
- ret += this->CheckLanguageNames();
+ ret = this->CheckLanguageNames();
+ if (ret < 0)
+ return 1;
+ errs += ret;
// Check for multiple default edges.
- ret += this->CheckMultipleDefaultEdges();
+ ret = this->CheckMultipleDefaultEdges();
+ if (ret < 0)
+ return 1;
+ errs += ret;
// Check for cycles.
- ret += this->CheckCycles();
+ ret = this->CheckCycles();
+ if (ret < 0)
+ return 1;
+ errs += ret;
- return ret;
+ return errs;
}
// Code related to graph visualization.
@@ -516,7 +613,7 @@
}
-void CompilationGraph::writeGraph(const std::string& OutputFilename) {
+int CompilationGraph::writeGraph(const std::string& OutputFilename) {
std::string ErrorInfo;
raw_fd_ostream O(OutputFilename.c_str(), ErrorInfo);
@@ -526,9 +623,11 @@
errs() << "done.\n";
}
else {
- throw std::runtime_error("Error opening file '" + OutputFilename
- + "' for writing!");
+ PrintError("Error opening file '" + OutputFilename + "' for writing!");
+ return 1;
}
+
+ return 0;
}
void CompilationGraph::viewGraph() {
Modified: llvm/branches/wendling/eh/lib/CompilerDriver/Main.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CompilerDriver/Main.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CompilerDriver/Main.cpp (original)
+++ llvm/branches/wendling/eh/lib/CompilerDriver/Main.cpp Sat Jul 31 19:59:02 2010
@@ -20,7 +20,6 @@
#include "llvm/System/Path.h"
#include <sstream>
-#include <stdexcept>
#include <string>
namespace cl = llvm::cl;
@@ -31,9 +30,9 @@
std::stringstream* GlobalTimeLog;
- sys::Path getTempDir() {
- sys::Path tempDir;
-
+ /// GetTempDir - Get the temporary directory location. Returns non-zero value
+ /// on error.
+ int GetTempDir(sys::Path& tempDir) {
// The --temp-dir option.
if (!TempDirname.empty()) {
tempDir = TempDirname;
@@ -41,7 +40,7 @@
// GCC 4.5-style -save-temps handling.
else if (SaveTemps == SaveTempsEnum::Unset) {
tempDir = sys::Path::GetTemporaryDirectory();
- return tempDir;
+ return 0;
}
else if (SaveTemps == SaveTempsEnum::Obj && !OutputFilename.empty()) {
tempDir = OutputFilename;
@@ -49,35 +48,34 @@
}
else {
// SaveTemps == Cwd --> use current dir (leave tempDir empty).
- return tempDir;
+ return 0;
}
if (!tempDir.exists()) {
std::string ErrMsg;
- if (tempDir.createDirectoryOnDisk(true, &ErrMsg))
- throw std::runtime_error(ErrMsg);
+ if (tempDir.createDirectoryOnDisk(true, &ErrMsg)) {
+ PrintError(ErrMsg);
+ return 1;
+ }
}
- return tempDir;
+ return 0;
}
- /// BuildTargets - A small wrapper for CompilationGraph::Build.
+ /// BuildTargets - A small wrapper for CompilationGraph::Build. Returns non-zero value
int BuildTargets(CompilationGraph& graph, const LanguageMap& langMap) {
int ret;
- const sys::Path& tempDir = getTempDir();
+ sys::Path tempDir;
bool toDelete = (SaveTemps == SaveTempsEnum::Unset);
- try {
- ret = graph.Build(tempDir, langMap);
- }
- catch(...) {
- if (toDelete)
- tempDir.eraseFromDisk(true);
- throw;
- }
+ if (int ret = GetTempDir(tempDir))
+ return ret;
+
+ ret = graph.Build(tempDir, langMap);
if (toDelete)
tempDir.eraseFromDisk(true);
+
return ret;
}
}
@@ -93,64 +91,54 @@
const char* ProgramName;
int Main(int argc, char** argv) {
- try {
- LanguageMap langMap;
- CompilationGraph graph;
-
- ProgramName = argv[0];
-
- cl::ParseCommandLineOptions
- (argc, argv, "LLVM Compiler Driver (Work In Progress)",
- /* ReadResponseFiles = */ false);
-
- PluginLoader Plugins;
- Plugins.RunInitialization(langMap, graph);
-
- if (CheckGraph) {
- int ret = graph.Check();
- if (!ret)
- llvm::errs() << "check-graph: no errors found.\n";
+ int ret = 0;
+ LanguageMap langMap;
+ CompilationGraph graph;
+
+ ProgramName = argv[0];
+
+ cl::ParseCommandLineOptions
+ (argc, argv, "LLVM Compiler Driver (Work In Progress)",
+ /* ReadResponseFiles = */ false);
- return ret;
- }
+ PluginLoader Plugins;
+ if (int ret = Plugins.RunInitialization(langMap, graph))
+ return ret;
- if (ViewGraph) {
- graph.viewGraph();
- if (!WriteGraph)
- return 0;
- }
+ if (CheckGraph) {
+ ret = graph.Check();
+ if (!ret)
+ llvm::errs() << "check-graph: no errors found.\n";
- if (WriteGraph) {
- graph.writeGraph(OutputFilename.empty()
- ? std::string("compilation-graph.dot")
- : OutputFilename);
+ return ret;
+ }
+
+ if (ViewGraph) {
+ graph.viewGraph();
+ if (!WriteGraph)
return 0;
- }
+ }
- if (Time) {
- GlobalTimeLog = new std::stringstream;
- GlobalTimeLog->precision(2);
- }
+ if (WriteGraph) {
+ const std::string& Out = (OutputFilename.empty()
+ ? std::string("compilation-graph.dot")
+ : OutputFilename);
+ return graph.writeGraph(Out);
+ }
- int ret = BuildTargets(graph, langMap);
+ if (Time) {
+ GlobalTimeLog = new std::stringstream;
+ GlobalTimeLog->precision(2);
+ }
- if (Time) {
- llvm::errs() << GlobalTimeLog->str();
- delete GlobalTimeLog;
- }
+ ret = BuildTargets(graph, langMap);
- return ret;
- }
- catch(llvmc::error_code& ec) {
- return ec.code();
+ if (Time) {
+ llvm::errs() << GlobalTimeLog->str();
+ delete GlobalTimeLog;
}
- catch(const std::exception& ex) {
- llvm::errs() << argv[0] << ": " << ex.what() << '\n';
- }
- catch(...) {
- llvm::errs() << argv[0] << ": unknown error!\n";
- }
- return 1;
+
+ return ret;
}
} // end namespace llvmc
Modified: llvm/branches/wendling/eh/lib/CompilerDriver/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CompilerDriver/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CompilerDriver/Makefile (original)
+++ llvm/branches/wendling/eh/lib/CompilerDriver/Makefile Sat Jul 31 19:59:02 2010
@@ -21,9 +21,6 @@
LINK_COMPONENTS = support system
endif
-REQUIRES_EH := 1
-REQUIRES_RTTI := 1
-
include $(LEVEL)/Makefile.common
ifeq ($(ENABLE_LLVMC_DYNAMIC_PLUGINS), 1)
Modified: llvm/branches/wendling/eh/lib/CompilerDriver/Plugin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/CompilerDriver/Plugin.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/CompilerDriver/Plugin.cpp (original)
+++ llvm/branches/wendling/eh/lib/CompilerDriver/Plugin.cpp Sat Jul 31 19:59:02 2010
@@ -62,17 +62,22 @@
pluginListInitialized = false;
}
- void PluginLoader::RunInitialization(LanguageMap& langMap,
- CompilationGraph& graph) const
+ int PluginLoader::RunInitialization(LanguageMap& langMap,
+ CompilationGraph& graph) const
{
llvm::sys::SmartScopedLock<true> Lock(*PluginMutex);
for (PluginList::iterator B = Plugins.begin(), E = Plugins.end();
B != E; ++B) {
const BasePlugin* BP = *B;
- BP->PreprocessOptions();
- BP->PopulateLanguageMap(langMap);
- BP->PopulateCompilationGraph(graph);
+ if (int ret = BP->PreprocessOptions())
+ return ret;
+ if (int ret = BP->PopulateLanguageMap(langMap))
+ return ret;
+ if (int ret = BP->PopulateCompilationGraph(graph))
+ return ret;
}
+
+ return 0;
}
}
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/ExecutionEngineBindings.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/ExecutionEngineBindings.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/ExecutionEngineBindings.cpp (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/ExecutionEngineBindings.cpp Sat Jul 31 19:59:02 2010
@@ -236,6 +236,10 @@
return 1;
}
+void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE, LLVMValueRef Fn) {
+ return unwrap(EE)->recompileAndRelinkFunction(unwrap<Function>(Fn));
+}
+
LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef EE) {
return wrap(unwrap(EE)->getTargetData());
}
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JIT.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JIT.cpp (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JIT.cpp Sat Jul 31 19:59:02 2010
@@ -67,7 +67,7 @@
}
-#if defined(__GNUC__) && !defined(__ARM__EABI__)
+#if defined(__GNUC__) && !defined(__ARM_EABI__) && !defined(__USING_SJLJ_EXCEPTIONS__)
// libgcc defines the __register_frame function to dynamically register new
// dwarf frames for exception handling. This functionality is not portable
@@ -308,7 +308,7 @@
}
// Register routine for informing unwinding runtime about new EH frames
-#if defined(__GNUC__) && !defined(__ARM_EABI__)
+#if defined(__GNUC__) && !defined(__ARM_EABI__) && !defined(__USING_SJLJ_EXCEPTIONS__)
#if USE_KEYMGR
struct LibgccObjectInfo* LOI = (struct LibgccObjectInfo*)
_keymgr_get_and_lock_processwide_ptr(KEYMGR_GCC3_DW2_OBJ_LIST);
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp Sat Jul 31 19:59:02 2010
@@ -90,8 +90,8 @@
// section. This allows GDB to get a good stack trace, particularly on
// linux x86_64. Mark this as a PROGBITS section that needs to be loaded
// into memory at runtime.
- ELFSection &EH = EW.getSection(".eh_frame", ELFSection::SHT_PROGBITS,
- ELFSection::SHF_ALLOC);
+ ELFSection &EH = EW.getSection(".eh_frame", ELF::SHT_PROGBITS,
+ ELF::SHF_ALLOC);
// Pointers in the DWARF EH info are all relative to the EH frame start,
// which is stored here.
EH.Addr = (uint64_t)I.EhStart;
@@ -102,9 +102,9 @@
// Add this single function to the symbol table, so the debugger prints the
// name instead of '???'. We give the symbol default global visibility.
ELFSym *FnSym = ELFSym::getGV(F,
- ELFSym::STB_GLOBAL,
- ELFSym::STT_FUNC,
- ELFSym::STV_DEFAULT);
+ ELF::STB_GLOBAL,
+ ELF::STT_FUNC,
+ ELF::STV_DEFAULT);
FnSym->SectionIdx = Text.SectionIdx;
FnSym->Size = I.FnEnd - I.FnStart;
FnSym->Value = 0; // Offset from start of section.
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -595,443 +595,3 @@
return StartEHPtr;
}
-
-unsigned JITDwarfEmitter::GetDwarfTableSizeInBytes(MachineFunction& F,
- JITCodeEmitter& jce,
- unsigned char* StartFunction,
- unsigned char* EndFunction) {
- const TargetMachine& TM = F.getTarget();
- TD = TM.getTargetData();
- stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection();
- RI = TM.getRegisterInfo();
- JCE = &jce;
- unsigned FinalSize = 0;
-
- FinalSize += GetExceptionTableSizeInBytes(&F);
-
- const std::vector<const Function *> Personalities = MMI->getPersonalities();
- FinalSize +=
- GetCommonEHFrameSizeInBytes(Personalities[MMI->getPersonalityIndex()]);
-
- FinalSize += GetEHFrameSizeInBytes(Personalities[MMI->getPersonalityIndex()],
- StartFunction);
-
- return FinalSize;
-}
-
-/// RoundUpToAlign - Add the specified alignment to FinalSize and returns
-/// the new value.
-static unsigned RoundUpToAlign(unsigned FinalSize, unsigned Alignment) {
- if (Alignment == 0) Alignment = 1;
- // Since we do not know where the buffer will be allocated, be pessimistic.
- return FinalSize + Alignment;
-}
-
-unsigned
-JITDwarfEmitter::GetEHFrameSizeInBytes(const Function* Personality,
- unsigned char* StartFunction) const {
- unsigned PointerSize = TD->getPointerSize();
- unsigned FinalSize = 0;
- // EH frame header.
- FinalSize += PointerSize;
- // FDE CIE Offset
- FinalSize += 3 * PointerSize;
- // If there is a personality and landing pads then point to the language
- // specific data area in the exception table.
- if (Personality) {
- FinalSize += MCAsmInfo::getULEB128Size(4);
- FinalSize += PointerSize;
- } else {
- FinalSize += MCAsmInfo::getULEB128Size(0);
- }
-
- // Indicate locations of function specific callee saved registers in
- // frame.
- FinalSize += GetFrameMovesSizeInBytes((intptr_t)StartFunction,
- MMI->getFrameMoves());
-
- FinalSize = RoundUpToAlign(FinalSize, 4);
-
- // Double zeroes for the unwind runtime
- FinalSize += 2 * PointerSize;
-
- return FinalSize;
-}
-
-unsigned JITDwarfEmitter::GetCommonEHFrameSizeInBytes(const Function* Personality)
- const {
-
- unsigned PointerSize = TD->getPointerSize();
- int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
- PointerSize : -PointerSize;
- unsigned FinalSize = 0;
- // EH Common Frame header
- FinalSize += PointerSize;
- FinalSize += 4;
- FinalSize += 1;
- FinalSize += Personality ? 5 : 3; // "zPLR" or "zR"
- FinalSize += MCAsmInfo::getULEB128Size(1);
- FinalSize += MCAsmInfo::getSLEB128Size(stackGrowth);
- FinalSize += 1;
-
- if (Personality) {
- FinalSize += MCAsmInfo::getULEB128Size(7);
-
- // Encoding
- FinalSize+= 1;
- //Personality
- FinalSize += PointerSize;
-
- FinalSize += MCAsmInfo::getULEB128Size(dwarf::DW_EH_PE_pcrel);
- FinalSize += MCAsmInfo::getULEB128Size(dwarf::DW_EH_PE_pcrel);
-
- } else {
- FinalSize += MCAsmInfo::getULEB128Size(1);
- FinalSize += MCAsmInfo::getULEB128Size(dwarf::DW_EH_PE_pcrel);
- }
-
- std::vector<MachineMove> Moves;
- RI->getInitialFrameState(Moves);
- FinalSize += GetFrameMovesSizeInBytes(0, Moves);
- FinalSize = RoundUpToAlign(FinalSize, 4);
- return FinalSize;
-}
-
-unsigned
-JITDwarfEmitter::GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr,
- const std::vector<MachineMove> &Moves) const {
- unsigned PointerSize = TD->getPointerSize();
- int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
- PointerSize : -PointerSize;
- bool IsLocal = BaseLabelPtr;
- unsigned FinalSize = 0;
-
- for (unsigned i = 0, N = Moves.size(); i < N; ++i) {
- const MachineMove &Move = Moves[i];
- MCSymbol *Label = Move.getLabel();
-
- // Throw out move if the label is invalid.
- if (Label && (*JCE->getLabelLocations())[Label] == 0)
- continue;
-
- intptr_t LabelPtr = 0;
- if (Label) LabelPtr = JCE->getLabelAddress(Label);
-
- const MachineLocation &Dst = Move.getDestination();
- const MachineLocation &Src = Move.getSource();
-
- // Advance row if new location.
- if (BaseLabelPtr && Label && (BaseLabelPtr != LabelPtr || !IsLocal)) {
- FinalSize++;
- FinalSize += PointerSize;
- BaseLabelPtr = LabelPtr;
- IsLocal = true;
- }
-
- // If advancing cfa.
- if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
- if (!Src.isReg()) {
- if (Src.getReg() == MachineLocation::VirtualFP) {
- ++FinalSize;
- } else {
- ++FinalSize;
- unsigned RegNum = RI->getDwarfRegNum(Src.getReg(), true);
- FinalSize += MCAsmInfo::getULEB128Size(RegNum);
- }
-
- int Offset = -Src.getOffset();
-
- FinalSize += MCAsmInfo::getULEB128Size(Offset);
- } else {
- llvm_unreachable("Machine move no supported yet.");
- }
- } else if (Src.isReg() &&
- Src.getReg() == MachineLocation::VirtualFP) {
- if (Dst.isReg()) {
- ++FinalSize;
- unsigned RegNum = RI->getDwarfRegNum(Dst.getReg(), true);
- FinalSize += MCAsmInfo::getULEB128Size(RegNum);
- } else {
- llvm_unreachable("Machine move no supported yet.");
- }
- } else {
- unsigned Reg = RI->getDwarfRegNum(Src.getReg(), true);
- int Offset = Dst.getOffset() / stackGrowth;
-
- if (Offset < 0) {
- ++FinalSize;
- FinalSize += MCAsmInfo::getULEB128Size(Reg);
- FinalSize += MCAsmInfo::getSLEB128Size(Offset);
- } else if (Reg < 64) {
- ++FinalSize;
- FinalSize += MCAsmInfo::getULEB128Size(Offset);
- } else {
- ++FinalSize;
- FinalSize += MCAsmInfo::getULEB128Size(Reg);
- FinalSize += MCAsmInfo::getULEB128Size(Offset);
- }
- }
- }
- return FinalSize;
-}
-
-unsigned
-JITDwarfEmitter::GetExceptionTableSizeInBytes(MachineFunction* MF) const {
- unsigned FinalSize = 0;
-
- // Map all labels and get rid of any dead landing pads.
- MMI->TidyLandingPads(JCE->getLabelLocations());
-
- const std::vector<const GlobalVariable *> &TypeInfos = MMI->getTypeInfos();
- const std::vector<unsigned> &FilterIds = MMI->getFilterIds();
- const std::vector<LandingPadInfo> &PadInfos = MMI->getLandingPads();
- if (PadInfos.empty()) return 0;
-
- // Sort the landing pads in order of their type ids. This is used to fold
- // duplicate actions.
- SmallVector<const LandingPadInfo *, 64> LandingPads;
- LandingPads.reserve(PadInfos.size());
- for (unsigned i = 0, N = PadInfos.size(); i != N; ++i)
- LandingPads.push_back(&PadInfos[i]);
- std::sort(LandingPads.begin(), LandingPads.end(), PadLT);
-
- // Negative type ids index into FilterIds, positive type ids index into
- // TypeInfos. The value written for a positive type id is just the type
- // id itself. For a negative type id, however, the value written is the
- // (negative) byte offset of the corresponding FilterIds entry. The byte
- // offset is usually equal to the type id, because the FilterIds entries
- // are written using a variable width encoding which outputs one byte per
- // entry as long as the value written is not too large, but can differ.
- // This kind of complication does not occur for positive type ids because
- // type infos are output using a fixed width encoding.
- // FilterOffsets[i] holds the byte offset corresponding to FilterIds[i].
- SmallVector<int, 16> FilterOffsets;
- FilterOffsets.reserve(FilterIds.size());
- int Offset = -1;
- for(std::vector<unsigned>::const_iterator I = FilterIds.begin(),
- E = FilterIds.end(); I != E; ++I) {
- FilterOffsets.push_back(Offset);
- Offset -= MCAsmInfo::getULEB128Size(*I);
- }
-
- // Compute the actions table and gather the first action index for each
- // landing pad site.
- SmallVector<ActionEntry, 32> Actions;
- SmallVector<unsigned, 64> FirstActions;
- FirstActions.reserve(LandingPads.size());
-
- int FirstAction = 0;
- unsigned SizeActions = 0;
- for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
- const LandingPadInfo *LP = LandingPads[i];
- const std::vector<int> &TypeIds = LP->TypeIds;
- const unsigned NumShared = i ? SharedTypeIds(LP, LandingPads[i-1]) : 0;
- unsigned SizeSiteActions = 0;
-
- if (NumShared < TypeIds.size()) {
- unsigned SizeAction = 0;
- ActionEntry *PrevAction = 0;
-
- if (NumShared) {
- const unsigned SizePrevIds = LandingPads[i-1]->TypeIds.size();
- assert(Actions.size());
- PrevAction = &Actions.back();
- SizeAction = MCAsmInfo::getSLEB128Size(PrevAction->NextAction) +
- MCAsmInfo::getSLEB128Size(PrevAction->ValueForTypeID);
- for (unsigned j = NumShared; j != SizePrevIds; ++j) {
- SizeAction -= MCAsmInfo::getSLEB128Size(PrevAction->ValueForTypeID);
- SizeAction += -PrevAction->NextAction;
- PrevAction = PrevAction->Previous;
- }
- }
-
- // Compute the actions.
- for (unsigned I = NumShared, M = TypeIds.size(); I != M; ++I) {
- int TypeID = TypeIds[I];
- assert(-1-TypeID < (int)FilterOffsets.size() && "Unknown filter id!");
- int ValueForTypeID = TypeID < 0 ? FilterOffsets[-1 - TypeID] : TypeID;
- unsigned SizeTypeID = MCAsmInfo::getSLEB128Size(ValueForTypeID);
-
- int NextAction = SizeAction ? -(SizeAction + SizeTypeID) : 0;
- SizeAction = SizeTypeID + MCAsmInfo::getSLEB128Size(NextAction);
- SizeSiteActions += SizeAction;
-
- ActionEntry Action = {ValueForTypeID, NextAction, PrevAction};
- Actions.push_back(Action);
-
- PrevAction = &Actions.back();
- }
-
- // Record the first action of the landing pad site.
- FirstAction = SizeActions + SizeSiteActions - SizeAction + 1;
- } // else identical - re-use previous FirstAction
-
- FirstActions.push_back(FirstAction);
-
- // Compute this sites contribution to size.
- SizeActions += SizeSiteActions;
- }
-
- // Compute the call-site table. Entries must be ordered by address.
- SmallVector<CallSiteEntry, 64> CallSites;
-
- RangeMapType PadMap;
- for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
- const LandingPadInfo *LandingPad = LandingPads[i];
- for (unsigned j=0, E = LandingPad->BeginLabels.size(); j != E; ++j) {
- MCSymbol *BeginLabel = LandingPad->BeginLabels[j];
- assert(!PadMap.count(BeginLabel) && "Duplicate landing pad labels!");
- PadRange P = { i, j };
- PadMap[BeginLabel] = P;
- }
- }
-
- bool MayThrow = false;
- MCSymbol *LastLabel = 0;
- for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
- I != E; ++I) {
- for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
- MI != E; ++MI) {
- if (!MI->isLabel()) {
- MayThrow |= MI->getDesc().isCall();
- continue;
- }
-
- MCSymbol *BeginLabel = MI->getOperand(0).getMCSymbol();
-
- if (BeginLabel == LastLabel)
- MayThrow = false;
-
- RangeMapType::iterator L = PadMap.find(BeginLabel);
-
- if (L == PadMap.end())
- continue;
-
- PadRange P = L->second;
- const LandingPadInfo *LandingPad = LandingPads[P.PadIndex];
-
- assert(BeginLabel == LandingPad->BeginLabels[P.RangeIndex] &&
- "Inconsistent landing pad map!");
-
- // If some instruction between the previous try-range and this one may
- // throw, create a call-site entry with no landing pad for the region
- // between the try-ranges.
- if (MayThrow) {
- CallSiteEntry Site = {LastLabel, BeginLabel, 0, 0};
- CallSites.push_back(Site);
- }
-
- LastLabel = LandingPad->EndLabels[P.RangeIndex];
- CallSiteEntry Site = {BeginLabel, LastLabel,
- LandingPad->LandingPadLabel, FirstActions[P.PadIndex]};
-
- assert(Site.BeginLabel && Site.EndLabel && Site.PadLabel &&
- "Invalid landing pad!");
-
- // Try to merge with the previous call-site.
- if (CallSites.size()) {
- CallSiteEntry &Prev = CallSites.back();
- if (Site.PadLabel == Prev.PadLabel && Site.Action == Prev.Action) {
- // Extend the range of the previous entry.
- Prev.EndLabel = Site.EndLabel;
- continue;
- }
- }
-
- // Otherwise, create a new call-site.
- CallSites.push_back(Site);
- }
- }
- // If some instruction between the previous try-range and the end of the
- // function may throw, create a call-site entry with no landing pad for the
- // region following the try-range.
- if (MayThrow) {
- CallSiteEntry Site = {LastLabel, 0, 0, 0};
- CallSites.push_back(Site);
- }
-
- // Final tallies.
- unsigned SizeSites = CallSites.size() * (sizeof(int32_t) + // Site start.
- sizeof(int32_t) + // Site length.
- sizeof(int32_t)); // Landing pad.
- for (unsigned i = 0, e = CallSites.size(); i < e; ++i)
- SizeSites += MCAsmInfo::getULEB128Size(CallSites[i].Action);
-
- unsigned SizeTypes = TypeInfos.size() * TD->getPointerSize();
-
- unsigned TypeOffset = sizeof(int8_t) + // Call site format
- // Call-site table length
- MCAsmInfo::getULEB128Size(SizeSites) +
- SizeSites + SizeActions + SizeTypes;
-
- unsigned TotalSize = sizeof(int8_t) + // LPStart format
- sizeof(int8_t) + // TType format
- MCAsmInfo::getULEB128Size(TypeOffset) + // TType base offset
- TypeOffset;
-
- unsigned SizeAlign = (4 - TotalSize) & 3;
-
- // Begin the exception table.
- FinalSize = RoundUpToAlign(FinalSize, 4);
- for (unsigned i = 0; i != SizeAlign; ++i) {
- ++FinalSize;
- }
-
- unsigned PointerSize = TD->getPointerSize();
-
- // Emit the header.
- ++FinalSize;
- // Asm->EOL("LPStart format (DW_EH_PE_omit)");
- ++FinalSize;
- // Asm->EOL("TType format (DW_EH_PE_absptr)");
- ++FinalSize;
- // Asm->EOL("TType base offset");
- ++FinalSize;
- // Asm->EOL("Call site format (DW_EH_PE_udata4)");
- ++FinalSize;
- // Asm->EOL("Call-site table length");
-
- // Emit the landing pad site information.
- for (unsigned i = 0; i < CallSites.size(); ++i) {
- CallSiteEntry &S = CallSites[i];
-
- // Asm->EOL("Region start");
- FinalSize += PointerSize;
-
- //Asm->EOL("Region length");
- FinalSize += PointerSize;
-
- // Asm->EOL("Landing pad");
- FinalSize += PointerSize;
-
- FinalSize += MCAsmInfo::getULEB128Size(S.Action);
- // Asm->EOL("Action");
- }
-
- // Emit the actions.
- for (unsigned I = 0, N = Actions.size(); I != N; ++I) {
- ActionEntry &Action = Actions[I];
-
- //Asm->EOL("TypeInfo index");
- FinalSize += MCAsmInfo::getSLEB128Size(Action.ValueForTypeID);
- //Asm->EOL("Next action");
- FinalSize += MCAsmInfo::getSLEB128Size(Action.NextAction);
- }
-
- // Emit the type ids.
- for (unsigned M = TypeInfos.size(); M; --M) {
- // Asm->EOL("TypeInfo");
- FinalSize += PointerSize;
- }
-
- // Emit the filter typeids.
- for (unsigned j = 0, M = FilterIds.size(); j < M; ++j) {
- unsigned TypeID = FilterIds[j];
- FinalSize += MCAsmInfo::getULEB128Size(TypeID);
- //Asm->EOL("Filter TypeInfo index");
- }
-
- FinalSize = RoundUpToAlign(FinalSize, 4);
-
- return FinalSize;
-}
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.h (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITDwarfEmitter.h Sat Jul 31 19:59:02 2010
@@ -49,17 +49,6 @@
unsigned char* EndFunction,
unsigned char* ExceptionTable) const;
- unsigned GetExceptionTableSizeInBytes(MachineFunction* MF) const;
-
- unsigned
- GetFrameMovesSizeInBytes(intptr_t BaseLabelPtr,
- const std::vector<MachineMove> &Moves) const;
-
- unsigned GetCommonEHFrameSizeInBytes(const Function* Personality) const;
-
- unsigned GetEHFrameSizeInBytes(const Function* Personality,
- unsigned char* StartFunction) const;
-
public:
JITDwarfEmitter(JIT& jit);
@@ -71,11 +60,6 @@
unsigned char* &EHFramePtr);
- unsigned GetDwarfTableSizeInBytes(MachineFunction& F,
- JITCodeEmitter& JCE,
- unsigned char* StartFunction,
- unsigned char* EndFunction);
-
void setModuleInfo(MachineModuleInfo* Info) {
MMI = Info;
}
Modified: llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/ExecutionEngine/JIT/JITEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -831,7 +831,7 @@
if (DL.isUnknown()) return;
if (!BeforePrintingInsn) return;
- const LLVMContext& Context = EmissionDetails.MF->getFunction()->getContext();
+ const LLVMContext &Context = EmissionDetails.MF->getFunction()->getContext();
if (DL.getScope(Context) != 0 && PrevDL != DL) {
JITEvent_EmittedFunctionDetails::LineStart NextLine;
@@ -859,23 +859,6 @@
return Size;
}
-static unsigned GetJumpTableSizeInBytes(MachineJumpTableInfo *MJTI, JIT *jit) {
- const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
- if (JT.empty()) return 0;
-
- unsigned NumEntries = 0;
- for (unsigned i = 0, e = JT.size(); i != e; ++i)
- NumEntries += JT[i].MBBs.size();
-
- return NumEntries * MJTI->getEntrySize(*jit->getTargetData());
-}
-
-static uintptr_t RoundUpToAlign(uintptr_t Size, unsigned Alignment) {
- if (Alignment == 0) Alignment = 1;
- // Since we do not know where the buffer will be allocated, be pessimistic.
- return Size + Alignment;
-}
-
/// addSizeOfGlobal - add the size of the global (plus any alignment padding)
/// into the running total Size.
@@ -1044,43 +1027,8 @@
uintptr_t ActualSize = 0;
// Set the memory writable, if it's not already
MemMgr->setMemoryWritable();
- if (MemMgr->NeedsExactSize()) {
- DEBUG(dbgs() << "JIT: ExactSize\n");
- const TargetInstrInfo* TII = F.getTarget().getInstrInfo();
- MachineConstantPool *MCP = F.getConstantPool();
-
- // Ensure the constant pool/jump table info is at least 4-byte aligned.
- ActualSize = RoundUpToAlign(ActualSize, 16);
-
- // Add the alignment of the constant pool
- ActualSize = RoundUpToAlign(ActualSize, MCP->getConstantPoolAlignment());
-
- // Add the constant pool size
- ActualSize += GetConstantPoolSizeInBytes(MCP, TheJIT->getTargetData());
-
- if (MachineJumpTableInfo *MJTI = F.getJumpTableInfo()) {
- // Add the aligment of the jump table info
- ActualSize = RoundUpToAlign(ActualSize,
- MJTI->getEntryAlignment(*TheJIT->getTargetData()));
-
- // Add the jump table size
- ActualSize += GetJumpTableSizeInBytes(MJTI, TheJIT);
- }
-
- // Add the alignment for the function
- ActualSize = RoundUpToAlign(ActualSize,
- std::max(F.getFunction()->getAlignment(), 8U));
-
- // Add the function size
- ActualSize += TII->GetFunctionSizeInBytes(F);
-
- DEBUG(dbgs() << "JIT: ActualSize before globals " << ActualSize << "\n");
- // Add the size of the globals that will be allocated after this function.
- // These are all the ones referenced from this function that were not
- // previously allocated.
- ActualSize += GetSizeOfGlobalsInBytes(F);
- DEBUG(dbgs() << "JIT: ActualSize after globals " << ActualSize << "\n");
- } else if (SizeEstimate > 0) {
+
+ if (SizeEstimate > 0) {
// SizeEstimate will be non-zero on reallocation attempts.
ActualSize = SizeEstimate;
}
@@ -1268,9 +1216,6 @@
SavedBufferEnd = BufferEnd;
SavedCurBufferPtr = CurBufferPtr;
- if (MemMgr->NeedsExactSize())
- ActualSize = DE->GetDwarfTableSizeInBytes(F, *this, FnStart, FnEnd);
-
BufferBegin = CurBufferPtr = MemMgr->startExceptionTable(F.getFunction(),
ActualSize);
BufferEnd = BufferBegin+ActualSize;
Modified: llvm/branches/wendling/eh/lib/Linker/LinkModules.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Linker/LinkModules.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Linker/LinkModules.cpp (original)
+++ llvm/branches/wendling/eh/lib/Linker/LinkModules.cpp Sat Jul 31 19:59:02 2010
@@ -545,14 +545,10 @@
for (Module::const_named_metadata_iterator I = Src->named_metadata_begin(),
E = Src->named_metadata_end(); I != E; ++I) {
const NamedMDNode *SrcNMD = I;
- NamedMDNode *DestNMD = Dest->getNamedMetadata(SrcNMD->getName());
- if (!DestNMD)
- NamedMDNode::Create(SrcNMD, Dest);
- else {
- // Add Src elements into Dest node.
- for (unsigned i = 0, e = SrcNMD->getNumOperands(); i != e; ++i)
- DestNMD->addOperand(SrcNMD->getOperand(i));
- }
+ NamedMDNode *DestNMD = Dest->getOrInsertNamedMetadata(SrcNMD->getName());
+ // Add Src elements into Dest node.
+ for (unsigned i = 0, e = SrcNMD->getNumOperands(); i != e; ++i)
+ DestNMD->addOperand(SrcNMD->getOperand(i));
}
}
Modified: llvm/branches/wendling/eh/lib/MC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/MC/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -11,6 +11,7 @@
MCInst.cpp
MCInstPrinter.cpp
MCLabel.cpp
+ MCDwarf.cpp
MCLoggingStreamer.cpp
MCMachOStreamer.cpp
MCNullStreamer.cpp
Modified: llvm/branches/wendling/eh/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCAsmStreamer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCAsmStreamer.cpp Sat Jul 31 19:59:02 2010
@@ -31,7 +31,7 @@
formatted_raw_ostream &OS;
const MCAsmInfo &MAI;
OwningPtr<MCInstPrinter> InstPrinter;
- MCCodeEmitter *Emitter;
+ OwningPtr<MCCodeEmitter> Emitter;
SmallString<128> CommentToEmit;
raw_svector_ostream CommentStream;
Modified: llvm/branches/wendling/eh/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCAssembler.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCAssembler.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCAssembler.cpp Sat Jul 31 19:59:02 2010
@@ -178,8 +178,12 @@
MCFragment::MCFragment() : Kind(FragmentType(~0)) {
}
+MCFragment::~MCFragment() {
+}
+
MCFragment::MCFragment(FragmentType _Kind, MCSectionData *_Parent)
- : Kind(_Kind), Parent(_Parent), Atom(0), EffectiveSize(~UINT64_C(0))
+ : Kind(_Kind), Parent(_Parent), Atom(0), Offset(~UINT64_C(0)),
+ EffectiveSize(~UINT64_C(0))
{
if (Parent)
Parent->getFragmentList().push_back(this);
@@ -647,7 +651,7 @@
assert(OW->getStream().tell() - Start == Layout.getSectionFileSize(SD));
}
-void MCAssembler::Finish() {
+void MCAssembler::Finish(MCObjectWriter *Writer) {
DEBUG_WITH_TYPE("mc-dump", {
llvm::errs() << "assembler backend - pre-layout\n--\n";
dump(); });
@@ -717,9 +721,15 @@
dump(); });
uint64_t StartOffset = OS.tell();
- llvm::OwningPtr<MCObjectWriter> Writer(getBackend().createObjectWriter(OS));
- if (!Writer)
- report_fatal_error("unable to create object writer!");
+
+ llvm::OwningPtr<MCObjectWriter> OwnWriter(0);
+ if (Writer == 0) {
+ //no custom Writer_ : create the default one life-managed by OwningPtr
+ OwnWriter.reset(getBackend().createObjectWriter(OS));
+ Writer = OwnWriter.get();
+ if (!Writer)
+ report_fatal_error("unable to create object writer!");
+ }
// Allow the object writer a chance to perform post-layout binding (for
// example, to set the index fields in the symbol data).
Modified: llvm/branches/wendling/eh/lib/MC/MCContext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCContext.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCContext.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCContext.cpp Sat Jul 31 19:59:02 2010
@@ -14,6 +14,7 @@
#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCLabel.h"
+#include "llvm/MC/MCDwarf.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Twine.h"
using namespace llvm;
@@ -181,3 +182,63 @@
Entry.setValue(Result);
return Result;
}
+
+//===----------------------------------------------------------------------===//
+// Dwarf Management
+//===----------------------------------------------------------------------===//
+
+/// GetDwarfFile - takes a file name an number to place in the dwarf file and
+/// directory tables. If the file number has already been allocated it is an
+/// error and zero is returned and the client reports the error, else the
+/// allocated file number is returned. The file numbers may be in any order.
+unsigned MCContext::GetDwarfFile(StringRef FileName, unsigned FileNumber) {
+ // TODO: a FileNumber of zero says to use the next available file number.
+ // Note: in GenericAsmParser::ParseDirectiveFile() FileNumber was checked
+ // to not be less than one. This needs to be change to be not less than zero.
+
+ // Make space for this FileNumber in the MCDwarfFiles vector if needed.
+ if (FileNumber >= MCDwarfFiles.size()) {
+ MCDwarfFiles.resize(FileNumber + 1);
+ } else {
+ MCDwarfFile *&ExistingFile = MCDwarfFiles[FileNumber];
+ if (ExistingFile)
+ // It is an error to use see the same number more than once.
+ return 0;
+ }
+
+ // Get the new MCDwarfFile slot for this FileNumber.
+ MCDwarfFile *&File = MCDwarfFiles[FileNumber];
+
+ // Separate the directory part from the basename of the FileName.
+ std::pair<StringRef, StringRef> Slash = FileName.rsplit('/');
+
+ // Find or make a entry in the MCDwarfDirs vector for this Directory.
+ StringRef Name;
+ unsigned DirIndex;
+ // Capture directory name.
+ if (Slash.second.empty()) {
+ Name = Slash.first;
+ DirIndex = 0; // For FileNames with no directories a DirIndex of 0 is used.
+ } else {
+ StringRef Directory = Slash.first;
+ Name = Slash.second;
+ for (DirIndex = 1; DirIndex < MCDwarfDirs.size(); DirIndex++) {
+ if (Directory == MCDwarfDirs[DirIndex])
+ break;
+ }
+ if (DirIndex >= MCDwarfDirs.size()) {
+ char *Buf = static_cast<char *>(Allocate(Directory.size()));
+ memcpy(Buf, Directory.data(), Directory.size());
+ MCDwarfDirs.push_back(StringRef(Buf, Directory.size()));
+ }
+ }
+
+ // Now make the MCDwarfFile entry and place it in the slot in the MCDwarfFiles
+ // vector.
+ char *Buf = static_cast<char *>(Allocate(Name.size()));
+ memcpy(Buf, Name.data(), Name.size());
+ File = new (*this) MCDwarfFile(StringRef(Buf, Name.size()), DirIndex);
+
+ // return the allocated FileNumber.
+ return FileNumber;
+}
Propchange: llvm/branches/wendling/eh/lib/MC/MCDisassembler/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -0,0 +1,9 @@
+Debug
+Debug+Checks
+Debug+Coverage
+Debug+Coverage-Asserts
+Release
+Release-Asserts
+Release+Coverage
+Debug+Asserts
+Release+Asserts
Modified: llvm/branches/wendling/eh/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCMachOStreamer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCMachOStreamer.cpp Sat Jul 31 19:59:02 2010
@@ -28,24 +28,6 @@
class MCMachOStreamer : public MCObjectStreamer {
private:
- MCFragment *getCurrentFragment() const {
- assert(getCurrentSectionData() && "No current section!");
-
- if (!getCurrentSectionData()->empty())
- return &getCurrentSectionData()->getFragmentList().back();
-
- return 0;
- }
-
- /// Get a data fragment to write into, creating a new one if the current
- /// fragment is not a data fragment.
- MCDataFragment *getOrCreateDataFragment() const {
- MCDataFragment *F = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
- if (!F)
- F = new MCDataFragment(getCurrentSectionData());
- return F;
- }
-
void EmitInstToFragment(const MCInst &Inst);
void EmitInstToData(const MCInst &Inst);
@@ -54,32 +36,6 @@
raw_ostream &OS, MCCodeEmitter *Emitter)
: MCObjectStreamer(Context, TAB, OS, Emitter) {}
- const MCExpr *AddValueSymbols(const MCExpr *Value) {
- switch (Value->getKind()) {
- case MCExpr::Target: assert(0 && "Can't handle target exprs yet!");
- case MCExpr::Constant:
- break;
-
- case MCExpr::Binary: {
- const MCBinaryExpr *BE = cast<MCBinaryExpr>(Value);
- AddValueSymbols(BE->getLHS());
- AddValueSymbols(BE->getRHS());
- break;
- }
-
- case MCExpr::SymbolRef:
- getAssembler().getOrCreateSymbolData(
- cast<MCSymbolRefExpr>(Value)->getSymbol());
- break;
-
- case MCExpr::Unary:
- AddValueSymbols(cast<MCUnaryExpr>(Value)->getSubExpr());
- break;
- }
-
- return Value;
- }
-
/// @name MCStreamer Interface
/// @{
@@ -126,10 +82,16 @@
unsigned char Value = 0);
virtual void EmitFileDirective(StringRef Filename) {
- report_fatal_error("unsupported directive: '.file'");
+ // FIXME: Just ignore the .file; it isn't important enough to fail the
+ // entire assembly.
+
+ //report_fatal_error("unsupported directive: '.file'");
}
virtual void EmitDwarfFileDirective(unsigned FileNo, StringRef Filename) {
- report_fatal_error("unsupported directive: '.file'");
+ // FIXME: Just ignore the .file; it isn't important enough to fail the
+ // entire assembly.
+
+ //report_fatal_error("unsupported directive: '.file'");
}
virtual void EmitInstruction(const MCInst &Inst);
@@ -142,6 +104,8 @@
} // end anonymous namespace.
void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) {
+ // TODO: This is almost exactly the same as WinCOFFStreamer. Consider merging
+ // into MCObjectStreamer.
assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
assert(!Symbol->isVariable() && "Cannot emit a variable symbol!");
assert(CurSection && "Cannot emit before setting section!");
@@ -185,6 +149,8 @@
}
void MCMachOStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
+ // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
+ // MCObjectStreamer.
// FIXME: Lift context changes into super class.
getAssembler().getOrCreateSymbolData(*Symbol);
Symbol->setVariableValue(AddValueSymbols(Value));
@@ -335,11 +301,15 @@
}
void MCMachOStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
+ // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
+ // MCObjectStreamer.
getOrCreateDataFragment()->getContents().append(Data.begin(), Data.end());
}
void MCMachOStreamer::EmitValue(const MCExpr *Value, unsigned Size,
unsigned AddrSpace) {
+ // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
+ // MCObjectStreamer.
MCDataFragment *DF = getOrCreateDataFragment();
// Avoid fixups when possible.
@@ -359,6 +329,8 @@
void MCMachOStreamer::EmitValueToAlignment(unsigned ByteAlignment,
int64_t Value, unsigned ValueSize,
unsigned MaxBytesToEmit) {
+ // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
+ // MCObjectStreamer.
if (MaxBytesToEmit == 0)
MaxBytesToEmit = ByteAlignment;
new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit,
@@ -371,6 +343,8 @@
void MCMachOStreamer::EmitCodeAlignment(unsigned ByteAlignment,
unsigned MaxBytesToEmit) {
+ // TODO: This is exactly the same as WinCOFFStreamer. Consider merging into
+ // MCObjectStreamer.
if (MaxBytesToEmit == 0)
MaxBytesToEmit = ByteAlignment;
MCAlignFragment *F = new MCAlignFragment(ByteAlignment, 0, 1, MaxBytesToEmit,
Modified: llvm/branches/wendling/eh/lib/MC/MCObjectStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCObjectStreamer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCObjectStreamer.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCObjectStreamer.cpp Sat Jul 31 19:59:02 2010
@@ -9,7 +9,11 @@
#include "llvm/MC/MCObjectStreamer.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/Target/TargetAsmBackend.h"
using namespace llvm;
MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB,
@@ -21,9 +25,52 @@
}
MCObjectStreamer::~MCObjectStreamer() {
+ delete &Assembler->getBackend();
+ delete &Assembler->getEmitter();
delete Assembler;
}
+MCFragment *MCObjectStreamer::getCurrentFragment() const {
+ assert(getCurrentSectionData() && "No current section!");
+
+ if (!getCurrentSectionData()->empty())
+ return &getCurrentSectionData()->getFragmentList().back();
+
+ return 0;
+}
+
+MCDataFragment *MCObjectStreamer::getOrCreateDataFragment() const {
+ MCDataFragment *F = dyn_cast_or_null<MCDataFragment>(getCurrentFragment());
+ if (!F)
+ F = new MCDataFragment(getCurrentSectionData());
+ return F;
+}
+
+const MCExpr *MCObjectStreamer::AddValueSymbols(const MCExpr *Value) {
+ switch (Value->getKind()) {
+ case MCExpr::Target: llvm_unreachable("Can't handle target exprs yet!");
+ case MCExpr::Constant:
+ break;
+
+ case MCExpr::Binary: {
+ const MCBinaryExpr *BE = cast<MCBinaryExpr>(Value);
+ AddValueSymbols(BE->getLHS());
+ AddValueSymbols(BE->getRHS());
+ break;
+ }
+
+ case MCExpr::SymbolRef:
+ Assembler->getOrCreateSymbolData(cast<MCSymbolRefExpr>(Value)->getSymbol());
+ break;
+
+ case MCExpr::Unary:
+ AddValueSymbols(cast<MCUnaryExpr>(Value)->getSubExpr());
+ break;
+ }
+
+ return Value;
+}
+
void MCObjectStreamer::SwitchSection(const MCSection *Section) {
assert(Section && "Cannot switch to a null section!");
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/AsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/AsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -11,47 +11,237 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/MC/MCParser/AsmParser.h"
#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCParser/AsmCond.h"
+#include "llvm/MC/MCParser/AsmLexer.h"
+#include "llvm/MC/MCParser/MCAsmParser.h"
+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCDwarf.h"
#include "llvm/Support/Compiler.h"
-#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetAsmParser.h"
+#include <vector>
using namespace llvm;
namespace {
+/// \brief Helper class for tracking macro definitions.
+struct Macro {
+ StringRef Name;
+ StringRef Body;
+
+public:
+ Macro(StringRef N, StringRef B) : Name(N), Body(B) {}
+};
+
+/// \brief Helper class for storing information about an active macro
+/// instantiation.
+struct MacroInstantiation {
+ /// The macro being instantiated.
+ const Macro *TheMacro;
+
+ /// The macro instantiation with substitutions.
+ MemoryBuffer *Instantiation;
+
+ /// The location of the instantiation.
+ SMLoc InstantiationLoc;
+
+ /// The location where parsing should resume upon instantiation completion.
+ SMLoc ExitLoc;
+
+public:
+ MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL,
+ const std::vector<std::vector<AsmToken> > &A);
+};
+
+/// \brief The concrete assembly parser instance.
+class AsmParser : public MCAsmParser {
+ friend class GenericAsmParser;
+
+ AsmParser(const AsmParser &); // DO NOT IMPLEMENT
+ void operator=(const AsmParser &); // DO NOT IMPLEMENT
+private:
+ AsmLexer Lexer;
+ MCContext &Ctx;
+ MCStreamer &Out;
+ SourceMgr &SrcMgr;
+ MCAsmParserExtension *GenericParser;
+ MCAsmParserExtension *PlatformParser;
+
+ /// This is the current buffer index we're lexing from as managed by the
+ /// SourceMgr object.
+ int CurBuffer;
+
+ AsmCond TheCondState;
+ std::vector<AsmCond> TheCondStack;
+
+ /// DirectiveMap - This is a table handlers for directives. Each handler is
+ /// invoked after the directive identifier is read and is responsible for
+ /// parsing and validating the rest of the directive. The handler is passed
+ /// in the directive name and the location of the directive keyword.
+ StringMap<std::pair<MCAsmParserExtension*, DirectiveHandler> > DirectiveMap;
+
+ /// MacroMap - Map of currently defined macros.
+ StringMap<Macro*> MacroMap;
+
+ /// ActiveMacros - Stack of active macro instantiations.
+ std::vector<MacroInstantiation*> ActiveMacros;
+
+ /// Boolean tracking whether macro substitution is enabled.
+ unsigned MacrosEnabled : 1;
+
+public:
+ AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
+ const MCAsmInfo &MAI);
+ ~AsmParser();
+
+ virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false);
+
+ void AddDirectiveHandler(MCAsmParserExtension *Object,
+ StringRef Directive,
+ DirectiveHandler Handler) {
+ DirectiveMap[Directive] = std::make_pair(Object, Handler);
+ }
+
+public:
+ /// @name MCAsmParser Interface
+ /// {
+
+ virtual SourceMgr &getSourceManager() { return SrcMgr; }
+ virtual MCAsmLexer &getLexer() { return Lexer; }
+ virtual MCContext &getContext() { return Ctx; }
+ virtual MCStreamer &getStreamer() { return Out; }
+
+ virtual void Warning(SMLoc L, const Twine &Meg);
+ virtual bool Error(SMLoc L, const Twine &Msg);
+
+ const AsmToken &Lex();
+
+ bool ParseExpression(const MCExpr *&Res);
+ virtual bool ParseExpression(const MCExpr *&Res, SMLoc &EndLoc);
+ virtual bool ParseParenExpression(const MCExpr *&Res, SMLoc &EndLoc);
+ virtual bool ParseAbsoluteExpression(int64_t &Res);
+
+ /// }
+
+private:
+ bool ParseStatement();
+
+ bool HandleMacroEntry(StringRef Name, SMLoc NameLoc, const Macro *M);
+ void HandleMacroExit();
+
+ void PrintMacroInstantiations();
+ void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const;
+
+ /// EnterIncludeFile - Enter the specified file. This returns true on failure.
+ bool EnterIncludeFile(const std::string &Filename);
+
+ /// \brief Reset the current lexer position to that given by \arg Loc. The
+ /// current token is not set; clients should ensure Lex() is called
+ /// subsequently.
+ void JumpToLoc(SMLoc Loc);
+
+ void EatToEndOfStatement();
+
+ /// \brief Parse up to the end of statement and a return the contents from the
+ /// current token until the end of the statement; the current token on exit
+ /// will be either the EndOfStatement or EOF.
+ StringRef ParseStringToEndOfStatement();
+
+ bool ParseAssignment(StringRef Name);
+
+ bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc);
+ bool ParseBinOpRHS(unsigned Precedence, const MCExpr *&Res, SMLoc &EndLoc);
+ bool ParseParenExpr(const MCExpr *&Res, SMLoc &EndLoc);
+
+ /// ParseIdentifier - Parse an identifier or string (as a quoted identifier)
+ /// and set \arg Res to the identifier contents.
+ bool ParseIdentifier(StringRef &Res);
+
+ // Directive Parsing.
+ bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz"
+ bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ...
+ bool ParseDirectiveFill(); // ".fill"
+ bool ParseDirectiveSpace(); // ".space"
+ bool ParseDirectiveSet(); // ".set"
+ bool ParseDirectiveOrg(); // ".org"
+ // ".align{,32}", ".p2align{,w,l}"
+ bool ParseDirectiveAlign(bool IsPow2, unsigned ValueSize);
+
+ /// ParseDirectiveSymbolAttribute - Parse a directive like ".globl" which
+ /// accepts a single symbol (which should be a label or an external).
+ bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr);
+ bool ParseDirectiveELFType(); // ELF specific ".type"
+
+ bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm"
+
+ bool ParseDirectiveAbort(); // ".abort"
+ bool ParseDirectiveInclude(); // ".include"
+
+ bool ParseDirectiveIf(SMLoc DirectiveLoc); // ".if"
+ bool ParseDirectiveElseIf(SMLoc DirectiveLoc); // ".elseif"
+ bool ParseDirectiveElse(SMLoc DirectiveLoc); // ".else"
+ bool ParseDirectiveEndIf(SMLoc DirectiveLoc); // .endif
+
+ /// ParseEscapedString - Parse the current token as a string which may include
+ /// escaped characters and return the string contents.
+ bool ParseEscapedString(std::string &Data);
+};
+
/// \brief Generic implementations of directive handling, etc. which is shared
/// (or the default, at least) for all assembler parser.
class GenericAsmParser : public MCAsmParserExtension {
+ template<bool (GenericAsmParser::*Handler)(StringRef, SMLoc)>
+ void AddDirectiveHandler(StringRef Directive) {
+ getParser().AddDirectiveHandler(this, Directive,
+ HandleDirective<GenericAsmParser, Handler>);
+ }
+
public:
GenericAsmParser() {}
+ AsmParser &getParser() {
+ return (AsmParser&) this->MCAsmParserExtension::getParser();
+ }
+
virtual void Initialize(MCAsmParser &Parser) {
// Call the base implementation.
this->MCAsmParserExtension::Initialize(Parser);
// Debugging directives.
- Parser.AddDirectiveHandler(this, ".file", MCAsmParser::DirectiveHandler(
- &GenericAsmParser::ParseDirectiveFile));
- Parser.AddDirectiveHandler(this, ".line", MCAsmParser::DirectiveHandler(
- &GenericAsmParser::ParseDirectiveLine));
- Parser.AddDirectiveHandler(this, ".loc", MCAsmParser::DirectiveHandler(
- &GenericAsmParser::ParseDirectiveLoc));
- }
-
- bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); // ".file"
- bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); // ".line"
- bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc"
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveFile>(".file");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLine>(".line");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLoc>(".loc");
+
+ // Macro directives.
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacrosOnOff>(
+ ".macros_on");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacrosOnOff>(
+ ".macros_off");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacro>(".macro");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endm");
+ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endmacro");
+ }
+
+ bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc);
+ bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc);
+ bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc);
+
+ bool ParseDirectiveMacrosOnOff(StringRef, SMLoc DirectiveLoc);
+ bool ParseDirectiveMacro(StringRef, SMLoc DirectiveLoc);
+ bool ParseDirectiveEndMacro(StringRef, SMLoc DirectiveLoc);
};
}
@@ -69,7 +259,7 @@
MCStreamer &_Out, const MCAsmInfo &_MAI)
: Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM),
GenericParser(new GenericAsmParser), PlatformParser(0),
- TargetParser(0), CurBuffer(0) {
+ CurBuffer(0), MacrosEnabled(true) {
Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer));
// Initialize the generic parser.
@@ -89,22 +279,33 @@
}
AsmParser::~AsmParser() {
+ assert(ActiveMacros.empty() && "Unexpected active macro instantiation!");
+
+ // Destroy any macros.
+ for (StringMap<Macro*>::iterator it = MacroMap.begin(),
+ ie = MacroMap.end(); it != ie; ++it)
+ delete it->getValue();
+
delete PlatformParser;
delete GenericParser;
}
-void AsmParser::setTargetParser(TargetAsmParser &P) {
- assert(!TargetParser && "Target parser is already initialized!");
- TargetParser = &P;
- TargetParser->Initialize(*this);
+void AsmParser::PrintMacroInstantiations() {
+ // Print the active macro instantiation stack.
+ for (std::vector<MacroInstantiation*>::const_reverse_iterator
+ it = ActiveMacros.rbegin(), ie = ActiveMacros.rend(); it != ie; ++it)
+ PrintMessage((*it)->InstantiationLoc, "while in macro instantiation",
+ "note");
}
void AsmParser::Warning(SMLoc L, const Twine &Msg) {
PrintMessage(L, Msg.str(), "warning");
+ PrintMacroInstantiations();
}
bool AsmParser::Error(SMLoc L, const Twine &Msg) {
PrintMessage(L, Msg.str(), "error");
+ PrintMacroInstantiations();
return true;
}
@@ -124,7 +325,12 @@
return false;
}
-
+
+void AsmParser::JumpToLoc(SMLoc Loc) {
+ CurBuffer = SrcMgr.FindBufferContainingLoc(Loc);
+ Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer), Loc.getPointer());
+}
+
const AsmToken &AsmParser::Lex() {
const AsmToken *tok = &Lexer.Lex();
@@ -133,15 +339,13 @@
// include stack.
SMLoc ParentIncludeLoc = SrcMgr.getParentIncludeLoc(CurBuffer);
if (ParentIncludeLoc != SMLoc()) {
- CurBuffer = SrcMgr.FindBufferContainingLoc(ParentIncludeLoc);
- Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer),
- ParentIncludeLoc.getPointer());
+ JumpToLoc(ParentIncludeLoc);
tok = &Lexer.Lex();
}
}
if (tok->is(AsmToken::Error))
- PrintMessage(Lexer.getErrLoc(), Lexer.getErr(), "error");
+ Error(Lexer.getErrLoc(), Lexer.getErr());
return *tok;
}
@@ -174,6 +378,16 @@
if (TheCondState.TheCond != StartingCondState.TheCond ||
TheCondState.Ignore != StartingCondState.Ignore)
return TokError("unmatched .ifs or .elses");
+
+ // Check to see there are no empty DwarfFile slots.
+ const std::vector<MCDwarfFile *> &MCDwarfFiles =
+ getContext().getMCDwarfFiles();
+ for (unsigned i = 1; i < MCDwarfFiles.size(); i++) {
+ if (!MCDwarfFiles[i]){
+ TokError("unassigned file number: " + Twine(i) + " for .file directives");
+ HadError = true;
+ }
+ }
// Finalize the output stream if there are no errors and if the client wants
// us to.
@@ -194,6 +408,16 @@
Lex();
}
+StringRef AsmParser::ParseStringToEndOfStatement() {
+ const char *Start = getTok().getLoc().getPointer();
+
+ while (Lexer.isNot(AsmToken::EndOfStatement) &&
+ Lexer.isNot(AsmToken::Eof))
+ Lex();
+
+ const char *End = getTok().getLoc().getPointer();
+ return StringRef(Start, End - Start);
+}
/// ParseParenExpr - Parse a paren expression and return it.
/// NOTE: This assumes the leading '(' has already been consumed.
@@ -568,7 +792,12 @@
default: // Normal instruction or directive.
break;
}
-
+
+ // If macros are enabled, check to see if this is a macro instantiation.
+ if (MacrosEnabled)
+ if (const Macro *M = MacroMap.lookup(IDVal))
+ return HandleMacroEntry(IDVal, IDLoc, M);
+
// Otherwise, we have a normal instruction or directive.
if (IDVal[0] == '.') {
// Assembler features
@@ -591,11 +820,14 @@
if (IDVal == ".quad")
return ParseDirectiveValue(8);
- // FIXME: Target hooks for IsPow2.
- if (IDVal == ".align")
- return ParseDirectiveAlign(/*IsPow2=*/true, /*ExprSize=*/1);
- if (IDVal == ".align32")
- return ParseDirectiveAlign(/*IsPow2=*/true, /*ExprSize=*/4);
+ if (IDVal == ".align") {
+ bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
+ return ParseDirectiveAlign(IsPow2, /*ExprSize=*/1);
+ }
+ if (IDVal == ".align32") {
+ bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
+ return ParseDirectiveAlign(IsPow2, /*ExprSize=*/4);
+ }
if (IDVal == ".balign")
return ParseDirectiveAlign(/*IsPow2=*/false, /*ExprSize=*/1);
if (IDVal == ".balignw")
@@ -662,7 +894,7 @@
std::pair<MCAsmParserExtension*, DirectiveHandler> Handler =
DirectiveMap.lookup(IDVal);
if (Handler.first)
- return (Handler.first->*Handler.second)(IDVal, IDLoc);
+ return (*Handler.second)(Handler.first, IDVal, IDLoc);
// Target hook for parsing target specific directives.
if (!getTargetParser().ParseDirective(ID))
@@ -712,6 +944,130 @@
return HadError;
}
+MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL,
+ const std::vector<std::vector<AsmToken> > &A)
+ : TheMacro(M), InstantiationLoc(IL), ExitLoc(EL)
+{
+ // Macro instantiation is lexical, unfortunately. We construct a new buffer
+ // to hold the macro body with substitutions.
+ SmallString<256> Buf;
+ raw_svector_ostream OS(Buf);
+
+ StringRef Body = M->Body;
+ while (!Body.empty()) {
+ // Scan for the next substitution.
+ std::size_t End = Body.size(), Pos = 0;
+ for (; Pos != End; ++Pos) {
+ // Check for a substitution or escape.
+ if (Body[Pos] != '$' || Pos + 1 == End)
+ continue;
+
+ char Next = Body[Pos + 1];
+ if (Next == '$' || Next == 'n' || isdigit(Next))
+ break;
+ }
+
+ // Add the prefix.
+ OS << Body.slice(0, Pos);
+
+ // Check if we reached the end.
+ if (Pos == End)
+ break;
+
+ switch (Body[Pos+1]) {
+ // $$ => $
+ case '$':
+ OS << '$';
+ break;
+
+ // $n => number of arguments
+ case 'n':
+ OS << A.size();
+ break;
+
+ // $[0-9] => argument
+ default: {
+ // Missing arguments are ignored.
+ unsigned Index = Body[Pos+1] - '0';
+ if (Index >= A.size())
+ break;
+
+ // Otherwise substitute with the token values, with spaces eliminated.
+ for (std::vector<AsmToken>::const_iterator it = A[Index].begin(),
+ ie = A[Index].end(); it != ie; ++it)
+ OS << it->getString();
+ break;
+ }
+ }
+
+ // Update the scan point.
+ Body = Body.substr(Pos + 2);
+ }
+
+ // We include the .endmacro in the buffer as our queue to exit the macro
+ // instantiation.
+ OS << ".endmacro\n";
+
+ Instantiation = MemoryBuffer::getMemBufferCopy(OS.str(), "<instantiation>");
+}
+
+bool AsmParser::HandleMacroEntry(StringRef Name, SMLoc NameLoc,
+ const Macro *M) {
+ // Arbitrarily limit macro nesting depth, to match 'as'. We can eliminate
+ // this, although we should protect against infinite loops.
+ if (ActiveMacros.size() == 20)
+ return TokError("macros cannot be nested more than 20 levels deep");
+
+ // Parse the macro instantiation arguments.
+ std::vector<std::vector<AsmToken> > MacroArguments;
+ MacroArguments.push_back(std::vector<AsmToken>());
+ unsigned ParenLevel = 0;
+ for (;;) {
+ if (Lexer.is(AsmToken::Eof))
+ return TokError("unexpected token in macro instantiation");
+ if (Lexer.is(AsmToken::EndOfStatement))
+ break;
+
+ // If we aren't inside parentheses and this is a comma, start a new token
+ // list.
+ if (ParenLevel == 0 && Lexer.is(AsmToken::Comma)) {
+ MacroArguments.push_back(std::vector<AsmToken>());
+ } else if (Lexer.is(AsmToken::LParen)) {
+ ++ParenLevel;
+ } else if (Lexer.is(AsmToken::RParen)) {
+ if (ParenLevel)
+ --ParenLevel;
+ } else {
+ MacroArguments.back().push_back(getTok());
+ }
+ Lex();
+ }
+
+ // Create the macro instantiation object and add to the current macro
+ // instantiation stack.
+ MacroInstantiation *MI = new MacroInstantiation(M, NameLoc,
+ getTok().getLoc(),
+ MacroArguments);
+ ActiveMacros.push_back(MI);
+
+ // Jump to the macro instantiation and prime the lexer.
+ CurBuffer = SrcMgr.AddNewSourceBuffer(MI->Instantiation, SMLoc());
+ Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer));
+ Lex();
+
+ return false;
+}
+
+void AsmParser::HandleMacroExit() {
+ // Jump to the EndOfStatement we should return to, and consume it.
+ JumpToLoc(ActiveMacros.back()->ExitLoc);
+ Lex();
+
+ // Pop the instantiation entry.
+ delete ActiveMacros.back();
+ ActiveMacros.pop_back();
+}
+
bool AsmParser::ParseAssignment(StringRef Name) {
// FIXME: Use better location, we should use proper tokens.
SMLoc EqualLoc = Lexer.getLoc();
@@ -1081,13 +1437,14 @@
bool UseCodeAlign = false;
if (const MCSectionMachO *S = dyn_cast<MCSectionMachO>(
getStreamer().getCurrentSection()))
- UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS);
+ UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS);
if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) &&
ValueSize == 1 && UseCodeAlign) {
getStreamer().EmitCodeAlignment(Alignment, MaxBytesToFill);
} else {
// FIXME: Target specific behavior about how the "extra" bytes are filled.
- getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize, MaxBytesToFill);
+ getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize,
+ MaxBytesToFill);
}
return false;
@@ -1238,31 +1595,22 @@
}
/// ParseDirectiveAbort
-/// ::= .abort [ "abort_string" ]
+/// ::= .abort [... message ...]
bool AsmParser::ParseDirectiveAbort() {
// FIXME: Use loc from directive.
SMLoc Loc = getLexer().getLoc();
- StringRef Str = "";
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- if (getLexer().isNot(AsmToken::String))
- return TokError("expected string in '.abort' directive");
-
- Str = getTok().getString();
-
- Lex();
- }
-
+ StringRef Str = ParseStringToEndOfStatement();
if (getLexer().isNot(AsmToken::EndOfStatement))
return TokError("unexpected token in '.abort' directive");
-
+
Lex();
- // FIXME: Handle here.
if (Str.empty())
Error(Loc, ".abort detected. Assembly stopping.");
else
Error(Loc, ".abort '" + Str + "' detected. Assembly stopping.");
+ // FIXME: Actually abort assembly here.
return false;
}
@@ -1286,9 +1634,7 @@
// Attempt to switch the lexer to the included file before consuming the end
// of statement to avoid losing it when we switch.
if (EnterIncludeFile(Filename)) {
- PrintMessage(IncludeLoc,
- "Could not find include file '" + Filename + "'",
- "error");
+ Error(IncludeLoc, "Could not find include file '" + Filename + "'");
return true;
}
@@ -1401,6 +1747,7 @@
bool GenericAsmParser::ParseDirectiveFile(StringRef, SMLoc DirectiveLoc) {
// FIXME: I'm not sure what this is.
int64_t FileNumber = -1;
+ SMLoc FileNumberLoc = getLexer().getLoc();
if (getLexer().is(AsmToken::Integer)) {
FileNumber = getTok().getIntVal();
Lex();
@@ -1421,8 +1768,11 @@
if (FileNumber == -1)
getStreamer().EmitFileDirective(Filename);
- else
+ else {
+ if (getContext().GetDwarfFile(Filename, FileNumber) == 0)
+ Error(FileNumberLoc, "file number already allocated");
getStreamer().EmitDwarfFileDirective(FileNumber, Filename);
+ }
return false;
}
@@ -1486,3 +1836,93 @@
return false;
}
+/// ParseDirectiveMacrosOnOff
+/// ::= .macros_on
+/// ::= .macros_off
+bool GenericAsmParser::ParseDirectiveMacrosOnOff(StringRef Directive,
+ SMLoc DirectiveLoc) {
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(getLexer().getLoc(),
+ "unexpected token in '" + Directive + "' directive");
+
+ getParser().MacrosEnabled = Directive == ".macros_on";
+
+ return false;
+}
+
+/// ParseDirectiveMacro
+/// ::= .macro name
+bool GenericAsmParser::ParseDirectiveMacro(StringRef Directive,
+ SMLoc DirectiveLoc) {
+ StringRef Name;
+ if (getParser().ParseIdentifier(Name))
+ return TokError("expected identifier in directive");
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in '.macro' directive");
+
+ // Eat the end of statement.
+ Lex();
+
+ AsmToken EndToken, StartToken = getTok();
+
+ // Lex the macro definition.
+ for (;;) {
+ // Check whether we have reached the end of the file.
+ if (getLexer().is(AsmToken::Eof))
+ return Error(DirectiveLoc, "no matching '.endmacro' in definition");
+
+ // Otherwise, check whether we have reach the .endmacro.
+ if (getLexer().is(AsmToken::Identifier) &&
+ (getTok().getIdentifier() == ".endm" ||
+ getTok().getIdentifier() == ".endmacro")) {
+ EndToken = getTok();
+ Lex();
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in '" + EndToken.getIdentifier() +
+ "' directive");
+ break;
+ }
+
+ // Otherwise, scan til the end of the statement.
+ getParser().EatToEndOfStatement();
+ }
+
+ if (getParser().MacroMap.lookup(Name)) {
+ return Error(DirectiveLoc, "macro '" + Name + "' is already defined");
+ }
+
+ const char *BodyStart = StartToken.getLoc().getPointer();
+ const char *BodyEnd = EndToken.getLoc().getPointer();
+ StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart);
+ getParser().MacroMap[Name] = new Macro(Name, Body);
+ return false;
+}
+
+/// ParseDirectiveEndMacro
+/// ::= .endm
+/// ::= .endmacro
+bool GenericAsmParser::ParseDirectiveEndMacro(StringRef Directive,
+ SMLoc DirectiveLoc) {
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in '" + Directive + "' directive");
+
+ // If we are inside a macro instantiation, terminate the current
+ // instantiation.
+ if (!getParser().ActiveMacros.empty()) {
+ getParser().HandleMacroExit();
+ return false;
+ }
+
+ // Otherwise, this .endmacro is a stray entry in the file; well formed
+ // .endmacro directives are handled during the macro definition parsing.
+ return TokError("unexpected '" + Directive + "' in file, "
+ "no current macro definition");
+}
+
+/// \brief Create an MCAsmParser instance.
+MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM,
+ MCContext &C, MCStreamer &Out,
+ const MCAsmInfo &MAI) {
+ return new AsmParser(T, SM, C, Out, MAI);
+}
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/DarwinAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/DarwinAsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/DarwinAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/DarwinAsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -25,6 +25,12 @@
/// \brief Implementation of directive handling which is shared across all
/// Darwin targets.
class DarwinAsmParser : public MCAsmParserExtension {
+ template<bool (DarwinAsmParser::*Handler)(StringRef, SMLoc)>
+ void AddDirectiveHandler(StringRef Directive) {
+ getParser().AddDirectiveHandler(this, Directive,
+ HandleDirective<DarwinAsmParser, Handler>);
+ }
+
bool ParseSectionSwitch(const char *Segment, const char *Section,
unsigned TAA = 0, unsigned ImplicitAlign = 0,
unsigned StubSize = 0);
@@ -36,168 +42,70 @@
// Call the base implementation.
this->MCAsmParserExtension::Initialize(Parser);
- Parser.AddDirectiveHandler(this, ".desc", MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveDesc));
- Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveLsym));
- Parser.AddDirectiveHandler(this, ".subsections_via_symbols",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols));
- Parser.AddDirectiveHandler(this, ".dump", MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveDumpOrLoad));
- Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveDumpOrLoad));
- Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveSection));
- Parser.AddDirectiveHandler(this, ".secure_log_unique",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveSecureLogUnique));
- Parser.AddDirectiveHandler(this, ".secure_log_reset",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveSecureLogReset));
- Parser.AddDirectiveHandler(this, ".tbss",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveTBSS));
- Parser.AddDirectiveHandler(this, ".zerofill",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseDirectiveZerofill));
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDesc>(".desc");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveLsym>(".lsym");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols>(
+ ".subsections_via_symbols");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDumpOrLoad>(".dump");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDumpOrLoad>(".load");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSection>(".section");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSecureLogUnique>(
+ ".secure_log_unique");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSecureLogReset>(
+ ".secure_log_reset");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveTBSS>(".tbss");
+ AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveZerofill>(".zerofill");
// Special section directives.
- Parser.AddDirectiveHandler(this, ".const",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveConst));
- Parser.AddDirectiveHandler(this, ".const_data",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveConstData));
- Parser.AddDirectiveHandler(this, ".constructor",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveConstructor));
- Parser.AddDirectiveHandler(this, ".cstring",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveCString));
- Parser.AddDirectiveHandler(this, ".data",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveData));
- Parser.AddDirectiveHandler(this, ".destructor",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveDestructor));
- Parser.AddDirectiveHandler(this, ".dyld",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveDyld));
- Parser.AddDirectiveHandler(this, ".fvmlib_init0",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveFVMLibInit0));
- Parser.AddDirectiveHandler(this, ".fvmlib_init1",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveFVMLibInit1));
- Parser.AddDirectiveHandler(this, ".lazy_symbol_pointer",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers));
- Parser.AddDirectiveHandler(this, ".literal16",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveLiteral16));
- Parser.AddDirectiveHandler(this, ".literal4",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveLiteral4));
- Parser.AddDirectiveHandler(this, ".literal8",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveLiteral8));
- Parser.AddDirectiveHandler(this, ".mod_init_func",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveModInitFunc));
- Parser.AddDirectiveHandler(this, ".mod_term_func",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveModTermFunc));
- Parser.AddDirectiveHandler(this, ".non_lazy_symbol_pointer",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers));
- Parser.AddDirectiveHandler(this, ".objc_cat_cls_meth",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth));
- Parser.AddDirectiveHandler(this, ".objc_cat_inst_meth",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth));
- Parser.AddDirectiveHandler(this, ".objc_category",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCCategory));
- Parser.AddDirectiveHandler(this, ".objc_class",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCClass));
- Parser.AddDirectiveHandler(this, ".objc_class_names",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCClassNames));
- Parser.AddDirectiveHandler(this, ".objc_class_vars",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCClassVars));
- Parser.AddDirectiveHandler(this, ".objc_cls_meth",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCClsMeth));
- Parser.AddDirectiveHandler(this, ".objc_cls_refs",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCClsRefs));
- Parser.AddDirectiveHandler(this, ".objc_inst_meth",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCInstMeth));
- Parser.AddDirectiveHandler(this, ".objc_instance_vars",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars));
- Parser.AddDirectiveHandler(this, ".objc_message_refs",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs));
- Parser.AddDirectiveHandler(this, ".objc_meta_class",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCMetaClass));
- Parser.AddDirectiveHandler(this, ".objc_meth_var_names",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames));
- Parser.AddDirectiveHandler(this, ".objc_meth_var_types",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes));
- Parser.AddDirectiveHandler(this, ".objc_module_info",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo));
- Parser.AddDirectiveHandler(this, ".objc_protocol",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCProtocol));
- Parser.AddDirectiveHandler(this, ".objc_selector_strs",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs));
- Parser.AddDirectiveHandler(this, ".objc_string_object",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCStringObject));
- Parser.AddDirectiveHandler(this, ".objc_symbols",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveObjCSymbols));
- Parser.AddDirectiveHandler(this, ".picsymbol_stub",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectivePICSymbolStub));
- Parser.AddDirectiveHandler(this, ".static_const",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveStaticConst));
- Parser.AddDirectiveHandler(this, ".static_data",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveStaticData));
- Parser.AddDirectiveHandler(this, ".symbol_stub",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveSymbolStub));
- Parser.AddDirectiveHandler(this, ".tdata",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveTData));
- Parser.AddDirectiveHandler(this, ".text",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveText));
- Parser.AddDirectiveHandler(this, ".thread_init_func",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveThreadInitFunc));
- Parser.AddDirectiveHandler(this, ".tlv",
- MCAsmParser::DirectiveHandler(
- &DarwinAsmParser::ParseSectionDirectiveTLV));
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConst>(".const");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConstData>(".const_data");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConstructor>(".constructor");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveCString>(".cstring");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveData>(".data");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveDestructor>(".destructor");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveDyld>(".dyld");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveFVMLibInit0>(".fvmlib_init0");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveFVMLibInit1>(".fvmlib_init1");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers>(".lazy_symbol_pointer");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral16>(".literal16");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral4>(".literal4");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral8>(".literal8");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveModInitFunc>(".mod_init_func");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveModTermFunc>(".mod_term_func");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers>(".non_lazy_symbol_pointer");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth>(".objc_cat_cls_meth");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth>(".objc_cat_inst_meth");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCategory>(".objc_category");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClass>(".objc_class");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClassNames>(".objc_class_names");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClassVars>(".objc_class_vars");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClsMeth>(".objc_cls_meth");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClsRefs>(".objc_cls_refs");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCInstMeth>(".objc_inst_meth");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars>(".objc_instance_vars");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs>(".objc_message_refs");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMetaClass>(".objc_meta_class");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames>(".objc_meth_var_names");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes>(".objc_meth_var_types");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo>(".objc_module_info");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCProtocol>(".objc_protocol");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs>(".objc_selector_strs");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCStringObject>(".objc_string_object");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCSymbols>(".objc_symbols");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectivePICSymbolStub>(".picsymbol_stub");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveStaticConst>(".static_const");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveStaticData>(".static_data");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveSymbolStub>(".symbol_stub");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveTData>(".tdata");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveText>(".text");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveThreadInitFunc>(".thread_init_func");
+ AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveTLV>(".tlv");
}
bool ParseDirectiveDesc(StringRef, SMLoc);
bool ParseDirectiveDumpOrLoad(StringRef, SMLoc);
bool ParseDirectiveLsym(StringRef, SMLoc);
- bool ParseDirectiveSection();
+ bool ParseDirectiveSection(StringRef, SMLoc);
bool ParseDirectiveSecureLogReset(StringRef, SMLoc);
bool ParseDirectiveSecureLogUnique(StringRef, SMLoc);
bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc);
@@ -493,7 +401,7 @@
/// ParseDirectiveSection:
/// ::= .section identifier (',' identifier)*
-bool DarwinAsmParser::ParseDirectiveSection() {
+bool DarwinAsmParser::ParseDirectiveSection(StringRef, SMLoc) {
SMLoc Loc = getLexer().getLoc();
StringRef SectionName;
@@ -537,28 +445,22 @@
}
/// ParseDirectiveSecureLogUnique
-/// ::= .secure_log_unique "log message"
+/// ::= .secure_log_unique ... message ...
bool DarwinAsmParser::ParseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) {
- std::string LogMessage;
-
- if (getLexer().isNot(AsmToken::String))
- LogMessage = "";
- else{
- LogMessage = getTok().getString();
- Lex();
- }
-
+ StringRef LogMessage = getParser().ParseStringToEndOfStatement();
if (getLexer().isNot(AsmToken::EndOfStatement))
return TokError("unexpected token in '.secure_log_unique' directive");
if (getContext().getSecureLogUsed() != false)
return Error(IDLoc, ".secure_log_unique specified multiple times");
- char *SecureLogFile = getContext().getSecureLogFile();
+ // Get the secure log path.
+ const char *SecureLogFile = getContext().getSecureLogFile();
if (SecureLogFile == NULL)
return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE "
"environment variable unset.");
+ // Open the secure log file if we haven't already.
raw_ostream *OS = getContext().getSecureLog();
if (OS == NULL) {
std::string Err;
@@ -571,6 +473,7 @@
getContext().setSecureLog(OS);
}
+ // Write the message.
int CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc);
*OS << getSourceManager().getBufferInfo(CurBuf).Buffer->getBufferIdentifier()
<< ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":"
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/ELFAsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -8,15 +8,24 @@
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
-#include "llvm/MC/MCSectionELF.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
+#include "llvm/MC/MCSectionELF.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/ADT/Twine.h"
using namespace llvm;
namespace {
class ELFAsmParser : public MCAsmParserExtension {
+ template<bool (ELFAsmParser::*Handler)(StringRef, SMLoc)>
+ void AddDirectiveHandler(StringRef Directive) {
+ getParser().AddDirectiveHandler(this, Directive,
+ HandleDirective<ELFAsmParser, Handler>);
+ }
+
bool ParseSectionSwitch(StringRef Section, unsigned Type,
unsigned Flags, SectionKind Kind);
@@ -27,10 +36,20 @@
// Call the base implementation.
this->MCAsmParserExtension::Initialize(Parser);
- Parser.AddDirectiveHandler(this, ".data", MCAsmParser::DirectiveHandler(
- &ELFAsmParser::ParseSectionDirectiveData));
- Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler(
- &ELFAsmParser::ParseSectionDirectiveText));
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveData>(".data");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveText>(".text");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveBSS>(".bss");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveRoData>(".rodata");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTData>(".tdata");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveTBSS>(".tbss");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRel>(".data.rel");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRo>(".data.rel.ro");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveDataRelRoLocal>(".data.rel.ro.local");
+ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSection>(".section");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".sleb128");
+ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".uleb128");
}
bool ParseSectionDirectiveData(StringRef, SMLoc) {
@@ -43,6 +62,55 @@
MCSectionELF::SHF_EXECINSTR |
MCSectionELF::SHF_ALLOC, SectionKind::getText());
}
+ bool ParseSectionDirectiveBSS(StringRef, SMLoc) {
+ return ParseSectionSwitch(".bss", MCSectionELF::SHT_NOBITS,
+ MCSectionELF::SHF_WRITE |
+ MCSectionELF::SHF_ALLOC, SectionKind::getBSS());
+ }
+ bool ParseSectionDirectiveRoData(StringRef, SMLoc) {
+ return ParseSectionSwitch(".rodata", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC,
+ SectionKind::getReadOnly());
+ }
+ bool ParseSectionDirectiveTData(StringRef, SMLoc) {
+ return ParseSectionSwitch(".tdata", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_TLS | MCSectionELF::SHF_WRITE,
+ SectionKind::getThreadData());
+ }
+ bool ParseSectionDirectiveTBSS(StringRef, SMLoc) {
+ return ParseSectionSwitch(".tbss", MCSectionELF::SHT_NOBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_TLS | MCSectionELF::SHF_WRITE,
+ SectionKind::getThreadBSS());
+ }
+ bool ParseSectionDirectiveDataRel(StringRef, SMLoc) {
+ return ParseSectionSwitch(".data.rel", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_WRITE,
+ SectionKind::getDataRel());
+ }
+ bool ParseSectionDirectiveDataRelRo(StringRef, SMLoc) {
+ return ParseSectionSwitch(".data.rel.ro", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_WRITE,
+ SectionKind::getReadOnlyWithRel());
+ }
+ bool ParseSectionDirectiveDataRelRoLocal(StringRef, SMLoc) {
+ return ParseSectionSwitch(".data.rel.ro.local", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_WRITE,
+ SectionKind::getReadOnlyWithRelLocal());
+ }
+ bool ParseSectionDirectiveEhFrame(StringRef, SMLoc) {
+ return ParseSectionSwitch(".eh_frame", MCSectionELF::SHT_PROGBITS,
+ MCSectionELF::SHF_ALLOC |
+ MCSectionELF::SHF_WRITE,
+ SectionKind::getDataRel());
+ }
+ bool ParseDirectiveLEB128(StringRef, SMLoc);
+ bool ParseDirectiveSection(StringRef, SMLoc);
+ bool ParseDirectiveSize(StringRef, SMLoc);
};
}
@@ -59,6 +127,151 @@
return false;
}
+bool ELFAsmParser::ParseDirectiveSize(StringRef, SMLoc) {
+ StringRef Name;
+ if (getParser().ParseIdentifier(Name))
+ return TokError("expected identifier in directive");
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);;
+
+ if (getLexer().isNot(AsmToken::Comma))
+ return TokError("unexpected token in directive");
+ Lex();
+
+ const MCExpr *Expr;
+ if (getParser().ParseExpression(Expr))
+ return true;
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in directive");
+
+ getStreamer().EmitELFSize(Sym, Expr);
+ return false;
+}
+
+// FIXME: This is a work in progress.
+bool ELFAsmParser::ParseDirectiveSection(StringRef, SMLoc) {
+ StringRef SectionName;
+ // FIXME: This doesn't parse section names like ".note.GNU-stack" correctly.
+ if (getParser().ParseIdentifier(SectionName))
+ return TokError("expected identifier in directive");
+
+ std::string FlagsStr;
+ StringRef TypeName;
+ int64_t Size = 0;
+ if (getLexer().is(AsmToken::Comma)) {
+ Lex();
+
+ if (getLexer().isNot(AsmToken::String))
+ return TokError("expected string in directive");
+
+ FlagsStr = getTok().getStringContents();
+ Lex();
+
+ AsmToken::TokenKind TypeStartToken;
+ if (getContext().getAsmInfo().getCommentString()[0] == '@')
+ TypeStartToken = AsmToken::Percent;
+ else
+ TypeStartToken = AsmToken::At;
+
+ if (getLexer().is(AsmToken::Comma)) {
+ Lex();
+ if (getLexer().is(TypeStartToken)) {
+ Lex();
+ if (getParser().ParseIdentifier(TypeName))
+ return TokError("expected identifier in directive");
+
+ if (getLexer().is(AsmToken::Comma)) {
+ Lex();
+
+ if (getParser().ParseAbsoluteExpression(Size))
+ return true;
+
+ if (Size <= 0)
+ return TokError("section size must be positive");
+ }
+ }
+ }
+ }
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in directive");
+
+ unsigned Flags = 0;
+ for (unsigned i = 0; i < FlagsStr.size(); i++) {
+ switch (FlagsStr[i]) {
+ case 'a':
+ Flags |= MCSectionELF::SHF_ALLOC;
+ break;
+ case 'x':
+ Flags |= MCSectionELF::SHF_EXECINSTR;
+ break;
+ case 'w':
+ Flags |= MCSectionELF::SHF_WRITE;
+ break;
+ case 'M':
+ Flags |= MCSectionELF::SHF_MERGE;
+ break;
+ case 'S':
+ Flags |= MCSectionELF::SHF_STRINGS;
+ break;
+ case 'T':
+ Flags |= MCSectionELF::SHF_TLS;
+ break;
+ case 'c':
+ Flags |= MCSectionELF::XCORE_SHF_CP_SECTION;
+ break;
+ case 'd':
+ Flags |= MCSectionELF::XCORE_SHF_DP_SECTION;
+ break;
+ default:
+ return TokError("unknown flag");
+ }
+ }
+
+ unsigned Type = MCSectionELF::SHT_NULL;
+ if (!TypeName.empty()) {
+ if (TypeName == "init_array")
+ Type = MCSectionELF::SHT_INIT_ARRAY;
+ else if (TypeName == "fini_array")
+ Type = MCSectionELF::SHT_FINI_ARRAY;
+ else if (TypeName == "preinit_array")
+ Type = MCSectionELF::SHT_PREINIT_ARRAY;
+ else if (TypeName == "nobits")
+ Type = MCSectionELF::SHT_NOBITS;
+ else if (TypeName == "progbits")
+ Type = MCSectionELF::SHT_PROGBITS;
+ else
+ return TokError("unknown section type");
+ }
+
+ SectionKind Kind = (Flags & MCSectionELF::SHF_EXECINSTR)
+ ? SectionKind::getText()
+ : SectionKind::getDataRel();
+ getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type,
+ Flags, Kind, false));
+ return false;
+}
+
+bool ELFAsmParser::ParseDirectiveLEB128(StringRef DirName, SMLoc) {
+ int64_t Value;
+ if (getParser().ParseAbsoluteExpression(Value))
+ return true;
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return TokError("unexpected token in directive");
+
+ // FIXME: Add proper MC support.
+ if (getContext().getAsmInfo().hasLEB128()) {
+ if (DirName[1] == 's')
+ getStreamer().EmitRawText("\t.sleb128\t" + Twine(Value));
+ else
+ getStreamer().EmitRawText("\t.uleb128\t" + Twine(Value));
+ return false;
+ }
+ // FIXME: This shouldn't be an error!
+ return TokError("LEB128 not supported yet");
+}
+
namespace llvm {
MCAsmParserExtension *createELFAsmParser() {
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/MCAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/MCAsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/MCAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/MCAsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -12,19 +12,26 @@
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/Support/SourceMgr.h"
+#include "llvm/Target/TargetAsmParser.h"
using namespace llvm;
-MCAsmParser::MCAsmParser() {
+MCAsmParser::MCAsmParser() : TargetParser(0) {
}
MCAsmParser::~MCAsmParser() {
}
+void MCAsmParser::setTargetParser(TargetAsmParser &P) {
+ assert(!TargetParser && "Target parser is already initialized!");
+ TargetParser = &P;
+ TargetParser->Initialize(*this);
+}
+
const AsmToken &MCAsmParser::getTok() {
return getLexer().getTok();
}
-bool MCAsmParser::TokError(const char *Msg) {
+bool MCAsmParser::TokError(const Twine &Msg) {
Error(getLexer().getLoc(), Msg);
return true;
}
Modified: llvm/branches/wendling/eh/lib/MC/MCParser/TargetAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCParser/TargetAsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCParser/TargetAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCParser/TargetAsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -11,7 +11,7 @@
using namespace llvm;
TargetAsmParser::TargetAsmParser(const Target &T)
- : TheTarget(T)
+ : TheTarget(T), AvailableFeatures(0)
{
}
Modified: llvm/branches/wendling/eh/lib/MC/MCStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/MCStreamer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/MCStreamer.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/MCStreamer.cpp Sat Jul 31 19:59:02 2010
@@ -15,7 +15,7 @@
#include <cstdlib>
using namespace llvm;
-MCStreamer::MCStreamer(MCContext &_Context) : Context(_Context), CurSection(0) {
+MCStreamer::MCStreamer(MCContext &Ctx) : Context(Ctx), CurSection(0) {
}
MCStreamer::~MCStreamer() {
Modified: llvm/branches/wendling/eh/lib/MC/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/Makefile (original)
+++ llvm/branches/wendling/eh/lib/MC/Makefile Sat Jul 31 19:59:02 2010
@@ -10,7 +10,7 @@
LEVEL = ../..
LIBRARYNAME = LLVMMC
BUILD_ARCHIVE := 1
-PARALLEL_DIRS := MCParser
+PARALLEL_DIRS := MCParser MCDisassembler
include $(LEVEL)/Makefile.common
Modified: llvm/branches/wendling/eh/lib/MC/WinCOFFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/WinCOFFObjectWriter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/WinCOFFObjectWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/WinCOFFObjectWriter.cpp Sat Jul 31 19:59:02 2010
@@ -12,41 +12,545 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "WinCOFFObjectWriter"
+
#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSection.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCValue.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCAsmLayout.h"
+#include "llvm/MC/MCSectionCOFF.h"
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+
+#include "llvm/Support/COFF.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+
+#include <cstdio>
+
using namespace llvm;
namespace {
+typedef llvm::SmallString<COFF::NameSize> name;
+
+enum AuxiliaryType {
+ ATFunctionDefinition,
+ ATbfAndefSymbol,
+ ATWeakExternal,
+ ATFile,
+ ATSectionDefinition
+};
+
+struct AuxSymbol {
+ AuxiliaryType AuxType;
+ COFF::Auxiliary Aux;
+};
+
+class COFFSymbol {
+public:
+ COFF::symbol Data;
+
+ typedef llvm::SmallVector<AuxSymbol, 1> AuxiliarySymbols;
+
+ name Name;
+ size_t Index;
+ AuxiliarySymbols Aux;
+ COFFSymbol *Other;
+
+ MCSymbolData const *MCData;
+
+ COFFSymbol(llvm::StringRef name, size_t index);
+ size_t size() const;
+ void set_name_offset(uint32_t Offset);
+};
+
+// This class contains staging data for a COFF relocation entry.
+struct COFFRelocation {
+ COFF::relocation Data;
+ COFFSymbol *Symb;
+
+ COFFRelocation() : Symb(NULL) {}
+ static size_t size() { return COFF::RelocationSize; }
+};
+
+typedef std::vector<COFFRelocation> relocations;
+
+class COFFSection {
+public:
+ COFF::section Header;
+
+ std::string Name;
+ size_t Number;
+ MCSectionData const *MCData;
+ COFFSymbol *Symb;
+ relocations Relocations;
+
+ COFFSection(llvm::StringRef name, size_t Index);
+ static size_t size();
+};
+
+// This class holds the COFF string table.
+class StringTable {
+ typedef llvm::StringMap<size_t> map;
+ map Map;
- class WinCOFFObjectWriter : public MCObjectWriter {
- public:
- WinCOFFObjectWriter(raw_ostream &OS);
-
- // MCObjectWriter interface implementation.
-
- void ExecutePostLayoutBinding(MCAssembler &Asm);
-
- void RecordRelocation(const MCAssembler &Asm,
- const MCAsmLayout &Layout,
- const MCFragment *Fragment,
- const MCFixup &Fixup,
- MCValue Target,
- uint64_t &FixedValue);
+ void update_length();
+public:
+ std::vector<char> Data;
- void WriteObject(const MCAssembler &Asm, const MCAsmLayout &Layout);
- };
+ StringTable();
+ size_t size() const;
+ size_t insert(llvm::StringRef String);
+};
+
+class WinCOFFObjectWriter : public MCObjectWriter {
+public:
+
+ typedef std::vector<COFFSymbol*> symbols;
+ typedef std::vector<COFFSection*> sections;
+
+ typedef StringMap<COFFSymbol *> name_symbol_map;
+ typedef StringMap<COFFSection *> name_section_map;
+
+ typedef DenseMap<MCSymbolData const *, COFFSymbol *> symbol_map;
+ typedef DenseMap<MCSectionData const *, COFFSection *> section_map;
+
+ // Root level file contents.
+ COFF::header Header;
+ sections Sections;
+ symbols Symbols;
+ StringTable Strings;
+
+ // Maps used during object file creation.
+ section_map SectionMap;
+ symbol_map SymbolMap;
+
+ WinCOFFObjectWriter(raw_ostream &OS);
+ ~WinCOFFObjectWriter();
+
+ COFFSymbol *createSymbol(llvm::StringRef Name);
+ COFFSection *createSection(llvm::StringRef Name);
+
+ void InitCOFFEntity(COFFSymbol &Symbol);
+ void InitCOFFEntity(COFFSection &Section);
+
+ template <typename object_t, typename list_t>
+ object_t *createCOFFEntity(llvm::StringRef Name, list_t &List);
+
+ void DefineSection(MCSectionData const &SectionData);
+ void DefineSymbol(MCSymbolData const &SymbolData, MCAssembler &Assembler);
+
+ bool ExportSection(COFFSection *S);
+ bool ExportSymbol(MCSymbolData const &SymbolData, MCAssembler &Asm);
+
+ // Entity writing methods.
+
+ void WriteFileHeader(const COFF::header &Header);
+ void WriteSymbol(const COFFSymbol *S);
+ void WriteAuxiliarySymbols(const COFFSymbol::AuxiliarySymbols &S);
+ void WriteSectionHeader(const COFF::section &S);
+ void WriteRelocation(const COFF::relocation &R);
+
+ // MCObjectWriter interface implementation.
+
+ void ExecutePostLayoutBinding(MCAssembler &Asm);
+
+ void RecordRelocation(const MCAssembler &Asm,
+ const MCAsmLayout &Layout,
+ const MCFragment *Fragment,
+ const MCFixup &Fixup,
+ MCValue Target,
+ uint64_t &FixedValue);
+
+ void WriteObject(const MCAssembler &Asm, const MCAsmLayout &Layout);
+};
}
+static inline void write_uint32_le(void *Data, uint32_t const &Value) {
+ uint8_t *Ptr = reinterpret_cast<uint8_t *>(Data);
+ Ptr[0] = (Value & 0x000000FF) >> 0;
+ Ptr[1] = (Value & 0x0000FF00) >> 8;
+ Ptr[2] = (Value & 0x00FF0000) >> 16;
+ Ptr[3] = (Value & 0xFF000000) >> 24;
+}
+
+static inline void write_uint16_le(void *Data, uint16_t const &Value) {
+ uint8_t *Ptr = reinterpret_cast<uint8_t *>(Data);
+ Ptr[0] = (Value & 0x00FF) >> 0;
+ Ptr[1] = (Value & 0xFF00) >> 8;
+}
+
+static inline void write_uint8_le(void *Data, uint8_t const &Value) {
+ uint8_t *Ptr = reinterpret_cast<uint8_t *>(Data);
+ Ptr[0] = (Value & 0xFF) >> 0;
+}
+
+//------------------------------------------------------------------------------
+// Symbol class implementation
+
+COFFSymbol::COFFSymbol(llvm::StringRef name, size_t index)
+ : Name(name.begin(), name.end()), Index(-1)
+ , Other(NULL), MCData(NULL) {
+ memset(&Data, 0, sizeof(Data));
+}
+
+size_t COFFSymbol::size() const {
+ return COFF::SymbolSize + (Data.NumberOfAuxSymbols * COFF::SymbolSize);
+}
+
+// In the case that the name does not fit within 8 bytes, the offset
+// into the string table is stored in the last 4 bytes instead, leaving
+// the first 4 bytes as 0.
+void COFFSymbol::set_name_offset(uint32_t Offset) {
+ write_uint32_le(Data.Name + 0, 0);
+ write_uint32_le(Data.Name + 4, Offset);
+}
+
+//------------------------------------------------------------------------------
+// Section class implementation
+
+COFFSection::COFFSection(llvm::StringRef name, size_t Index)
+ : Name(name), Number(Index + 1)
+ , MCData(NULL), Symb(NULL) {
+ memset(&Header, 0, sizeof(Header));
+}
+
+size_t COFFSection::size() {
+ return COFF::SectionSize;
+}
+
+//------------------------------------------------------------------------------
+// StringTable class implementation
+
+/// Write the length of the string table into Data.
+/// The length of the string table includes uint32 length header.
+void StringTable::update_length() {
+ write_uint32_le(&Data.front(), Data.size());
+}
+
+StringTable::StringTable() {
+ // The string table data begins with the length of the entire string table
+ // including the length header. Allocate space for this header.
+ Data.resize(4);
+}
+
+size_t StringTable::size() const {
+ return Data.size();
+}
+
+/// Add String to the table iff it is not already there.
+/// @returns the index into the string table where the string is now located.
+size_t StringTable::insert(llvm::StringRef String) {
+ map::iterator i = Map.find(String);
+
+ if (i != Map.end())
+ return i->second;
+
+ size_t Offset = Data.size();
+
+ // Insert string data into string table.
+ Data.insert(Data.end(), String.begin(), String.end());
+ Data.push_back('\0');
+
+ // Put a reference to it in the map.
+ Map[String] = Offset;
+
+ // Update the internal length field.
+ update_length();
+
+ return Offset;
+}
+
+//------------------------------------------------------------------------------
+// WinCOFFObjectWriter class implementation
+
WinCOFFObjectWriter::WinCOFFObjectWriter(raw_ostream &OS)
: MCObjectWriter(OS, true) {
+ memset(&Header, 0, sizeof(Header));
+ // TODO: Move magic constant out to COFF.h
+ Header.Machine = 0x14C; // x86
+}
+
+WinCOFFObjectWriter::~WinCOFFObjectWriter() {
+ for (symbols::iterator I = Symbols.begin(), E = Symbols.end(); I != E; ++I)
+ delete *I;
+ for (sections::iterator I = Sections.begin(), E = Sections.end(); I != E; ++I)
+ delete *I;
+}
+
+COFFSymbol *WinCOFFObjectWriter::createSymbol(llvm::StringRef Name) {
+ return createCOFFEntity<COFFSymbol>(Name, Symbols);
+}
+
+COFFSection *WinCOFFObjectWriter::createSection(llvm::StringRef Name) {
+ return createCOFFEntity<COFFSection>(Name, Sections);
+}
+
+/// This function initializes a symbol by entering its name into the string
+/// table if it is too long to fit in the symbol table header.
+void WinCOFFObjectWriter::InitCOFFEntity(COFFSymbol &S) {
+ if (S.Name.size() > COFF::NameSize) {
+ size_t StringTableEntry = Strings.insert(S.Name.c_str());
+
+ S.set_name_offset(StringTableEntry);
+ } else
+ memcpy(S.Data.Name, S.Name.c_str(), S.Name.size());
+}
+
+/// This function initializes a section by entering its name into the string
+/// table if it is too long to fit in the section table header.
+void WinCOFFObjectWriter::InitCOFFEntity(COFFSection &S) {
+ if (S.Name.size() > COFF::NameSize) {
+ size_t StringTableEntry = Strings.insert(S.Name.c_str());
+
+ // FIXME: Why is this number 999999? This number is never mentioned in the
+ // spec. I'm assuming this is due to the printed value needing to fit into
+ // the S.Header.Name field. In which case why not 9999999 (7 9's instead of
+ // 6)? The spec does not state if this entry should be null terminated in
+ // this case, and thus this seems to be the best way to do it. I think I
+ // just solved my own FIXME...
+ if (StringTableEntry > 999999)
+ report_fatal_error("COFF string table is greater than 999999 bytes.");
+
+ sprintf(S.Header.Name, "/%d", (unsigned)StringTableEntry);
+ } else
+ memcpy(S.Header.Name, S.Name.c_str(), S.Name.size());
+}
+
+/// A template used to lookup or create a symbol/section, and initialize it if
+/// needed.
+template <typename object_t, typename list_t>
+object_t *WinCOFFObjectWriter::createCOFFEntity(llvm::StringRef Name,
+ list_t &List) {
+ object_t *Object = new object_t(Name, List.size());
+
+ InitCOFFEntity(*Object);
+
+ List.push_back(Object);
+
+ return Object;
+}
+
+/// This function takes a section data object from the assembler
+/// and creates the associated COFF section staging object.
+void WinCOFFObjectWriter::DefineSection(MCSectionData const &SectionData) {
+ // FIXME: Not sure how to verify this (at least in a debug build).
+ MCSectionCOFF const &Sec =
+ static_cast<MCSectionCOFF const &>(SectionData.getSection());
+
+ COFFSection *coff_section = createSection(Sec.getSectionName());
+ COFFSymbol *coff_symbol = createSymbol(Sec.getSectionName());
+
+ coff_section->Symb = coff_symbol;
+ coff_symbol->Data.StorageClass = COFF::IMAGE_SYM_CLASS_STATIC;
+ coff_symbol->Data.SectionNumber = coff_section->Number;
+
+ // In this case the auxiliary symbol is a Section Definition.
+ coff_symbol->Aux.resize(1);
+ memset(&coff_symbol->Aux[0], 0, sizeof(coff_symbol->Aux[0]));
+ coff_symbol->Aux[0].AuxType = ATSectionDefinition;
+ coff_symbol->Aux[0].Aux.SectionDefinition.Number = coff_section->Number;
+ coff_symbol->Aux[0].Aux.SectionDefinition.Selection = Sec.getSelection();
+
+ coff_section->Header.Characteristics = Sec.getCharacteristics();
+
+ uint32_t &Characteristics = coff_section->Header.Characteristics;
+ switch (SectionData.getAlignment()) {
+ case 1: Characteristics |= COFF::IMAGE_SCN_ALIGN_1BYTES; break;
+ case 2: Characteristics |= COFF::IMAGE_SCN_ALIGN_2BYTES; break;
+ case 4: Characteristics |= COFF::IMAGE_SCN_ALIGN_4BYTES; break;
+ case 8: Characteristics |= COFF::IMAGE_SCN_ALIGN_8BYTES; break;
+ case 16: Characteristics |= COFF::IMAGE_SCN_ALIGN_16BYTES; break;
+ case 32: Characteristics |= COFF::IMAGE_SCN_ALIGN_32BYTES; break;
+ case 64: Characteristics |= COFF::IMAGE_SCN_ALIGN_64BYTES; break;
+ case 128: Characteristics |= COFF::IMAGE_SCN_ALIGN_128BYTES; break;
+ case 256: Characteristics |= COFF::IMAGE_SCN_ALIGN_256BYTES; break;
+ case 512: Characteristics |= COFF::IMAGE_SCN_ALIGN_512BYTES; break;
+ case 1024: Characteristics |= COFF::IMAGE_SCN_ALIGN_1024BYTES; break;
+ case 2048: Characteristics |= COFF::IMAGE_SCN_ALIGN_2048BYTES; break;
+ case 4096: Characteristics |= COFF::IMAGE_SCN_ALIGN_4096BYTES; break;
+ case 8192: Characteristics |= COFF::IMAGE_SCN_ALIGN_8192BYTES; break;
+ default:
+ llvm_unreachable("unsupported section alignment");
+ }
+
+ // Bind internal COFF section to MC section.
+ coff_section->MCData = &SectionData;
+ SectionMap[&SectionData] = coff_section;
+}
+
+/// This function takes a section data object from the assembler
+/// and creates the associated COFF symbol staging object.
+void WinCOFFObjectWriter::DefineSymbol(MCSymbolData const &SymbolData,
+ MCAssembler &Assembler) {
+ COFFSymbol *coff_symbol = createSymbol(SymbolData.getSymbol().getName());
+
+ coff_symbol->Data.Type = (SymbolData.getFlags() & 0x0000FFFF) >> 0;
+ coff_symbol->Data.StorageClass = (SymbolData.getFlags() & 0x00FF0000) >> 16;
+
+ // If no storage class was specified in the streamer, define it here.
+ if (coff_symbol->Data.StorageClass == 0) {
+ bool external = SymbolData.isExternal() || (SymbolData.Fragment == NULL);
+
+ coff_symbol->Data.StorageClass =
+ external ? COFF::IMAGE_SYM_CLASS_EXTERNAL : COFF::IMAGE_SYM_CLASS_STATIC;
+ }
+
+ if (SymbolData.getFlags() & COFF::SF_WeakReference) {
+ coff_symbol->Data.StorageClass = COFF::IMAGE_SYM_CLASS_WEAK_EXTERNAL;
+
+ const MCExpr *Value = SymbolData.getSymbol().getVariableValue();
+
+ // FIXME: This assert message isn't very good.
+ assert(Value->getKind() == MCExpr::SymbolRef &&
+ "Value must be a SymbolRef!");
+
+ const MCSymbolRefExpr *SymbolRef =
+ static_cast<const MCSymbolRefExpr *>(Value);
+
+ const MCSymbolData &OtherSymbolData =
+ Assembler.getSymbolData(SymbolRef->getSymbol());
+
+ // FIXME: This assert message isn't very good.
+ assert(SymbolMap.find(&OtherSymbolData) != SymbolMap.end() &&
+ "OtherSymbolData must be in the symbol map!");
+
+ coff_symbol->Other = SymbolMap[&OtherSymbolData];
+
+ // Setup the Weak External auxiliary symbol.
+ coff_symbol->Aux.resize(1);
+ memset(&coff_symbol->Aux[0], 0, sizeof(coff_symbol->Aux[0]));
+ coff_symbol->Aux[0].AuxType = ATWeakExternal;
+ coff_symbol->Aux[0].Aux.WeakExternal.TagIndex = 0;
+ coff_symbol->Aux[0].Aux.WeakExternal.Characteristics =
+ COFF::IMAGE_WEAK_EXTERN_SEARCH_LIBRARY;
+ }
+
+ // Bind internal COFF symbol to MC symbol.
+ coff_symbol->MCData = &SymbolData;
+ SymbolMap[&SymbolData] = coff_symbol;
+}
+
+bool WinCOFFObjectWriter::ExportSection(COFFSection *S) {
+ return (S->Header.Characteristics
+ & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA) == 0;
+}
+
+bool WinCOFFObjectWriter::ExportSymbol(MCSymbolData const &SymbolData,
+ MCAssembler &Asm) {
+ // This doesn't seem to be right. Strings referred to from the .data section
+ // need symbols so they can be linked to code in the .text section right?
+
+ // return Asm.isSymbolLinkerVisible (&SymbolData);
+
+ // For now, all symbols are exported, the linker will sort it out for us.
+ return true;
+}
+
+//------------------------------------------------------------------------------
+// entity writing methods
+
+void WinCOFFObjectWriter::WriteFileHeader(const COFF::header &Header) {
+ WriteLE16(Header.Machine);
+ WriteLE16(Header.NumberOfSections);
+ WriteLE32(Header.TimeDateStamp);
+ WriteLE32(Header.PointerToSymbolTable);
+ WriteLE32(Header.NumberOfSymbols);
+ WriteLE16(Header.SizeOfOptionalHeader);
+ WriteLE16(Header.Characteristics);
+}
+
+void WinCOFFObjectWriter::WriteSymbol(const COFFSymbol *S) {
+ WriteBytes(StringRef(S->Data.Name, COFF::NameSize));
+ WriteLE32(S->Data.Value);
+ WriteLE16(S->Data.SectionNumber);
+ WriteLE16(S->Data.Type);
+ Write8(S->Data.StorageClass);
+ Write8(S->Data.NumberOfAuxSymbols);
+ WriteAuxiliarySymbols(S->Aux);
+}
+
+void WinCOFFObjectWriter::WriteAuxiliarySymbols(
+ const COFFSymbol::AuxiliarySymbols &S) {
+ for(COFFSymbol::AuxiliarySymbols::const_iterator i = S.begin(), e = S.end();
+ i != e; ++i) {
+ switch(i->AuxType) {
+ case ATFunctionDefinition:
+ WriteLE32(i->Aux.FunctionDefinition.TagIndex);
+ WriteLE32(i->Aux.FunctionDefinition.TotalSize);
+ WriteLE32(i->Aux.FunctionDefinition.PointerToLinenumber);
+ WriteLE32(i->Aux.FunctionDefinition.PointerToNextFunction);
+ WriteZeros(sizeof(i->Aux.FunctionDefinition.unused));
+ break;
+ case ATbfAndefSymbol:
+ WriteZeros(sizeof(i->Aux.bfAndefSymbol.unused1));
+ WriteLE16(i->Aux.bfAndefSymbol.Linenumber);
+ WriteZeros(sizeof(i->Aux.bfAndefSymbol.unused2));
+ WriteLE32(i->Aux.bfAndefSymbol.PointerToNextFunction);
+ WriteZeros(sizeof(i->Aux.bfAndefSymbol.unused3));
+ break;
+ case ATWeakExternal:
+ WriteLE32(i->Aux.WeakExternal.TagIndex);
+ WriteLE32(i->Aux.WeakExternal.Characteristics);
+ WriteZeros(sizeof(i->Aux.WeakExternal.unused));
+ break;
+ case ATFile:
+ WriteBytes(StringRef(reinterpret_cast<const char *>(i->Aux.File.FileName),
+ sizeof(i->Aux.File.FileName)));
+ break;
+ case ATSectionDefinition:
+ WriteLE32(i->Aux.SectionDefinition.Length);
+ WriteLE16(i->Aux.SectionDefinition.NumberOfRelocations);
+ WriteLE16(i->Aux.SectionDefinition.NumberOfLinenumbers);
+ WriteLE32(i->Aux.SectionDefinition.CheckSum);
+ WriteLE16(i->Aux.SectionDefinition.Number);
+ Write8(i->Aux.SectionDefinition.Selection);
+ WriteZeros(sizeof(i->Aux.SectionDefinition.unused));
+ break;
+ }
+ }
+}
+
+void WinCOFFObjectWriter::WriteSectionHeader(const COFF::section &S) {
+ WriteBytes(StringRef(S.Name, COFF::NameSize));
+
+ WriteLE32(S.VirtualSize);
+ WriteLE32(S.VirtualAddress);
+ WriteLE32(S.SizeOfRawData);
+ WriteLE32(S.PointerToRawData);
+ WriteLE32(S.PointerToRelocations);
+ WriteLE32(S.PointerToLineNumbers);
+ WriteLE16(S.NumberOfRelocations);
+ WriteLE16(S.NumberOfLineNumbers);
+ WriteLE32(S.Characteristics);
+}
+
+void WinCOFFObjectWriter::WriteRelocation(const COFF::relocation &R) {
+ WriteLE32(R.VirtualAddress);
+ WriteLE32(R.SymbolTableIndex);
+ WriteLE16(R.Type);
}
////////////////////////////////////////////////////////////////////////////////
// MCObjectWriter interface implementations
void WinCOFFObjectWriter::ExecutePostLayoutBinding(MCAssembler &Asm) {
+ // "Define" each section & symbol. This creates section & symbol
+ // entries in the staging area and gives them their final indexes.
+
+ for (MCAssembler::const_iterator i = Asm.begin(), e = Asm.end(); i != e; i++)
+ DefineSection(*i);
+
+ for (MCAssembler::const_symbol_iterator i = Asm.symbol_begin(),
+ e = Asm.symbol_end(); i != e; i++) {
+ if (ExportSymbol(*i, Asm))
+ DefineSymbol(*i, Asm);
+ }
}
void WinCOFFObjectWriter::RecordRelocation(const MCAssembler &Asm,
@@ -55,10 +559,175 @@
const MCFixup &Fixup,
MCValue Target,
uint64_t &FixedValue) {
+ assert(Target.getSymA() != NULL && "Relocation must reference a symbol!");
+ assert(Target.getSymB() == NULL &&
+ "Relocation must reference only one symbol!");
+
+ MCSectionData const *SectionData = Fragment->getParent();
+ MCSymbolData const *SymbolData =
+ &Asm.getSymbolData(Target.getSymA()->getSymbol());
+
+ assert(SectionMap.find(SectionData) != SectionMap.end() &&
+ "Section must already have been defined in ExecutePostLayoutBinding!");
+ assert(SymbolMap.find(SymbolData) != SymbolMap.end() &&
+ "Symbol must already have been defined in ExecutePostLayoutBinding!");
+
+ COFFSection *coff_section = SectionMap[SectionData];
+ COFFSymbol *coff_symbol = SymbolMap[SymbolData];
+
+ FixedValue = Target.getConstant();
+
+ COFFRelocation Reloc;
+
+ Reloc.Data.SymbolTableIndex = 0;
+ Reloc.Data.VirtualAddress = Layout.getFragmentOffset(Fragment);
+ Reloc.Symb = coff_symbol;
+
+ Reloc.Data.VirtualAddress += Fixup.getOffset();
+
+ switch (Fixup.getKind()) {
+ case FirstTargetFixupKind: // reloc_pcrel_4byte
+ Reloc.Data.Type = COFF::IMAGE_REL_I386_REL32;
+ FixedValue += 4;
+ break;
+ case FK_Data_4:
+ Reloc.Data.Type = COFF::IMAGE_REL_I386_DIR32;
+ break;
+ default:
+ llvm_unreachable("unsupported relocation type");
+ }
+
+ coff_section->Relocations.push_back(Reloc);
}
void WinCOFFObjectWriter::WriteObject(const MCAssembler &Asm,
const MCAsmLayout &Layout) {
+ // Assign symbol and section indexes and offsets.
+
+ Header.NumberOfSymbols = 0;
+
+ for (symbols::iterator i = Symbols.begin(), e = Symbols.end(); i != e; i++) {
+ COFFSymbol *coff_symbol = *i;
+ MCSymbolData const *SymbolData = coff_symbol->MCData;
+
+ coff_symbol->Index = Header.NumberOfSymbols++;
+
+ // Update section number & offset for symbols that have them.
+ if ((SymbolData != NULL) && (SymbolData->Fragment != NULL)) {
+ COFFSection *coff_section = SectionMap[SymbolData->Fragment->getParent()];
+
+ coff_symbol->Data.SectionNumber = coff_section->Number;
+ coff_symbol->Data.Value = Layout.getFragmentOffset(SymbolData->Fragment);
+ }
+
+ // Update auxiliary symbol info.
+ coff_symbol->Data.NumberOfAuxSymbols = coff_symbol->Aux.size();
+ Header.NumberOfSymbols += coff_symbol->Data.NumberOfAuxSymbols;
+ }
+
+ // Fixup weak external references.
+ for (symbols::iterator i = Symbols.begin(), e = Symbols.end(); i != e; i++) {
+ COFFSymbol *symb = *i;
+
+ if (symb->Other != NULL) {
+ assert(symb->Aux.size() == 1 &&
+ "Symbol must contain one aux symbol!");
+ assert(symb->Aux[0].AuxType == ATWeakExternal &&
+ "Symbol's aux symbol must be a Weak External!");
+ symb->Aux[0].Aux.WeakExternal.TagIndex = symb->Other->Index;
+ }
+ }
+
+ // Assign file offsets to COFF object file structures.
+
+ unsigned offset = 0;
+
+ offset += COFF::HeaderSize;
+ offset += COFF::SectionSize * Asm.size();
+
+ Header.NumberOfSections = Sections.size();
+
+ for (MCAssembler::const_iterator i = Asm.begin(),
+ e = Asm.end();
+ i != e; i++) {
+ COFFSection *Sec = SectionMap[i];
+
+ Sec->Header.SizeOfRawData = Layout.getSectionFileSize(i);
+
+ if (ExportSection(Sec)) {
+ Sec->Header.PointerToRawData = offset;
+
+ offset += Sec->Header.SizeOfRawData;
+ }
+
+ if (Sec->Relocations.size() > 0) {
+ Sec->Header.NumberOfRelocations = Sec->Relocations.size();
+ Sec->Header.PointerToRelocations = offset;
+
+ offset += COFF::RelocationSize * Sec->Relocations.size();
+
+ for (relocations::iterator cr = Sec->Relocations.begin(),
+ er = Sec->Relocations.end();
+ cr != er; cr++) {
+ (*cr).Data.SymbolTableIndex = (*cr).Symb->Index;
+ }
+ }
+
+ assert(Sec->Symb->Aux.size() == 1 && "Section's symbol must have one aux!");
+ AuxSymbol &Aux = Sec->Symb->Aux[0];
+ assert(Aux.AuxType == ATSectionDefinition &&
+ "Section's symbol's aux symbol must be a Section Definition!");
+ Aux.Aux.SectionDefinition.Length = Sec->Header.SizeOfRawData;
+ Aux.Aux.SectionDefinition.NumberOfRelocations =
+ Sec->Header.NumberOfRelocations;
+ Aux.Aux.SectionDefinition.NumberOfLinenumbers =
+ Sec->Header.NumberOfLineNumbers;
+ }
+
+ Header.PointerToSymbolTable = offset;
+
+ // Write it all to disk...
+ WriteFileHeader(Header);
+
+ {
+ sections::iterator i, ie;
+ MCAssembler::const_iterator j, je;
+
+ for (i = Sections.begin(), ie = Sections.end(); i != ie; i++)
+ WriteSectionHeader((*i)->Header);
+
+ for (i = Sections.begin(), ie = Sections.end(),
+ j = Asm.begin(), je = Asm.end();
+ (i != ie) && (j != je); i++, j++) {
+ if ((*i)->Header.PointerToRawData != 0) {
+ assert(OS.tell() == (*i)->Header.PointerToRawData &&
+ "Section::PointerToRawData is insane!");
+
+ Asm.WriteSectionData(j, Layout, this);
+ }
+
+ if ((*i)->Relocations.size() > 0) {
+ assert(OS.tell() == (*i)->Header.PointerToRelocations &&
+ "Section::PointerToRelocations is insane!");
+
+ for (relocations::const_iterator k = (*i)->Relocations.begin(),
+ ke = (*i)->Relocations.end();
+ k != ke; k++) {
+ WriteRelocation(k->Data);
+ }
+ } else
+ assert((*i)->Header.PointerToRelocations == 0 &&
+ "Section::PointerToRelocations is insane!");
+ }
+ }
+
+ assert(OS.tell() == Header.PointerToSymbolTable &&
+ "Header::PointerToSymbolTable is insane!");
+
+ for (symbols::iterator i = Symbols.begin(), e = Symbols.end(); i != e; i++)
+ WriteSymbol(*i);
+
+ OS.write((char const *)&Strings.Data.front(), Strings.Data.size());
}
//------------------------------------------------------------------------------
Modified: llvm/branches/wendling/eh/lib/MC/WinCOFFStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/MC/WinCOFFStreamer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/MC/WinCOFFStreamer.cpp (original)
+++ llvm/branches/wendling/eh/lib/MC/WinCOFFStreamer.cpp Sat Jul 31 19:59:02 2010
@@ -18,27 +18,34 @@
#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmLayout.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCSectionCOFF.h"
+#include "llvm/Target/TargetRegistry.h"
#include "llvm/Target/TargetAsmBackend.h"
+#include "llvm/ADT/StringMap.h"
+
#include "llvm/Support/COFF.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-#define dbg_notimpl(x) \
- do { dbgs() << "not implemented, " << __FUNCTION__ << " (" << x << ")"; \
- abort(); } while (false);
-
namespace {
class WinCOFFStreamer : public MCObjectStreamer {
public:
+ MCSymbol const *CurSymbol;
+
WinCOFFStreamer(MCContext &Context,
TargetAsmBackend &TAB,
MCCodeEmitter &CE,
raw_ostream &OS);
+ void AddCommonSymbol(MCSymbol *Symbol, uint64_t Size,
+ unsigned ByteAlignment, bool External);
+
// MCStreamer interface
virtual void EmitLabel(MCSymbol *Symbol);
@@ -52,18 +59,18 @@
virtual void EndCOFFSymbolDef();
virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value);
virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
- unsigned ByteAlignment);
+ unsigned ByteAlignment);
virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size);
virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol,
- unsigned Size,unsigned ByteAlignment);
+ unsigned Size,unsigned ByteAlignment);
virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
- uint64_t Size, unsigned ByteAlignment);
+ uint64_t Size, unsigned ByteAlignment);
virtual void EmitBytes(StringRef Data, unsigned AddrSpace);
- virtual void EmitValue(const MCExpr *Value, unsigned Size,
+ virtual void EmitValue(const MCExpr *Value, unsigned Size,
unsigned AddrSpace);
virtual void EmitGPRel32Value(const MCExpr *Value);
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value,
- unsigned ValueSize, unsigned MaxBytesToEmit);
+ unsigned ValueSize, unsigned MaxBytesToEmit);
virtual void EmitCodeAlignment(unsigned ByteAlignment,
unsigned MaxBytesToEmit);
virtual void EmitValueToOffset(const MCExpr *Offset, unsigned char Value);
@@ -78,96 +85,223 @@
TargetAsmBackend &TAB,
MCCodeEmitter &CE,
raw_ostream &OS)
- : MCObjectStreamer(Context, TAB, OS, &CE) {
+ : MCObjectStreamer(Context, TAB, OS, &CE)
+ , CurSymbol(NULL) {
+}
+
+void WinCOFFStreamer::AddCommonSymbol(MCSymbol *Symbol, uint64_t Size,
+ unsigned ByteAlignment, bool External) {
+ assert(!Symbol->isInSection() && "Symbol must not already have a section!");
+
+ std::string SectionName(".bss$linkonce");
+ SectionName.append(Symbol->getName().begin(), Symbol->getName().end());
+
+ MCSymbolData &SymbolData = getAssembler().getOrCreateSymbolData(*Symbol);
+
+ unsigned Characteristics =
+ COFF::IMAGE_SCN_LNK_COMDAT |
+ COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA |
+ COFF::IMAGE_SCN_MEM_READ |
+ COFF::IMAGE_SCN_MEM_WRITE;
+
+ int Selection = COFF::IMAGE_COMDAT_SELECT_LARGEST;
+
+ const MCSection *Section = MCStreamer::getContext().getCOFFSection(
+ SectionName, Characteristics, Selection, SectionKind::getBSS());
+
+ MCSectionData &SectionData = getAssembler().getOrCreateSectionData(*Section);
+
+ if (SectionData.getAlignment() < ByteAlignment)
+ SectionData.setAlignment(ByteAlignment);
+
+ SymbolData.setExternal(External);
+
+ Symbol->setSection(*Section);
+
+ if (ByteAlignment != 1)
+ new MCAlignFragment(ByteAlignment, 0, 0, ByteAlignment, &SectionData);
+
+ SymbolData.setFragment(new MCFillFragment(0, 0, Size, &SectionData));
}
// MCStreamer interface
void WinCOFFStreamer::EmitLabel(MCSymbol *Symbol) {
+ // TODO: This is copied almost exactly from the MachOStreamer. Consider
+ // merging into MCObjectStreamer?
+ assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
+ assert(!Symbol->isVariable() && "Cannot emit a variable symbol!");
+ assert(CurSection && "Cannot emit before setting section!");
+
+ Symbol->setSection(*CurSection);
+
+ MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
+
+ // FIXME: This is wasteful, we don't necessarily need to create a data
+ // fragment. Instead, we should mark the symbol as pointing into the data
+ // fragment if it exists, otherwise we should just queue the label and set its
+ // fragment pointer when we emit the next fragment.
+ MCDataFragment *F = getOrCreateDataFragment();
+ assert(!SD.getFragment() && "Unexpected fragment on symbol data!");
+ SD.setFragment(F);
+ SD.setOffset(F->getContents().size());
}
void WinCOFFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) {
- dbg_notimpl("Flag = " << Flag);
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
+ // TODO: This is exactly the same as MachOStreamer. Consider merging into
+ // MCObjectStreamer.
+ getAssembler().getOrCreateSymbolData(*Symbol);
+ AddValueSymbols(Value);
+ Symbol->setVariableValue(Value);
}
void WinCOFFStreamer::EmitSymbolAttribute(MCSymbol *Symbol,
MCSymbolAttr Attribute) {
+ switch (Attribute) {
+ case MCSA_WeakReference:
+ getAssembler().getOrCreateSymbolData(*Symbol).modifyFlags(
+ COFF::SF_WeakReference,
+ COFF::SF_WeakReference);
+ break;
+
+ case MCSA_Global:
+ getAssembler().getOrCreateSymbolData(*Symbol).setExternal(true);
+ break;
+
+ default:
+ llvm_unreachable("unsupported attribute");
+ break;
+ }
}
void WinCOFFStreamer::EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) {
- dbg_notimpl("Symbol = " << Symbol->getName() << ", DescValue = "<< DescValue);
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::BeginCOFFSymbolDef(MCSymbol const *Symbol) {
+ assert(CurSymbol == NULL && "EndCOFFSymbolDef must be called between calls "
+ "to BeginCOFFSymbolDef!");
+ CurSymbol = Symbol;
}
void WinCOFFStreamer::EmitCOFFSymbolStorageClass(int StorageClass) {
+ assert(CurSymbol != NULL && "BeginCOFFSymbolDef must be called first!");
+ assert((StorageClass & ~0xFF) == 0 && "StorageClass must only have data in "
+ "the first byte!");
+
+ getAssembler().getOrCreateSymbolData(*CurSymbol).modifyFlags(
+ StorageClass << COFF::SF_ClassShift,
+ COFF::SF_ClassMask);
}
void WinCOFFStreamer::EmitCOFFSymbolType(int Type) {
+ assert(CurSymbol != NULL && "BeginCOFFSymbolDef must be called first!");
+ assert((Type & ~0xFFFF) == 0 && "Type must only have data in the first 2 "
+ "bytes");
+
+ getAssembler().getOrCreateSymbolData(*CurSymbol).modifyFlags(
+ Type << COFF::SF_TypeShift,
+ COFF::SF_TypeMask);
}
void WinCOFFStreamer::EndCOFFSymbolDef() {
+ assert(CurSymbol != NULL && "BeginCOFFSymbolDef must be called first!");
+ CurSymbol = NULL;
}
void WinCOFFStreamer::EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
- dbg_notimpl("Symbol = " << Symbol->getName() << ", Value = " << *Value);
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
- unsigned ByteAlignment) {
+ unsigned ByteAlignment) {
+ AddCommonSymbol(Symbol, Size, ByteAlignment, true);
}
void WinCOFFStreamer::EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size) {
+ AddCommonSymbol(Symbol, Size, 1, false);
}
void WinCOFFStreamer::EmitZerofill(const MCSection *Section, MCSymbol *Symbol,
- unsigned Size,unsigned ByteAlignment) {
- MCSectionCOFF const *SectionCOFF =
- static_cast<MCSectionCOFF const *>(Section);
-
- dbg_notimpl("Section = " << SectionCOFF->getSectionName() << ", Symbol = " <<
- Symbol->getName() << ", Size = " << Size << ", ByteAlignment = "
- << ByteAlignment);
+ unsigned Size,unsigned ByteAlignment) {
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
uint64_t Size, unsigned ByteAlignment) {
- MCSectionCOFF const *SectionCOFF =
- static_cast<MCSectionCOFF const *>(Section);
-
- dbg_notimpl("Section = " << SectionCOFF->getSectionName() << ", Symbol = " <<
- Symbol->getName() << ", Size = " << Size << ", ByteAlignment = "
- << ByteAlignment);
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
+ // TODO: This is copied exactly from the MachOStreamer. Consider merging into
+ // MCObjectStreamer?
+ getOrCreateDataFragment()->getContents().append(Data.begin(), Data.end());
}
void WinCOFFStreamer::EmitValue(const MCExpr *Value, unsigned Size,
- unsigned AddrSpace) {
+ unsigned AddrSpace) {
+ assert(AddrSpace == 0 && "Address space must be 0!");
+
+ // TODO: This is copied exactly from the MachOStreamer. Consider merging into
+ // MCObjectStreamer?
+ MCDataFragment *DF = getOrCreateDataFragment();
+
+ // Avoid fixups when possible.
+ int64_t AbsValue;
+ if (AddValueSymbols(Value)->EvaluateAsAbsolute(AbsValue)) {
+ // FIXME: Endianness assumption.
+ for (unsigned i = 0; i != Size; ++i)
+ DF->getContents().push_back(uint8_t(AbsValue >> (i * 8)));
+ } else {
+ DF->addFixup(MCFixup::Create(DF->getContents().size(),
+ AddValueSymbols(Value),
+ MCFixup::getKindForSize(Size)));
+ DF->getContents().resize(DF->getContents().size() + Size, 0);
+ }
}
void WinCOFFStreamer::EmitGPRel32Value(const MCExpr *Value) {
- dbg_notimpl("Value = '" << *Value);
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitValueToAlignment(unsigned ByteAlignment,
- int64_t Value,
- unsigned ValueSize,
- unsigned MaxBytesToEmit) {
+ int64_t Value,
+ unsigned ValueSize,
+ unsigned MaxBytesToEmit) {
+ // TODO: This is copied exactly from the MachOStreamer. Consider merging into
+ // MCObjectStreamer?
+ if (MaxBytesToEmit == 0)
+ MaxBytesToEmit = ByteAlignment;
+ new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit,
+ getCurrentSectionData());
+
+ // Update the maximum alignment on the current section if necessary.
+ if (ByteAlignment > getCurrentSectionData()->getAlignment())
+ getCurrentSectionData()->setAlignment(ByteAlignment);
}
void WinCOFFStreamer::EmitCodeAlignment(unsigned ByteAlignment,
- unsigned MaxBytesToEmit = 0) {
+ unsigned MaxBytesToEmit) {
+ // TODO: This is copied exactly from the MachOStreamer. Consider merging into
+ // MCObjectStreamer?
+ if (MaxBytesToEmit == 0)
+ MaxBytesToEmit = ByteAlignment;
+ MCAlignFragment *F = new MCAlignFragment(ByteAlignment, 0, 1, MaxBytesToEmit,
+ getCurrentSectionData());
+ F->setEmitNops(true);
+
+ // Update the maximum alignment on the current section if necessary.
+ if (ByteAlignment > getCurrentSectionData()->getAlignment())
+ getCurrentSectionData()->setAlignment(ByteAlignment);
}
void WinCOFFStreamer::EmitValueToOffset(const MCExpr *Offset,
- unsigned char Value = 0) {
- dbg_notimpl("Offset = '" << *Offset << "', Value = " << Value);
+ unsigned char Value) {
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitFileDirective(StringRef Filename) {
@@ -176,11 +310,24 @@
}
void WinCOFFStreamer::EmitDwarfFileDirective(unsigned FileNo,
- StringRef Filename) {
- dbg_notimpl("FileNo = " << FileNo << ", Filename = '" << Filename << "'");
+ StringRef Filename) {
+ llvm_unreachable("not implemented");
}
void WinCOFFStreamer::EmitInstruction(const MCInst &Instruction) {
+ for (unsigned i = 0, e = Instruction.getNumOperands(); i != e; ++i)
+ if (Instruction.getOperand(i).isExpr())
+ AddValueSymbols(Instruction.getOperand(i).getExpr());
+
+ getCurrentSectionData()->setHasInstructions(true);
+
+ MCInstFragment *Fragment =
+ new MCInstFragment(Instruction, getCurrentSectionData());
+
+ raw_svector_ostream VecOS(Fragment->getCode());
+
+ getAssembler().getEmitter().EncodeInstruction(Instruction, VecOS,
+ Fragment->getFixups());
}
void WinCOFFStreamer::Finish() {
@@ -192,7 +339,10 @@
MCStreamer *createWinCOFFStreamer(MCContext &Context,
TargetAsmBackend &TAB,
MCCodeEmitter &CE,
- raw_ostream &OS) {
- return new WinCOFFStreamer(Context, TAB, CE, OS);
+ raw_ostream &OS,
+ bool RelaxAll) {
+ WinCOFFStreamer *S = new WinCOFFStreamer(Context, TAB, CE, OS);
+ S->getAssembler().setRelaxAll(RelaxAll);
+ return S;
}
}
Modified: llvm/branches/wendling/eh/lib/Support/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Support/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Support/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Support/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -6,6 +6,7 @@
circular_raw_ostream.cpp
CommandLine.cpp
ConstantRange.cpp
+ CrashRecoveryContext.cpp
Debug.cpp
DeltaAlgorithm.cpp
DAGDeltaAlgorithm.cpp
Modified: llvm/branches/wendling/eh/lib/System/ThreadLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/ThreadLocal.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/ThreadLocal.cpp (original)
+++ llvm/branches/wendling/eh/lib/System/ThreadLocal.cpp Sat Jul 31 19:59:02 2010
@@ -67,6 +67,10 @@
return pthread_getspecific(*key);
}
+void ThreadLocalImpl::removeInstance() {
+ setInstance(0);
+}
+
}
#elif defined(LLVM_ON_UNIX)
Modified: llvm/branches/wendling/eh/lib/System/Unix/ThreadLocal.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/Unix/ThreadLocal.inc?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/Unix/ThreadLocal.inc (original)
+++ llvm/branches/wendling/eh/lib/System/Unix/ThreadLocal.inc Sat Jul 31 19:59:02 2010
@@ -22,4 +22,5 @@
ThreadLocalImpl::~ThreadLocalImpl() { }
void ThreadLocalImpl::setInstance(const void* d) { data = const_cast<void*>(d);}
const void* ThreadLocalImpl::getInstance() { return data; }
+void ThreadLocalImpl::removeInstance() { setInstance(0); }
}
Modified: llvm/branches/wendling/eh/lib/System/Win32/ThreadLocal.inc
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/System/Win32/ThreadLocal.inc?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/System/Win32/ThreadLocal.inc (original)
+++ llvm/branches/wendling/eh/lib/System/Win32/ThreadLocal.inc Sat Jul 31 19:59:02 2010
@@ -46,4 +46,8 @@
assert(errorcode != 0);
}
+void ThreadLocalImpl::removeInstance() {
+ setInstance(0);
+}
+
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARM.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARM.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARM.h Sat Jul 31 19:59:02 2010
@@ -98,6 +98,7 @@
FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
FunctionPass *createARMExpandPseudoPass();
+FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
FunctionPass *createARMConstantIslandPass();
FunctionPass *createNEONPreAllocPass();
FunctionPass *createNEONMoveFixPass();
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -15,9 +15,9 @@
#include "ARM.h"
#include "ARMAddressingModes.h"
#include "ARMConstantPoolValue.h"
-#include "ARMGenInstrInfo.inc"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
+#include "ARMGenInstrInfo.inc"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/GlobalValue.h"
@@ -501,7 +501,7 @@
llvm_unreachable("Unknown or unset size field for instr!");
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::DBG_VALUE:
return 0;
@@ -573,48 +573,6 @@
return 0; // Not reached
}
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-///
-bool
-ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
- switch (MI.getOpcode()) {
- default: break;
- case ARM::VMOVS:
- case ARM::VMOVD:
- case ARM::VMOVDneon:
- case ARM::VMOVQ:
- case ARM::VMOVQQ : {
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
- return true;
- }
- case ARM::MOVr:
- case ARM::MOVr_TC:
- case ARM::tMOVr:
- case ARM::tMOVgpr2tgpr:
- case ARM::tMOVtgpr2gpr:
- case ARM::tMOVgpr2gpr:
- case ARM::t2MOVr: {
- assert(MI.getDesc().getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "Invalid ARM MOV instruction");
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
- return true;
- }
- }
-
- return false;
-}
-
unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
@@ -763,8 +721,9 @@
Align);
// tGPR is used sometimes in ARM instructions that need to avoid using
- // certain registers. Just treat it as GPR here.
- if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
+ // certain registers. Just treat it as GPR here. Likewise, rGPR.
+ if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
+ || RC == ARM::rGPRRegisterClass)
RC = ARM::GPRRegisterClass;
switch (RC->getID()) {
@@ -865,7 +824,8 @@
// tGPR is used sometimes in ARM instructions that need to avoid using
// certain registers. Just treat it as GPR here.
- if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
+ if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
+ || RC == ARM::rGPRRegisterClass)
RC = ARM::GPRRegisterClass;
switch (RC->getID()) {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -15,11 +15,12 @@
#define ARMBASEINSTRUCTIONINFO_H
#include "ARM.h"
-#include "ARMRegisterInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetInstrInfo.h"
namespace llvm {
+ class ARMSubtarget;
+ class ARMBaseRegisterInfo;
/// ARMII - This namespace holds all of the target specific flags that
/// instruction info tracks.
@@ -198,7 +199,7 @@
}
class ARMBaseInstrInfo : public TargetInstrInfoImpl {
- const ARMSubtarget& Subtarget;
+ const ARMSubtarget &Subtarget;
protected:
// Can be only subclassed.
explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
@@ -223,7 +224,7 @@
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
- bool AllowModify) const;
+ bool AllowModify = false) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
@@ -262,12 +263,6 @@
///
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -627,12 +627,25 @@
bool ARMBaseRegisterInfo::
needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
+ const Function *F = MF.getFunction();
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
- return (RealignStack &&
- !AFI->isThumb1OnlyFunction() &&
- (MFI->getMaxAlignment() > StackAlign) &&
- !MFI->hasVarSizedObjects());
+ bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
+ F->hasFnAttr(Attribute::StackAlignment));
+
+ // FIXME: Currently we don't support stack realignment for functions with
+ // variable-sized allocas.
+ // FIXME: It's more complicated than this...
+ if (0 && requiresRealignment && MFI->hasVarSizedObjects())
+ report_fatal_error(
+ "Stack realignment in presense of dynamic allocas is not supported");
+
+ // FIXME: This probably isn't the right place for this.
+ if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
+ report_fatal_error(
+ "Stack realignment in thumb1 functions is not supported");
+
+ return requiresRealignment && canRealignStack(MF);
}
bool ARMBaseRegisterInfo::
@@ -710,6 +723,19 @@
return Limit;
}
+static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
+ const ARMBaseInstrInfo &TII) {
+ unsigned FnSize = 0;
+ for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
+ MBBI != E; ++MBBI) {
+ const MachineBasicBlock &MBB = *MBBI;
+ for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
+ I != E; ++I)
+ FnSize += TII.GetInstSizeInBytes(I);
+ }
+ return FnSize;
+}
+
void
ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const {
@@ -807,7 +833,7 @@
bool ForceLRSpill = false;
if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
- unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
+ unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
// Force LR to be spilled if the Thumb function size is > 2048. This enables
// use of BL to implement far jump. If it turns out that it's not needed
// then the branch fix up path will undo it.
@@ -1226,7 +1252,7 @@
// add/sub sp brackets around call sites. Returns true if the call frame is
// included as part of the stack frame.
bool ARMBaseRegisterInfo::
-hasReservedCallFrame(MachineFunction &MF) const {
+hasReservedCallFrame(const MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
// It's not always a good idea to include the call frame as part of the
@@ -1244,7 +1270,7 @@
// is not sufficient here since we still may reference some objects via SP
// even when FP is available in Thumb2 mode.
bool ARMBaseRegisterInfo::
-canSimplifyCallFramePseudos(MachineFunction &MF) const {
+canSimplifyCallFramePseudos(const MachineFunction &MF) const {
return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMBaseRegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -44,7 +44,7 @@
}
}
-struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
+class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
protected:
const ARMBaseInstrInfo &TII;
const ARMSubtarget &STI;
@@ -144,8 +144,8 @@
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
- virtual bool hasReservedCallFrame(MachineFunction &MF) const;
- virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const;
+ virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
+ virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMCodeEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -654,6 +654,19 @@
switch (Opcode) {
default:
llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
+ case ARM::BX:
+ case ARM::BMOVPCRX:
+ case ARM::BXr9:
+ case ARM::BMOVPCRXr9: {
+ // First emit mov lr, pc
+ unsigned Binary = 0x01a0e00f;
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+ emitWordLE(Binary);
+
+ // and then emit the branch.
+ emitMiscBranchInstruction(MI);
+ break;
+ }
case TargetOpcode::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
@@ -662,7 +675,7 @@
}
break;
}
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getMCSymbol());
break;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMConstantIslandPass.cpp Sat Jul 31 19:59:02 2010
@@ -165,7 +165,7 @@
/// HasInlineAsm - True if the function contains inline assembly.
bool HasInlineAsm;
- const TargetInstrInfo *TII;
+ const ARMInstrInfo *TII;
const ARMSubtarget *STI;
ARMFunctionInfo *AFI;
bool isThumb;
@@ -272,7 +272,7 @@
bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
MachineConstantPool &MCP = *MF.getConstantPool();
- TII = MF.getTarget().getInstrInfo();
+ TII = (const ARMInstrInfo*)MF.getTarget().getInstrInfo();
AFI = MF.getInfo<ARMFunctionInfo>();
STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
@@ -323,6 +323,8 @@
// constant pool users.
InitialFunctionScan(MF, CPEMIs);
CPEMIs.clear();
+ DEBUG(dumpBBs());
+
/// Remove dead constant pool entries.
RemoveUnusedCPEntries();
@@ -366,6 +368,8 @@
if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
MadeChange |= UndoLRSpillRestore();
+ DEBUG(errs() << '\n'; dumpBBs());
+
BBSizes.clear();
BBOffsets.clear();
WaterList.clear();
@@ -509,6 +513,10 @@
case ARM::tBR_JTr:
// A Thumb1 table jump may involve padding; for the offsets to
// be right, functions containing these must be 4-byte aligned.
+ // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
+ // table entries. So this code checks whether offset of tBR_JTr + 2
+ // is aligned. That is held in Offset+MBBSize, which already has
+ // 2 added in for the size of the mov pc instruction.
MF.EnsureAlignment(2U);
if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
// FIXME: Add a pseudo ALIGN instruction instead.
@@ -768,28 +776,54 @@
WaterList.insert(IP, OrigBB);
NewWaterList.insert(OrigBB);
- // Figure out how large the first NewMBB is. (It cannot
- // contain a constpool_entry or tablejump.)
- unsigned NewBBSize = 0;
- for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
- I != E; ++I)
- NewBBSize += TII->GetInstSizeInBytes(I);
-
unsigned OrigBBI = OrigBB->getNumber();
unsigned NewBBI = NewBB->getNumber();
- // Set the size of NewBB in BBSizes.
- BBSizes[NewBBI] = NewBBSize;
- // We removed instructions from UserMBB, subtract that off from its size.
- // Add 2 or 4 to the block to count the unconditional branch we added to it.
int delta = isThumb1 ? 2 : 4;
- BBSizes[OrigBBI] -= NewBBSize - delta;
+
+ // Figure out how large the OrigBB is. As the first half of the original
+ // block, it cannot contain a tablejump. The size includes
+ // the new jump we added. (It should be possible to do this without
+ // recounting everything, but it's very confusing, and this is rarely
+ // executed.)
+ unsigned OrigBBSize = 0;
+ for (MachineBasicBlock::iterator I = OrigBB->begin(), E = OrigBB->end();
+ I != E; ++I)
+ OrigBBSize += TII->GetInstSizeInBytes(I);
+ BBSizes[OrigBBI] = OrigBBSize;
// ...and adjust BBOffsets for NewBB accordingly.
BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI];
+ // Figure out how large the NewMBB is. As the second half of the original
+ // block, it may contain a tablejump.
+ unsigned NewBBSize = 0;
+ for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
+ I != E; ++I)
+ NewBBSize += TII->GetInstSizeInBytes(I);
+ // Set the size of NewBB in BBSizes. It does not include any padding now.
+ BBSizes[NewBBI] = NewBBSize;
+
+ MachineInstr* ThumbJTMI = prior(NewBB->end());
+ if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
+ // We've added another 2-byte instruction before this tablejump, which
+ // means we will always need padding if we didn't before, and vice versa.
+
+ // The original offset of the jump instruction was:
+ unsigned OrigOffset = BBOffsets[OrigBBI] + BBSizes[OrigBBI] - delta;
+ if (OrigOffset%4 == 0) {
+ // We had padding before and now we don't. No net change in code size.
+ delta = 0;
+ } else {
+ // We didn't have padding before and now we do.
+ BBSizes[NewBBI] += 2;
+ delta = 4;
+ }
+ }
+
// All BBOffsets following these blocks must be modified.
- AdjustBBOffsetsAfter(NewBB, delta);
+ if (delta)
+ AdjustBBOffsetsAfter(NewBB, delta);
return NewBB;
}
@@ -915,6 +949,10 @@
}
// Thumb1 jump tables require padding. They should be at the end;
// following unconditional branches are removed by AnalyzeBranch.
+ // tBR_JTr expands to a mov pc followed by .align 2 and then the jump
+ // table entries. So this code checks whether offset of tBR_JTr
+ // is aligned; if it is, the offset of the jump table following the
+ // instruction will not be aligned, and we need padding.
MachineInstr *ThumbJTMI = prior(MBB->end());
if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
unsigned NewMIOffset = GetOffsetOf(ThumbJTMI);
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMExpandPseudoInsts.cpp Sat Jul 31 19:59:02 2010
@@ -19,7 +19,7 @@
#include "ARMBaseInstrInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-
+#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
namespace {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelDAGToDAG.cpp Sat Jul 31 19:59:02 2010
@@ -36,6 +36,11 @@
using namespace llvm;
+static cl::opt<bool>
+DisableShifterOp("disable-shifter-op", cl::Hidden,
+ cl::desc("Disable isel of shifter-op"),
+ cl::init(false));
+
//===--------------------------------------------------------------------===//
/// ARMDAGToDAGISel - ARM specific code to select ARM machine
/// instructions for SelectionDAG operations.
@@ -220,6 +225,9 @@
SDValue &BaseReg,
SDValue &ShReg,
SDValue &Opc) {
+ if (DisableShifterOp)
+ return false;
+
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
// Don't match base register only case. That is matched to a separate
@@ -666,6 +674,9 @@
bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
SDValue &BaseReg,
SDValue &Opc) {
+ if (DisableShifterOp)
+ return false;
+
ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
// Don't match base register only case. That is matched to a separate
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.cpp Sat Jul 31 19:59:02 2010
@@ -57,6 +57,13 @@
cl::desc("Generate tail calls (TEMPORARY OPTION)."),
cl::init(true));
+// This option should go away when Machine LICM is smart enough to hoist a
+// reg-to-reg VDUP.
+static cl::opt<bool>
+EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden,
+ cl::desc("Generate VDUP for integer constant splats (TEMPORARY OPTION)."),
+ cl::init(false));
+
static cl::opt<bool>
EnableARMLongCalls("arm-long-calls", cl::Hidden,
cl::desc("Generate calls via indirect call instructions"),
@@ -166,6 +173,7 @@
ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
: TargetLowering(TM, createTLOF(TM)) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
+ RegInfo = TM.getRegisterInfo();
if (Subtarget->isTargetDarwin()) {
// Uses VFP for Thumb libfuncs if available.
@@ -530,6 +538,9 @@
setTargetDAGCombine(ISD::SUB);
setTargetDAGCombine(ISD::MUL);
+ if (Subtarget->hasV6T2Ops())
+ setTargetDAGCombine(ISD::OR);
+
setStackPointerRegisterToSaveRestore(ARM::SP);
if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
@@ -547,6 +558,37 @@
benefitFromCodePlacementOpt = true;
}
+std::pair<const TargetRegisterClass*, uint8_t>
+ARMTargetLowering::findRepresentativeClass(EVT VT) const{
+ const TargetRegisterClass *RRC = 0;
+ uint8_t Cost = 1;
+ switch (VT.getSimpleVT().SimpleTy) {
+ default:
+ return TargetLowering::findRepresentativeClass(VT);
+ // Use DPR as representative register class for all floating point
+ // and vector types. Since there are 32 SPR registers and 32 DPR registers so
+ // the cost is 1 for both f32 and f64.
+ case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
+ case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
+ RRC = ARM::DPRRegisterClass;
+ break;
+ case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
+ case MVT::v4f32: case MVT::v2f64:
+ RRC = ARM::DPRRegisterClass;
+ Cost = 2;
+ break;
+ case MVT::v4i64:
+ RRC = ARM::DPRRegisterClass;
+ Cost = 4;
+ break;
+ case MVT::v8i64:
+ RRC = ARM::DPRRegisterClass;
+ Cost = 8;
+ break;
+ }
+ return std::make_pair(RRC, Cost);
+}
+
const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
@@ -638,6 +680,7 @@
case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
case ARMISD::FMAX: return "ARMISD::FMAX";
case ARMISD::FMIN: return "ARMISD::FMIN";
+ case ARMISD::BFI: return "ARMISD::BFI";
}
}
@@ -656,11 +699,23 @@
return TargetLowering::getRegClassFor(VT);
}
+// Create a fast isel object.
+FastISel *
+ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
+ return ARM::createFastISel(funcInfo);
+}
+
/// getFunctionAlignment - Return the Log2 alignment of this function.
unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
}
+/// getMaximalGlobalOffset - Returns the maximal possible offset which can
+/// be used for loads / stores from the global.
+unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
+ return (Subtarget->isThumb1Only() ? 127 : 4095);
+}
+
Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
unsigned NumVals = N->getNumValues();
if (!NumVals)
@@ -688,6 +743,23 @@
return Sched::RegPressure;
}
+unsigned
+ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
+ switch (RC->getID()) {
+ default:
+ return 0;
+ case ARM::tGPRRegClassID:
+ return 5 - FPDiff;
+ case ARM::GPRRegClassID:
+ return 10 - FPDiff - (Subtarget->isR9Reserved() ? 1 : 0);
+ case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
+ case ARM::DPRRegClassID:
+ return 32 - 10;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Lowering Code
//===----------------------------------------------------------------------===//
@@ -793,8 +865,9 @@
CCState &State, bool CanFail) {
static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
+ static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 };
- unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
+ unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
if (Reg == 0) {
// For the 2nd half of a v2f64, do not just fail.
if (CanFail)
@@ -812,6 +885,10 @@
if (HiRegList[i] == Reg)
break;
+ unsigned T = State.AllocateReg(LoRegList[i]);
+ (void)T;
+ assert(T == LoRegList[i] && "Could not allocate register");
+
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
LocVT, LocInfo));
@@ -1624,6 +1701,10 @@
return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
}
+unsigned ARMTargetLowering::getJumpTableEncoding() const {
+ return MachineJumpTableInfo::EK_Inline;
+}
+
SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
@@ -1945,54 +2026,6 @@
}
SDValue
-ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
- SelectionDAG &DAG) const {
- SDNode *Node = Op.getNode();
- DebugLoc dl = Node->getDebugLoc();
- EVT VT = Node->getValueType(0);
- SDValue Chain = Op.getOperand(0);
- SDValue Size = Op.getOperand(1);
- SDValue Align = Op.getOperand(2);
-
- // Chain the dynamic stack allocation so that it doesn't modify the stack
- // pointer when other instructions are using the stack.
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
-
- unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
- unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
- if (AlignVal > StackAlign)
- // Do this now since selection pass cannot introduce new target
- // independent node.
- Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
-
- // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
- // using a "add r, sp, r" instead. Negate the size now so we don't have to
- // do even more horrible hack later.
- MachineFunction &MF = DAG.getMachineFunction();
- ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- if (AFI->isThumb1OnlyFunction()) {
- bool Negate = true;
- ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
- if (C) {
- uint32_t Val = C->getZExtValue();
- if (Val <= 508 && ((Val & 3) == 0))
- Negate = false;
- }
- if (Negate)
- Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
- }
-
- SDVTList VTList = DAG.getVTList(VT, MVT::Other);
- SDValue Ops1[] = { Chain, Size, Align };
- SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
- Chain = Res.getValue(1);
- Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
- DAG.getIntPtrConstant(0, true), SDValue());
- SDValue Ops2[] = { Res, Chain };
- return DAG.getMergeValues(Ops2, 2, dl);
-}
-
-SDValue
ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG,
DebugLoc dl) const {
@@ -2403,8 +2436,9 @@
bool SeenZero = false;
if (canChangeToInt(LHS, SeenZero, Subtarget) &&
canChangeToInt(RHS, SeenZero, Subtarget) &&
- // If one of the operand is zero, it's safe to ignore the NaN case.
- (FiniteOnlyFPMath() || SeenZero)) {
+ // If one of the operand is zero, it's safe to ignore the NaN case since
+ // we only care about equality comparisons.
+ (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
// If unsafe fp math optimization is enabled and there are no othter uses of
// the CMP operands, and the condition code is EQ oe NE, we can optimize it
// to an integer comparison.
@@ -2587,7 +2621,7 @@
}
// Return LR, which contains the return address. Mark it an implicit live-in.
- unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
+ unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
}
@@ -3230,9 +3264,30 @@
return true;
}
+// If N is an integer constant that can be moved into a register in one
+// instruction, return an SDValue of such a constant (will become a MOV
+// instruction). Otherwise return null.
+static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
+ const ARMSubtarget *ST, DebugLoc dl) {
+ uint64_t Val;
+ if (!isa<ConstantSDNode>(N))
+ return SDValue();
+ Val = cast<ConstantSDNode>(N)->getZExtValue();
+
+ if (ST->isThumb1Only()) {
+ if (Val <= 255 || ~Val <= 255)
+ return DAG.getConstant(Val, MVT::i32);
+ } else {
+ if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
+ return DAG.getConstant(Val, MVT::i32);
+ }
+ return SDValue();
+}
+
// If this is a case we can't handle, return null and let the default
// expansion code take care of it.
-static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
+static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) {
BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
@@ -3292,15 +3347,41 @@
if (isOnlyLowElement)
return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
- // If all elements are constants, fall back to the default expansion, which
- // will generate a load from the constant pool.
+ unsigned EltSize = VT.getVectorElementType().getSizeInBits();
+
+ if (EnableARMVDUPsplat) {
+ // Use VDUP for non-constant splats. For f32 constant splats, reduce to
+ // i32 and try again.
+ if (usesOnlyOneValue && EltSize <= 32) {
+ if (!isConstant)
+ return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
+ if (VT.getVectorElementType().isFloatingPoint()) {
+ SmallVector<SDValue, 8> Ops;
+ for (unsigned i = 0; i < NumElts; ++i)
+ Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
+ Op.getOperand(i)));
+ SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
+ NumElts);
+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
+ LowerBUILD_VECTOR(Val, DAG, ST));
+ }
+ SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
+ if (Val.getNode())
+ return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
+ }
+ }
+
+ // If all elements are constants and the case above didn't get hit, fall back
+ // to the default expansion, which will generate a load from the constant
+ // pool.
if (isConstant)
return SDValue();
- // Use VDUP for non-constant splats.
- unsigned EltSize = VT.getVectorElementType().getSizeInBits();
- if (usesOnlyOneValue && EltSize <= 32)
- return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
+ if (!EnableARMVDUPsplat) {
+ // Use VDUP for non-constant splats.
+ if (usesOnlyOneValue && EltSize <= 32)
+ return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
+ }
// Vectors with 32- or 64-bit elements can be built by directly assigning
// the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
@@ -3597,7 +3678,6 @@
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
case ISD::BR_JT: return LowerBR_JT(Op, DAG);
- case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
case ISD::VASTART: return LowerVASTART(Op, DAG);
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
case ISD::SINT_TO_FP:
@@ -3621,7 +3701,7 @@
case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
case ISD::VSETCC: return LowerVSETCC(Op, DAG);
- case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
+ case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
@@ -4141,30 +4221,43 @@
return SDValue();
}
-/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
-static SDValue PerformADDCombine(SDNode *N,
- TargetLowering::DAGCombinerInfo &DCI) {
- // added by evan in r37685 with no testcase.
- SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
-
+/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
+/// operands N0 and N1. This is a helper for PerformADDCombine that is
+/// called with the default operands, and if that fails, with commuted
+/// operands.
+static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
+ TargetLowering::DAGCombinerInfo &DCI) {
// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
if (Result.getNode()) return Result;
}
- if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
- SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
- if (Result.getNode()) return Result;
- }
return SDValue();
}
+/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
+///
+static SDValue PerformADDCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+
+ // First try with the default operand order.
+ SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
+ if (Result.getNode())
+ return Result;
+
+ // If that didn't work, try again with the operands commuted.
+ return PerformADDCombineWithOperands(N, N1, N0, DCI);
+}
+
/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
+///
static SDValue PerformSUBCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
- // added by evan in r37685 with no testcase.
- SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
@@ -4231,6 +4324,105 @@
return SDValue();
}
+/// PerformORCombine - Target-specific dag combine xforms for ISD::OR
+static SDValue PerformORCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI,
+ const ARMSubtarget *Subtarget) {
+ // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
+ // reasonable.
+
+ // BFI is only available on V6T2+
+ if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
+ return SDValue();
+
+ SelectionDAG &DAG = DCI.DAG;
+ SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
+ DebugLoc DL = N->getDebugLoc();
+ // 1) or (and A, mask), val => ARMbfi A, val, mask
+ // iff (val & mask) == val
+ //
+ // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
+ // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
+ // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
+ // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
+ // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
+ // (i.e., copy a bitfield value into another bitfield of the same width)
+ if (N0.getOpcode() != ISD::AND)
+ return SDValue();
+
+ EVT VT = N->getValueType(0);
+ if (VT != MVT::i32)
+ return SDValue();
+
+
+ // The value and the mask need to be constants so we can verify this is
+ // actually a bitfield set. If the mask is 0xffff, we can do better
+ // via a movt instruction, so don't use BFI in that case.
+ ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+ if (!C)
+ return SDValue();
+ unsigned Mask = C->getZExtValue();
+ if (Mask == 0xffff)
+ return SDValue();
+ SDValue Res;
+ // Case (1): or (and A, mask), val => ARMbfi A, val, mask
+ if ((C = dyn_cast<ConstantSDNode>(N1))) {
+ unsigned Val = C->getZExtValue();
+ if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
+ return SDValue();
+ Val >>= CountTrailingZeros_32(~Mask);
+
+ Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
+ DAG.getConstant(Val, MVT::i32),
+ DAG.getConstant(Mask, MVT::i32));
+
+ // Do not add new nodes to DAG combiner worklist.
+ DCI.CombineTo(N, Res, false);
+ } else if (N1.getOpcode() == ISD::AND) {
+ // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
+ C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+ if (!C)
+ return SDValue();
+ unsigned Mask2 = C->getZExtValue();
+
+ if (ARM::isBitFieldInvertedMask(Mask) &&
+ ARM::isBitFieldInvertedMask(~Mask2) &&
+ (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
+ // The pack halfword instruction works better for masks that fit it,
+ // so use that when it's available.
+ if (Subtarget->hasT2ExtractPack() &&
+ (Mask == 0xffff || Mask == 0xffff0000))
+ return SDValue();
+ // 2a
+ unsigned lsb = CountTrailingZeros_32(Mask2);
+ Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
+ DAG.getConstant(lsb, MVT::i32));
+ Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
+ DAG.getConstant(Mask, MVT::i32));
+ // Do not add new nodes to DAG combiner worklist.
+ DCI.CombineTo(N, Res, false);
+ } else if (ARM::isBitFieldInvertedMask(~Mask) &&
+ ARM::isBitFieldInvertedMask(Mask2) &&
+ (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
+ // The pack halfword instruction works better for masks that fit it,
+ // so use that when it's available.
+ if (Subtarget->hasT2ExtractPack() &&
+ (Mask2 == 0xffff || Mask2 == 0xffff0000))
+ return SDValue();
+ // 2b
+ unsigned lsb = CountTrailingZeros_32(Mask);
+ Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
+ DAG.getConstant(lsb, MVT::i32));
+ Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
+ DAG.getConstant(Mask2, MVT::i32));
+ // Do not add new nodes to DAG combiner worklist.
+ DCI.CombineTo(N, Res, false);
+ }
+ }
+
+ return SDValue();
+}
+
/// PerformVMOVRRDCombine - Target-specific dag combine xforms for
/// ARMISD::VMOVRRD.
static SDValue PerformVMOVRRDCombine(SDNode *N,
@@ -4561,7 +4753,7 @@
static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
// If the target supports NEON, try to use vmax/vmin instructions for f32
- // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
+ // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
// be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
// a NaN; only do the transformation when it matches that behavior.
@@ -4648,6 +4840,7 @@
case ISD::ADD: return PerformADDCombine(N, DCI);
case ISD::SUB: return PerformSUBCombine(N, DCI);
case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
+ case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
@@ -5379,6 +5572,21 @@
return ((int)Sign << 7) | (Exp << 4) | Mantissa;
}
+bool ARM::isBitFieldInvertedMask(unsigned v) {
+ if (v == 0xffffffff)
+ return 0;
+ // there can be 1's on either or both "outsides", all the "inside"
+ // bits must be 0's
+ unsigned int lsb = 0, msb = 31;
+ while (v & (1 << msb)) --msb;
+ while (v & (1 << lsb)) ++lsb;
+ for (unsigned int i = lsb; i <= msb; ++i) {
+ if (v & (1 << i))
+ return 0;
+ }
+ return 1;
+}
+
/// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool.
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMISelLowering.h Sat Jul 31 19:59:02 2010
@@ -17,6 +17,8 @@
#include "ARMSubtarget.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include <vector>
@@ -150,7 +152,10 @@
// Floating-point max and min:
FMAX,
- FMIN
+ FMIN,
+
+ // Bit-field insert
+ BFI
};
}
@@ -162,6 +167,7 @@
/// returns -1.
int getVFPf32Imm(const APFloat &FPImm);
int getVFPf64Imm(const APFloat &FPImm);
+ bool isBitFieldInvertedMask(unsigned v);
}
//===--------------------------------------------------------------------===//
@@ -171,6 +177,8 @@
public:
explicit ARMTargetLowering(TargetMachine &TM);
+ virtual unsigned getJumpTableEncoding(void) const;
+
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result
@@ -255,8 +263,19 @@
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
+ /// getMaximalGlobalOffset - Returns the maximal possible offset which can
+ /// be used for loads / stores from the global.
+ virtual unsigned getMaximalGlobalOffset() const;
+
+ /// createFastISel - This method returns a target specific FastISel object,
+ /// or null if the target does not support "fast" ISel.
+ virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
+
Sched::Preference getSchedulingPreference(SDNode *N) const;
+ unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
+
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
@@ -265,11 +284,17 @@
/// materialize the FP immediate as a load from a constant pool.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
+ protected:
+ std::pair<const TargetRegisterClass*, uint8_t>
+ findRepresentativeClass(EVT VT) const;
+
private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
/// make the right decision when generating code for different targets.
const ARMSubtarget *Subtarget;
+ const TargetRegisterInfo *RegInfo;
+
/// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
///
unsigned ARMPCLabelIndex;
@@ -315,7 +340,6 @@
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
@@ -377,6 +401,10 @@
unsigned BinOpcode) const;
};
+
+ namespace ARM {
+ FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
+ }
}
#endif // ARMISELLOWERING_H
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrFormats.td Sat Jul 31 19:59:02 2010
@@ -313,7 +313,7 @@
}
class ABXIx2<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
- : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, itin,
+ : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, Pseudo, itin,
asm, "", pattern>;
// BR_JT instructions
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrInfo.td Sat Jul 31 19:59:02 2010
@@ -61,6 +61,9 @@
def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
+def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
+ SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
+
// Node definitions.
def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
@@ -131,6 +134,9 @@
def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
[SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
+
+def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
+
//===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions.
//
@@ -221,19 +227,7 @@
/// e.g., 0xf000ffff
def bf_inv_mask_imm : Operand<i32>,
PatLeaf<(imm), [{
- uint32_t v = (uint32_t)N->getZExtValue();
- if (v == 0xffffffff)
- return 0;
- // there can be 1's on either or both "outsides", all the "inside"
- // bits must be 0's
- unsigned int lsb = 0, msb = 31;
- while (v & (1 << msb)) --msb;
- while (v & (1 << lsb)) ++lsb;
- for (unsigned int i = lsb; i <= msb; ++i) {
- if (v & (1 << i))
- return 0;
- }
- return 1;
+ return ARM::isBitFieldInvertedMask(N->getZExtValue());
}] > {
let PrintMethod = "printBitfieldInvMaskImmOperand";
}
@@ -1117,7 +1111,7 @@
let isNotDuplicable = 1, isIndirectBranch = 1 in {
def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
- IIC_Br, "mov\tpc, $target \n$jt",
+ IIC_Br, "mov\tpc, $target$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
let Inst{11-4} = 0b00000000;
let Inst{15-12} = 0b1111;
@@ -1127,7 +1121,7 @@
}
def BR_JTm : JTI<(outs),
(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
- IIC_Br, "ldr\tpc, $target \n$jt",
+ IIC_Br, "ldr\tpc, $target$jt",
[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
imm:$id)]> {
let Inst{15-12} = 0b1111;
@@ -1139,7 +1133,7 @@
}
def BR_JTadd : JTI<(outs),
(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
- IIC_Br, "add\tpc, $target, $idx \n$jt",
+ IIC_Br, "add\tpc, $target, $idx$jt",
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
imm:$id)]> {
let Inst{15-12} = 0b1111;
@@ -1573,8 +1567,12 @@
defm UXTB16 : AI_unary_rrot<0b01101100,
"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
-def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
- (UXTB16r_rot GPR:$Src, 24)>;
+// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
+// The transformation should probably be done as a combiner action
+// instead so we can include a check for masking back in the upper
+// eight bits of the source into the lower eight bits of the result.
+//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
+// (UXTB16r_rot GPR:$Src, 24)>;
def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
(UXTB16r_rot GPR:$Src, 8)>;
@@ -1716,24 +1714,26 @@
// ARM Arithmetic Instruction -- for disassembly only
// GPR:$dst = GPR:$a op GPR:$b
-class AAI<bits<8> op27_20, bits<4> op7_4, string opc>
+class AAI<bits<8> op27_20, bits<4> op7_4, string opc,
+ list<dag> pattern = [/* For disassembly only; pattern left blank */]>
: AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr,
- opc, "\t$dst, $a, $b",
- [/* For disassembly only; pattern left blank */]> {
+ opc, "\t$dst, $a, $b", pattern> {
let Inst{27-20} = op27_20;
let Inst{7-4} = op7_4;
}
// Saturating add/subtract -- for disassembly only
-def QADD : AAI<0b00010000, 0b0101, "qadd">;
+def QADD : AAI<0b00010000, 0b0101, "qadd",
+ [(set GPR:$dst, (int_arm_qadd GPR:$a, GPR:$b))]>;
def QADD16 : AAI<0b01100010, 0b0001, "qadd16">;
def QADD8 : AAI<0b01100010, 0b1001, "qadd8">;
def QASX : AAI<0b01100010, 0b0011, "qasx">;
def QDADD : AAI<0b00010100, 0b0101, "qdadd">;
def QDSUB : AAI<0b00010110, 0b0101, "qdsub">;
def QSAX : AAI<0b01100010, 0b0101, "qsax">;
-def QSUB : AAI<0b00010010, 0b0101, "qsub">;
+def QSUB : AAI<0b00010010, 0b0101, "qsub",
+ [(set GPR:$dst, (int_arm_qsub GPR:$a, GPR:$b))]>;
def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">;
def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">;
def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">;
@@ -1835,6 +1835,9 @@
let Inst{7-4} = 0b0011;
}
+def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSATlsl imm:$pos, GPR:$a, 0)>;
+def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USATlsl imm:$pos, GPR:$a, 0)>;
+
//===----------------------------------------------------------------------===//
// Bitwise Instructions.
//
@@ -1858,11 +1861,11 @@
}
// A8.6.18 BFI - Bitfield insert (Encoding A1)
-// Added for disassembler with the pattern field purposely left blank.
-def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
+def BFI : I<(outs GPR:$dst), (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm),
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
- "bfi", "\t$dst, $src, $imm", "",
- [/* For disassembly only; pattern left blank */]>,
+ "bfi", "\t$dst, $val, $imm", "$src = $dst",
+ [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val,
+ bf_inv_mask_imm:$imm))]>,
Requires<[IsARM, HasV6T2]> {
let Inst{27-21} = 0b0111110;
let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrNEON.td Sat Jul 31 19:59:02 2010
@@ -100,14 +100,14 @@
def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
- unsigned EltBits;
+ unsigned EltBits = 0;
uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
return (EltBits == 32 && EltVal == 0);
}]>;
def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
- unsigned EltBits;
+ unsigned EltBits = 0;
uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
return (EltBits == 8 && EltVal == 0xff);
}]>;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb.td Sat Jul 31 19:59:02 2010
@@ -378,7 +378,7 @@
def tBR_JTr : T1JTI<(outs),
(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
- IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
+ IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
Encoding16 {
let Inst{15-7} = 0b010001101;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb2.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMInstrThumb2.td Sat Jul 31 19:59:02 2010
@@ -32,7 +32,7 @@
ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
[shl,srl,sra,rotr]> {
let PrintMethod = "printT2SOOperand";
- let MIOperandInfo = (ops GPR, i32imm);
+ let MIOperandInfo = (ops rGPR, i32imm);
}
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
@@ -162,7 +162,7 @@
def t2addrmode_so_reg : Operand<i32>,
ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
let PrintMethod = "printT2AddrModeSoRegOperand";
- let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
+ let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
}
@@ -176,9 +176,9 @@
multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Cheap = 0, bit ReMat = 0> {
// shifted imm
- def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
+ def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
opc, "\t$dst, $src",
- [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
+ [(set rGPR:$dst, (opnode t2_so_imm:$src))]> {
let isAsCheapAsAMove = Cheap;
let isReMaterializable = ReMat;
let Inst{31-27} = 0b11110;
@@ -189,9 +189,9 @@
let Inst{15} = 0;
}
// register
- def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
+ def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVr,
opc, ".w\t$dst, $src",
- [(set GPR:$dst, (opnode GPR:$src))]> {
+ [(set rGPR:$dst, (opnode rGPR:$src))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -202,9 +202,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
+ def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi,
opc, ".w\t$dst, $src",
- [(set GPR:$dst, (opnode t2_so_reg:$src))]> {
+ [(set rGPR:$dst, (opnode t2_so_reg:$src))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -219,9 +219,9 @@
multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0, string wide =""> {
// shifted imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
+ def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, "\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
@@ -229,9 +229,9 @@
let Inst{15} = 0;
}
// register
- def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
+ def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -242,9 +242,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
+ def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, !strconcat(wide, "\t$dst, $lhs, $rhs"),
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -263,9 +263,9 @@
/// T2I_bin_irs counterpart.
multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
+ def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
opc, ".w\t$dst, $rhs, $lhs",
- [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
@@ -273,9 +273,9 @@
let Inst{15} = 0;
}
// shifted register
- def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
+ def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
opc, "\t$dst, $rhs, $lhs",
- [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -289,9 +289,9 @@
multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> {
// shifted imm
- def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
+ def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
@@ -299,9 +299,9 @@
let Inst{15} = 0;
}
// register
- def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
+ def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -312,9 +312,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
+ def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
!strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -328,9 +328,9 @@
multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
bit Commutable = 0> {
// shifted imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
+ def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24} = 1;
@@ -339,9 +339,9 @@
let Inst{15} = 0;
}
// 12-bit imm
- def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
+ def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi,
!strconcat(opc, "w"), "\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24} = 0;
@@ -350,9 +350,9 @@
let Inst{15} = 0;
}
// register
- def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
+ def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -364,9 +364,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
+ def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
+ [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24} = 1;
@@ -382,9 +382,9 @@
multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> {
// shifted imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
+ def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, "\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
@@ -393,9 +393,9 @@
let Inst{15} = 0;
}
// register
- def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
+ def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
Requires<[IsThumb2]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
@@ -407,9 +407,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
+ def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -423,9 +423,9 @@
multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
bit Commutable = 0> {
// shifted imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
+ def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi,
opc, "\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>,
Requires<[IsThumb2]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
@@ -434,9 +434,9 @@
let Inst{15} = 0;
}
// register
- def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
+ def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>,
Requires<[IsThumb2]> {
let isCommutable = Commutable;
let Inst{31-27} = 0b11101;
@@ -448,9 +448,9 @@
let Inst{5-4} = 0b00; // type
}
// shifted register
- def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
+ def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
+ [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>,
Requires<[IsThumb2]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -465,9 +465,9 @@
let Defs = [CPSR] in {
multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
// shifted imm
- def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
+ def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
!strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs",
- [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = opcod;
@@ -475,9 +475,9 @@
let Inst{15} = 0;
}
// shifted register
- def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
+ def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
!strconcat(opc, "s"), "\t$dst, $rhs, $lhs",
- [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -490,18 +490,18 @@
// rotate operation that produces a value.
multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
// 5-bit imm
- def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
+ def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> {
+ [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> {
let Inst{31-27} = 0b11101;
let Inst{26-21} = 0b010010;
let Inst{19-16} = 0b1111; // Rn
let Inst{5-4} = opcod;
}
// register
- def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr,
+ def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr,
opc, ".w\t$dst, $lhs, $rhs",
- [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
+ [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-21} = opcod;
@@ -527,9 +527,9 @@
let Inst{11-8} = 0b1111; // Rd
}
// register
- def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
+ def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), IIC_iCMPr,
opc, ".w\t$lhs, $rhs",
- [(opnode GPR:$lhs, GPR:$rhs)]> {
+ [(opnode GPR:$lhs, rGPR:$rhs)]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = opcod;
@@ -639,9 +639,9 @@
/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
- def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+ def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
opc, ".w\t$dst, $src",
- [(set GPR:$dst, (opnode GPR:$src))]> {
+ [(set rGPR:$dst, (opnode rGPR:$src))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
@@ -650,9 +650,9 @@
let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
- def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
+ def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, ".w\t$dst, $src, ror $rot",
- [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> {
+ [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
@@ -665,9 +665,9 @@
// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
- def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+ def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
opc, "\t$dst, $src",
- [(set GPR:$dst, (opnode GPR:$src))]>,
+ [(set rGPR:$dst, (opnode rGPR:$src))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -677,9 +677,9 @@
let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
- def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
+ def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, "\t$dst, $src, ror $rot",
- [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
+ [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -694,7 +694,7 @@
// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
// supported yet.
multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> {
- def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+ def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
opc, "\t$dst, $src", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -704,7 +704,7 @@
let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
- def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
+ def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, "\t$dst, $src, ror $rot", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -719,9 +719,9 @@
/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24.
multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
- def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
+ def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
opc, "\t$dst, $LHS, $RHS",
- [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
+ [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -730,10 +730,10 @@
let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
- def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
+ def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
- [(set GPR:$dst, (opnode GPR:$LHS,
- (rotr GPR:$RHS, rot_imm:$rot)))]>,
+ [(set rGPR:$dst, (opnode rGPR:$LHS,
+ (rotr rGPR:$RHS, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -747,7 +747,7 @@
// DO variant - disassembly only, no pattern
multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> {
- def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
+ def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr,
opc, "\t$dst, $LHS, $RHS", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -756,7 +756,7 @@
let Inst{7} = 1;
let Inst{5-4} = 0b00; // rotate
}
- def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
+ def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot),
IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
@@ -779,7 +779,7 @@
// assembler.
let neverHasSideEffects = 1 in {
let isReMaterializable = 1 in
-def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
+def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
"adr$p.w\t$dst, #$label", []> {
let Inst{31-27} = 0b11110;
let Inst{25-24} = 0b10;
@@ -790,7 +790,7 @@
let Inst{15} = 0;
}
} // neverHasSideEffects
-def t2LEApcrelJT : T2XI<(outs GPR:$dst),
+def t2LEApcrelJT : T2XI<(outs rGPR:$dst),
(ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
"adr$p.w\t$dst, #${label}_${id}", []> {
let Inst{31-27} = 0b11110;
@@ -866,9 +866,9 @@
}
// Signed and unsigned division on v7-M
-def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
+def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
"sdiv", "\t$dst, $a, $b",
- [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>,
+ [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>,
Requires<[HasDivide]> {
let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011100;
@@ -877,9 +877,9 @@
let Inst{7-4} = 0b1111;
}
-def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
+def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi,
"udiv", "\t$dst, $a, $b",
- [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>,
+ [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>,
Requires<[HasDivide]> {
let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011101;
@@ -889,6 +889,9 @@
}
// Pseudo instruction that will expand into a t2SUBrSPi + a copy.
+// FIXME: Now that we have rGPR, do we need these pseudos? It seems
+// that the coalescer will now properly know how to do the right
+// thing without them.
let usesCustomInserter = 1 in { // Expanded after instruction selection.
def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>;
@@ -917,10 +920,10 @@
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
// Load doubleword
-def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
+def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
(ins t2addrmode_imm8s4:$addr),
IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>;
-def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2),
+def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2),
(ins i32imm:$addr), IIC_iLoadi,
"ldrd", "\t$dst1, $addr", []> {
let Inst{19-16} = 0b1111; // Rn
@@ -967,6 +970,11 @@
def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
(t2LDRHpci tconstpool:$addr)>;
+// FIXME: The destination register of the loads and stores can't be PC, but
+// can be SP. We need another regclass (similar to rGPR) to represent
+// that. Not a pressing issue since these are selected manually,
+// not via pattern.
+
// Indexed loads
let mayLoad = 1, neverHasSideEffects = 1 in {
def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb),
@@ -1286,9 +1294,9 @@
// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in
-def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
+def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi,
"mov", ".w\t$dst, $src",
- [(set GPR:$dst, t2_so_imm:$src)]> {
+ [(set rGPR:$dst, t2_so_imm:$src)]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
let Inst{24-21} = 0b0010;
@@ -1298,9 +1306,9 @@
}
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
+def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
"movw", "\t$dst, $src",
- [(set GPR:$dst, imm0_65535:$src)]> {
+ [(set rGPR:$dst, imm0_65535:$src)]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-21} = 0b0010;
@@ -1309,10 +1317,10 @@
}
let Constraints = "$src = $dst" in
-def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi,
+def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
"movt", "\t$dst, $imm",
- [(set GPR:$dst,
- (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> {
+ [(set rGPR:$dst,
+ (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-21} = 0b0110;
@@ -1320,7 +1328,7 @@
let Inst{15} = 0;
}
-def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
+def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
//===----------------------------------------------------------------------===//
// Extend Instructions.
@@ -1352,10 +1360,14 @@
defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
-def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
- (t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
-def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
- (t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
+// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
+// The transformation should probably be done as a combiner action
+// instead so we can include a check for masking back in the upper
+// eight bits of the source into the lower eight bits of the result.
+//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
+// (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
+def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
+ (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
@@ -1409,18 +1421,18 @@
def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
let AddedComplexity = 1 in
-def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm),
- (t2SUBSri GPR:$src, imm0_255_neg:$imm)>;
-def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm),
- (t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>;
+def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm),
+ (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
+def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm),
+ (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
// The with-carry-in form matches bitwise not instead of the negation.
// Effectively, the inverse interpretation of the carry flag already accounts
// for part of the negation.
let AddedComplexity = 1 in
-def : T2Pat<(adde GPR:$src, imm0_255_not:$imm),
- (t2SBCSri GPR:$src, imm0_255_not:$imm)>;
-def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm),
- (t2SBCSri GPR:$src, t2_so_imm_not:$imm)>;
+def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm),
+ (t2SBCSri rGPR:$src, imm0_255_not:$imm)>;
+def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm),
+ (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>;
// Select Bytes -- for disassembly only
@@ -1437,9 +1449,10 @@
// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
// And Miscellaneous operations -- for disassembly only
-class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc>
- : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc,
- "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> {
+class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
+ list<dag> pat = [/* For disassembly only; pattern left blank */]>
+ : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc,
+ "\t$dst, $a, $b", pat> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0101;
let Inst{22-20} = op22_20;
@@ -1449,14 +1462,16 @@
// Saturating add/subtract -- for disassembly only
-def t2QADD : T2I_pam<0b000, 0b1000, "qadd">;
+def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
+ [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>;
def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">;
def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">;
def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
-def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">;
+def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
+ [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>;
def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
@@ -1498,17 +1513,18 @@
// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
-def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b),
NoItinerary, "usad8", "\t$dst, $a, $b", []> {
let Inst{15-12} = 0b1111;
}
-def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst),
- (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8",
+def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8",
"\t$dst, $a, $b, $acc", []>;
// Signed/Unsigned saturate -- for disassembly only
-def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
+def t2SSATlsl:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1518,7 +1534,7 @@
let Inst{21} = 0; // sh = '0'
}
-def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
+def t2SSATasr:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1528,7 +1544,7 @@
let Inst{21} = 1; // sh = '1'
}
-def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
+def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
"ssat16", "\t$dst, $bit_pos, $a",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1540,7 +1556,7 @@
let Inst{7-6} = 0b00; // imm2 = '00'
}
-def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
+def t2USATlsl:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1550,7 +1566,7 @@
let Inst{21} = 0; // sh = '0'
}
-def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt),
+def t2USATasr:T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos,rGPR:$a,i32imm:$shamt),
NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1560,7 +1576,7 @@
let Inst{21} = 1; // sh = '1'
}
-def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary,
+def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary,
"usat16", "\t$dst, $bit_pos, $a",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -1572,6 +1588,9 @@
let Inst{7-6} = 0b00; // imm2 = '00'
}
+def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSATlsl imm:$pos, GPR:$a, 0)>;
+def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USATlsl imm:$pos, GPR:$a, 0)>;
+
//===----------------------------------------------------------------------===//
// Shift and rotate Instructions.
//
@@ -1582,9 +1601,9 @@
defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
let Uses = [CPSR] in {
-def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
+def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
"rrx", "\t$dst, $src",
- [(set GPR:$dst, (ARMrrx GPR:$src))]> {
+ [(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
@@ -1596,9 +1615,9 @@
}
let Defs = [CPSR] in {
-def t2MOVsrl_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
+def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
"lsrs", ".w\t$dst, $src, #1",
- [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> {
+ [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
@@ -1609,9 +1628,9 @@
let Inst{14-12} = 0b000;
let Inst{7-6} = 0b01;
}
-def t2MOVsra_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
+def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
"asrs", ".w\t$dst, $src, #1",
- [(set GPR:$dst, (ARMsra_flag GPR:$src))]> {
+ [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010;
@@ -1639,9 +1658,9 @@
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
let Constraints = "$src = $dst" in
-def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
+def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
IIC_iUNAsi, "bfc", "\t$dst, $imm",
- [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> {
+ [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b10110;
@@ -1649,7 +1668,7 @@
let Inst{15} = 0;
}
-def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
+def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
@@ -1657,7 +1676,7 @@
let Inst{15} = 0;
}
-def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
+def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
@@ -1666,10 +1685,12 @@
}
// A8.6.18 BFI - Bitfield insert (Encoding T1)
-// Added for disassembler with the pattern field purposely left blank.
-// FIXME: Utilize this instruction in codgen.
-def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
- IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> {
+let Constraints = "$src = $dst" in
+def t2BFI : T2I<(outs rGPR:$dst),
+ (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
+ IIC_iALUi, "bfi", "\t$dst, $val, $imm",
+ [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
+ bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b10110;
@@ -1684,12 +1705,13 @@
defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
-def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
- (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
+let AddedComplexity = 1 in
+def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
+ (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
-def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
- (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
+def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
+ (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
Requires<[IsThumb2]>;
def : T2Pat<(t2_so_imm_not:$src),
@@ -1699,9 +1721,9 @@
// Multiply Instructions.
//
let isCommutable = 1 in
-def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
"mul", "\t$dst, $a, $b",
- [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> {
+ [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
@@ -1709,9 +1731,9 @@
let Inst{7-4} = 0b0000; // Multiply
}
-def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"mla", "\t$dst, $a, $b, $c",
- [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> {
+ [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
@@ -1719,9 +1741,9 @@
let Inst{7-4} = 0b0000; // Multiply
}
-def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"mls", "\t$dst, $a, $b, $c",
- [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> {
+ [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
@@ -1732,7 +1754,7 @@
// Extra precision multiplies with low / high results
let neverHasSideEffects = 1 in {
let isCommutable = 1 in {
-def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
+def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
"smull", "\t$ldst, $hdst, $a, $b", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
@@ -1740,7 +1762,7 @@
let Inst{7-4} = 0b0000;
}
-def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64,
+def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMUL64,
"umull", "\t$ldst, $hdst, $a, $b", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
@@ -1750,7 +1772,7 @@
} // isCommutable
// Multiply + accumulate
-def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
+def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
"smlal", "\t$ldst, $hdst, $a, $b", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
@@ -1758,7 +1780,7 @@
let Inst{7-4} = 0b0000;
}
-def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
+def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
"umlal", "\t$ldst, $hdst, $a, $b", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
@@ -1766,7 +1788,7 @@
let Inst{7-4} = 0b0000;
}
-def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64,
+def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), (ins rGPR:$a, rGPR:$b), IIC_iMAC64,
"umaal", "\t$ldst, $hdst, $a, $b", []>{
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0111;
@@ -1778,9 +1800,9 @@
// Rounding variants of the below included for disassembly only
// Most significant word multiply
-def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
"smmul", "\t$dst, $a, $b",
- [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> {
+ [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
@@ -1788,7 +1810,7 @@
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
-def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
"smmulr", "\t$dst, $a, $b", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
@@ -1797,9 +1819,9 @@
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
-def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"smmla", "\t$dst, $a, $b, $c",
- [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> {
+ [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
@@ -1807,7 +1829,7 @@
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
-def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2SMMLAR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"smmlar", "\t$dst, $a, $b, $c", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
@@ -1816,9 +1838,9 @@
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
-def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2SMMLS : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"smmls", "\t$dst, $a, $b, $c",
- [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> {
+ [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
@@ -1826,7 +1848,7 @@
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
-def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32,
+def t2SMMLSR : T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32,
"smmlsr", "\t$dst, $a, $b, $c", []> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
@@ -1836,10 +1858,10 @@
}
multiclass T2I_smul<string opc, PatFrag opnode> {
- def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+ def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
!strconcat(opc, "bb"), "\t$dst, $a, $b",
- [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
- (sext_inreg GPR:$b, i16)))]> {
+ [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
+ (sext_inreg rGPR:$b, i16)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1848,10 +1870,10 @@
let Inst{5-4} = 0b00;
}
- def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+ def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
!strconcat(opc, "bt"), "\t$dst, $a, $b",
- [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
- (sra GPR:$b, (i32 16))))]> {
+ [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16),
+ (sra rGPR:$b, (i32 16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1860,10 +1882,10 @@
let Inst{5-4} = 0b01;
}
- def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+ def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
!strconcat(opc, "tb"), "\t$dst, $a, $b",
- [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
- (sext_inreg GPR:$b, i16)))]> {
+ [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
+ (sext_inreg rGPR:$b, i16)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1872,10 +1894,10 @@
let Inst{5-4} = 0b10;
}
- def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32,
+ def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32,
!strconcat(opc, "tt"), "\t$dst, $a, $b",
- [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
- (sra GPR:$b, (i32 16))))]> {
+ [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)),
+ (sra rGPR:$b, (i32 16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1884,10 +1906,10 @@
let Inst{5-4} = 0b11;
}
- def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
+ def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
!strconcat(opc, "wb"), "\t$dst, $a, $b",
- [(set GPR:$dst, (sra (opnode GPR:$a,
- (sext_inreg GPR:$b, i16)), (i32 16)))]> {
+ [(set rGPR:$dst, (sra (opnode rGPR:$a,
+ (sext_inreg rGPR:$b, i16)), (i32 16)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
@@ -1896,10 +1918,10 @@
let Inst{5-4} = 0b00;
}
- def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16,
+ def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16,
!strconcat(opc, "wt"), "\t$dst, $a, $b",
- [(set GPR:$dst, (sra (opnode GPR:$a,
- (sra GPR:$b, (i32 16))), (i32 16)))]> {
+ [(set rGPR:$dst, (sra (opnode rGPR:$a,
+ (sra rGPR:$b, (i32 16))), (i32 16)))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
@@ -1911,11 +1933,11 @@
multiclass T2I_smla<string opc, PatFrag opnode> {
- def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc,
- (opnode (sext_inreg GPR:$a, i16),
- (sext_inreg GPR:$b, i16))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc,
+ (opnode (sext_inreg rGPR:$a, i16),
+ (sext_inreg rGPR:$b, i16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1924,10 +1946,10 @@
let Inst{5-4} = 0b00;
}
- def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
- (sra GPR:$b, (i32 16)))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16),
+ (sra rGPR:$b, (i32 16)))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1936,10 +1958,10 @@
let Inst{5-4} = 0b01;
}
- def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
- (sext_inreg GPR:$b, i16))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
+ (sext_inreg rGPR:$b, i16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1948,10 +1970,10 @@
let Inst{5-4} = 0b10;
}
- def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
- (sra GPR:$b, (i32 16)))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)),
+ (sra rGPR:$b, (i32 16)))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
@@ -1960,10 +1982,10 @@
let Inst{5-4} = 0b11;
}
- def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
- (sext_inreg GPR:$b, i16)), (i32 16))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
+ (sext_inreg rGPR:$b, i16)), (i32 16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
@@ -1972,10 +1994,10 @@
let Inst{5-4} = 0b00;
}
- def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16,
+ def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16,
!strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
- [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
- (sra GPR:$b, (i32 16))), (i32 16))))]> {
+ [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a,
+ (sra rGPR:$b, (i32 16))), (i32 16))))]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
@@ -1989,61 +2011,61 @@
defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
-def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
+def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
[/* For disassembly only; pattern left blank */]>;
-def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
+def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
[/* For disassembly only; pattern left blank */]>;
-def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
+def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
[/* For disassembly only; pattern left blank */]>;
-def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
+def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
[/* For disassembly only; pattern left blank */]>;
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
// These are for disassembly only.
-def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> {
let Inst{15-12} = 0b1111;
}
-def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> {
let Inst{15-12} = 0b1111;
}
-def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> {
let Inst{15-12} = 0b1111;
}
-def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b),
IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> {
let Inst{15-12} = 0b1111;
}
-def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst),
- (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad",
+def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad",
"\t$dst, $a, $b, $acc", []>;
-def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst),
- (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx",
+def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx",
"\t$dst, $a, $b, $acc", []>;
-def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst),
- (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd",
+def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd",
"\t$dst, $a, $b, $acc", []>;
-def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst),
- (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx",
+def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst),
+ (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx",
"\t$dst, $a, $b, $acc", []>;
-def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald",
+def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald",
"\t$ldst, $hdst, $a, $b", []>;
-def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx",
+def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx",
"\t$ldst, $hdst, $a, $b", []>;
-def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld",
+def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld",
"\t$ldst, $hdst, $a, $b", []>;
-def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst),
- (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx",
+def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst),
+ (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx",
"\t$ldst, $hdst, $a, $b", []>;
//===----------------------------------------------------------------------===//
@@ -2061,35 +2083,35 @@
let Inst{5-4} = op2;
}
-def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>;
+def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
+ "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
-def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
"rbit", "\t$dst, $src",
- [(set GPR:$dst, (ARMrbit GPR:$src))]>;
+ [(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
-def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
- "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>;
+def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
+ "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
-def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
"rev16", ".w\t$dst, $src",
- [(set GPR:$dst,
- (or (and (srl GPR:$src, (i32 8)), 0xFF),
- (or (and (shl GPR:$src, (i32 8)), 0xFF00),
- (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
- (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
+ [(set rGPR:$dst,
+ (or (and (srl rGPR:$src, (i32 8)), 0xFF),
+ (or (and (shl rGPR:$src, (i32 8)), 0xFF00),
+ (or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
+ (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
-def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
+def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
"revsh", ".w\t$dst, $src",
- [(set GPR:$dst,
+ [(set rGPR:$dst,
(sext_inreg
- (or (srl (and GPR:$src, 0xFF00), (i32 8)),
- (shl GPR:$src, (i32 8))), i16))]>;
+ (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
+ (shl rGPR:$src, (i32 8))), i16))]>;
-def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
+def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
- [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
- (and (shl GPR:$src2, (i32 imm:$shamt)),
+ [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
+ (and (shl rGPR:$src2, (i32 imm:$shamt)),
0xFFFF0000)))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11101;
@@ -2100,17 +2122,17 @@
}
// Alternate cases for PKHBT where identities eliminate some nodes.
-def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
- (t2PKHBT GPR:$src1, GPR:$src2, 0)>,
+def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
+ (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
Requires<[HasT2ExtractPack]>;
-def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
- (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>,
+def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$shamt)),
+ (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$shamt)>,
Requires<[HasT2ExtractPack]>;
-def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
+def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
- [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
- (and (sra GPR:$src2, imm16_31:$shamt),
+ [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
+ (and (sra rGPR:$src2, imm16_31:$shamt),
0xFFFF)))]>,
Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11101;
@@ -2122,12 +2144,12 @@
// Alternate cases for PKHTB where identities eliminate some nodes. Note that
// a shift amount of 0 is *not legal* here, it is PKHBT instead.
-def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
- (t2PKHTB GPR:$src1, GPR:$src2, 16)>,
+def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, (i32 16))),
+ (t2PKHTB rGPR:$src1, rGPR:$src2, 16)>,
Requires<[HasT2ExtractPack]>;
-def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
- (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
- (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>,
+def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
+ (and (srl rGPR:$src2, imm1_15:$shamt), 0xFFFF)),
+ (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$shamt)>,
Requires<[HasT2ExtractPack]>;
//===----------------------------------------------------------------------===//
@@ -2166,9 +2188,9 @@
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in {
-def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr,
+def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
"mov", ".w\t$dst, $true",
- [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
+ [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst"> {
let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01;
@@ -2179,9 +2201,9 @@
let Inst{7-4} = 0b0000;
}
-def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true),
+def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
IIC_iCMOVi, "mov", ".w\t$dst, $true",
-[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
+[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst"> {
let Inst{31-27} = 0b11110;
let Inst{25} = 0;
@@ -2201,20 +2223,20 @@
let Inst{19-16} = 0b1111; // Rn
let Inst{5-4} = opcod; // Shift type.
}
-def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst),
- (ins GPR:$false, GPR:$true, i32imm:$rhs),
+def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst),
+ (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
-def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst),
- (ins GPR:$false, GPR:$true, i32imm:$rhs),
+def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst),
+ (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
-def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst),
- (ins GPR:$false, GPR:$true, i32imm:$rhs),
+def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst),
+ (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
-def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst),
- (ins GPR:$false, GPR:$true, i32imm:$rhs),
+def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
+ (ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
} // neverHasSideEffects
@@ -2329,13 +2351,13 @@
}
let mayLoad = 1 in {
-def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
+def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]",
"", []>;
-def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
+def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]",
"", []>;
-def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone,
+def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone,
Size4Bytes, NoItinerary,
"ldrex", "\t$dest, [$ptr]", "",
[]> {
@@ -2344,20 +2366,20 @@
let Inst{11-8} = 0b1111;
let Inst{7-0} = 0b00000000; // imm8 = 0
}
-def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr),
+def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr),
AddrModeNone, Size4Bytes, NoItinerary,
"ldrexd", "\t$dest, $dest2, [$ptr]", "",
[], {?, ?, ?, ?}>;
}
let mayStore = 1, Constraints = "@earlyclobber $success" in {
-def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
+def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
AddrModeNone, Size4Bytes, NoItinerary,
"strexb", "\t$success, $src, [$ptr]", "", []>;
-def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr),
+def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
AddrModeNone, Size4Bytes, NoItinerary,
"strexh", "\t$success, $src, [$ptr]", "", []>;
-def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr),
+def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr),
AddrModeNone, Size4Bytes, NoItinerary,
"strex", "\t$success, $src, [$ptr]", "",
[]> {
@@ -2365,8 +2387,8 @@
let Inst{26-20} = 0b0000100;
let Inst{7-0} = 0b00000000; // imm8 = 0
}
-def t2STREXD : T2I_strex<0b11, (outs GPR:$success),
- (ins GPR:$src, GPR:$src2, GPR:$ptr),
+def t2STREXD : T2I_strex<0b11, (outs rGPR:$success),
+ (ins rGPR:$src, rGPR:$src2, rGPR:$ptr),
AddrModeNone, Size4Bytes, NoItinerary,
"strexd", "\t$success, $src, $src2, [$ptr]", "", [],
{?, ?, ?, ?}>;
@@ -2482,7 +2504,7 @@
def t2BR_JT :
T2JTI<(outs),
(ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "mov\tpc, $target\n$jt",
+ IIC_Br, "mov\tpc, $target$jt",
[(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0100100;
@@ -2496,7 +2518,7 @@
def t2TBB :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "tbb\t$index\n$jt", []> {
+ IIC_Br, "tbb\t$index$jt", []> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
@@ -2507,7 +2529,7 @@
def t2TBH :
T2JTI<(outs),
(ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
- IIC_Br, "tbh\t$index\n$jt", []> {
+ IIC_Br, "tbh\t$index$jt", []> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0001101;
let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction)
@@ -2560,7 +2582,7 @@
// Branch and Exchange Jazelle -- for disassembly only
// Rm = Inst{19-16}
-def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
+def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
@@ -2647,25 +2669,25 @@
}
// Return From Exception is a system instruction -- for disassembly only
-def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!",
+def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0000011; // W = 1
}
-def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base",
+def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0000001; // W = 0
}
-def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!",
+def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0011011; // W = 1
}
-def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base",
+def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11101;
let Inst{26-20} = 0b0011001; // W = 0
@@ -2676,26 +2698,26 @@
//
// Two piece so_imms.
-def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
- (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS),
+ (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
(t2_so_imm2part_2 imm:$RHS))>;
-def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
- (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS),
+ (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
(t2_so_imm2part_2 imm:$RHS))>;
-def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
- (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS),
+ (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
(t2_so_imm2part_2 imm:$RHS))>;
-def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS),
- (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
+def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
+ (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)),
(t2_so_neg_imm2part_2 imm:$RHS))>;
// 32-bit immediate using movw + movt.
// This is a single pseudo instruction to make it re-materializable. Remove
// when we can do generalized remat.
let isReMaterializable = 1 in
-def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi,
+def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
- [(set GPR:$dst, (i32 imm:$src))]>;
+ [(set rGPR:$dst, (i32 imm:$src))]>;
// ConstantPool, GlobalAddress, and JumpTable
def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
@@ -2723,7 +2745,7 @@
//
// Rd = Instr{11-8}
-def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
+def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
@@ -2734,7 +2756,7 @@
}
// Rd = Instr{11-8}
-def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
+def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{26} = 0;
@@ -2745,7 +2767,7 @@
}
// Rn = Inst{19-16}
-def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
+def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
"\tcpsr$mask, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
@@ -2757,7 +2779,7 @@
}
// Rn = Inst{19-16}
-def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr",
+def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr",
"\tspsr$mask, $src",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMRegisterInfo.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMRegisterInfo.td Sat Jul 31 19:59:02 2010
@@ -318,6 +318,115 @@
}];
}
+// restricted GPR register class. Many Thumb2 instructions allow the full
+// register range for operands, but have undefined behaviours when PC
+// or SP (R13 or R15) are used. The ARM ARM refers to these operands
+// via the BadReg() pseudo-code description.
+def rGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
+ R7, R8, R9, R10, R11, R12, LR]> {
+ let MethodProtos = [{
+ iterator allocation_order_begin(const MachineFunction &MF) const;
+ iterator allocation_order_end(const MachineFunction &MF) const;
+ }];
+ let MethodBodies = [{
+ // FP is R11, R9 is available.
+ static const unsigned ARM_rGPRAO_1[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R9, ARM::R10,
+ ARM::R11 };
+ // FP is R11, R9 is not available.
+ static const unsigned ARM_rGPRAO_2[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7,
+ ARM::R8, ARM::R10,
+ ARM::R11 };
+ // FP is R7, R9 is available as non-callee-saved register.
+ // This is used by Darwin.
+ static const unsigned ARM_rGPRAO_3[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R9, ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,ARM::R7 };
+ // FP is R7, R9 is not available.
+ static const unsigned ARM_rGPRAO_4[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R10,ARM::R11,
+ ARM::R7 };
+ // FP is R7, R9 is available as callee-saved register.
+ // This is used by non-Darwin platform in Thumb mode.
+ static const unsigned ARM_rGPRAO_5[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R12,ARM::LR,
+ ARM::R4, ARM::R5, ARM::R6,
+ ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
+
+ // For Thumb1 mode, we don't want to allocate hi regs at all, as we
+ // don't know how to spill them. If we make our prologue/epilogue code
+ // smarter at some point, we can go back to using the above allocation
+ // orders for the Thumb1 instructions that know how to use hi regs.
+ static const unsigned THUMB_rGPRAO[] = {
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+ ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
+
+ rGPRClass::iterator
+ rGPRClass::allocation_order_begin(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ if (Subtarget.isThumb1Only())
+ return THUMB_rGPRAO;
+ if (Subtarget.isTargetDarwin()) {
+ if (Subtarget.isR9Reserved())
+ return ARM_rGPRAO_4;
+ else
+ return ARM_rGPRAO_3;
+ } else {
+ if (Subtarget.isR9Reserved())
+ return ARM_rGPRAO_2;
+ else if (Subtarget.isThumb())
+ return ARM_rGPRAO_5;
+ else
+ return ARM_rGPRAO_1;
+ }
+ }
+
+ rGPRClass::iterator
+ rGPRClass::allocation_order_end(const MachineFunction &MF) const {
+ const TargetMachine &TM = MF.getTarget();
+ const TargetRegisterInfo *RI = TM.getRegisterInfo();
+ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+ GPRClass::iterator I;
+
+ if (Subtarget.isThumb1Only()) {
+ I = THUMB_rGPRAO + (sizeof(THUMB_rGPRAO)/sizeof(unsigned));
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+
+ if (Subtarget.isTargetDarwin()) {
+ if (Subtarget.isR9Reserved())
+ I = ARM_rGPRAO_4 + (sizeof(ARM_rGPRAO_4)/sizeof(unsigned));
+ else
+ I = ARM_rGPRAO_3 + (sizeof(ARM_rGPRAO_3)/sizeof(unsigned));
+ } else {
+ if (Subtarget.isR9Reserved())
+ I = ARM_rGPRAO_2 + (sizeof(ARM_rGPRAO_2)/sizeof(unsigned));
+ else if (Subtarget.isThumb())
+ I = ARM_rGPRAO_5 + (sizeof(ARM_rGPRAO_5)/sizeof(unsigned));
+ else
+ I = ARM_rGPRAO_1 + (sizeof(ARM_rGPRAO_1)/sizeof(unsigned));
+ }
+
+ // Mac OS X requires FP not to be clobbered for backtracing purpose.
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+ }
+ }];
+}
+
// Thumb registers are R0-R7 normally. Some instructions can still use
// the general GPR register class above (MOV, e.g.)
def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.cpp Sat Jul 31 19:59:02 2010
@@ -85,9 +85,15 @@
TSInfo(*this) {
}
+// Pass Pipeline Configuration
+bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ if (OptLevel != CodeGenOpt::None)
+ PM.add(createARMGlobalMergePass(getTargetLowering()));
+ return false;
+}
-// Pass Pipeline Configuration
bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
PM.add(createARMISelDag(*this, OptLevel));
Modified: llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/ARMTargetMachine.h Sat Jul 31 19:59:02 2010
@@ -50,6 +50,7 @@
}
// Pass Pipeline Configuration
+ virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
Modified: llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -37,6 +37,7 @@
class ARMAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
+ TargetMachine &TM;
private:
MCAsmParser &getParser() const { return Parser; }
@@ -94,8 +95,8 @@
public:
- ARMAsmParser(const Target &T, MCAsmParser &_Parser)
- : TargetAsmParser(T), Parser(_Parser) {}
+ ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
+ : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
Removed: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (removed)
@@ -1,1438 +0,0 @@
-//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format ARM assembly language.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "asm-printer"
-#include "ARM.h"
-#include "ARMBuildAttrs.h"
-#include "ARMAddressingModes.h"
-#include "ARMConstantPoolValue.h"
-#include "ARMInstPrinter.h"
-#include "ARMMachineFunctionInfo.h"
-#include "ARMMCInstLower.h"
-#include "ARMTargetMachine.h"
-#include "llvm/Analysis/DebugInfo.h"
-#include "llvm/Constants.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineModuleInfoImpls.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegistry.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include <cctype>
-using namespace llvm;
-
-static cl::opt<bool>
-EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
- cl::desc("enable experimental asmprinter gunk in the arm backend"));
-
-namespace {
- class ARMAsmPrinter : public AsmPrinter {
-
- /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
- /// make the right decision when printing asm code for different targets.
- const ARMSubtarget *Subtarget;
-
- /// AFI - Keep a pointer to ARMFunctionInfo for the current
- /// MachineFunction.
- ARMFunctionInfo *AFI;
-
- /// MCP - Keep a pointer to constantpool entries of the current
- /// MachineFunction.
- const MachineConstantPool *MCP;
-
- public:
- explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
- : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
- Subtarget = &TM.getSubtarget<ARMSubtarget>();
- }
-
- virtual const char *getPassName() const {
- return "ARM Assembly Printer";
- }
-
- void printInstructionThroughMCStreamer(const MachineInstr *MI);
-
-
- void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
- const char *Modifier = 0);
- void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
- void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printSORegOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
- const char *Modifier = 0);
- void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
- const char *Modifier = 0);
- void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O,
- const char *Modifier = 0);
- void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum,
- raw_ostream &O);
-
- void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
- void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O,
- unsigned Scale);
- void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
-
- void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
- void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {}
- void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
-
- void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {}
- void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {}
- void printNegZeroOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {}
- void printPredicateOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printPCLabel(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printRegisterList(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printCPInstOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O,
- const char *Modifier);
- void printJTBlockOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printTBAddrMode(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printNoHashImmediate(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
- void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O);
-
- virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O);
- virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
- unsigned AsmVariant,
- const char *ExtraCode, raw_ostream &O);
-
- void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
- static const char *getRegisterName(unsigned RegNo);
-
- virtual void EmitInstruction(const MachineInstr *MI);
- bool runOnMachineFunction(MachineFunction &F);
-
- virtual void EmitConstantPool() {} // we emit constant pools customly!
- virtual void EmitFunctionEntryLabel();
- void EmitStartOfAsmFile(Module &M);
- void EmitEndOfAsmFile(Module &M);
-
- MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
- const MachineBasicBlock *MBB) const;
- MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
-
- /// EmitMachineConstantPoolValue - Print a machine constantpool value to
- /// the .s file.
- virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
- EmitMachineConstantPoolValue(MCPV, OS);
- OutStreamer.EmitRawText(OS.str());
- }
-
- void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
- raw_ostream &O) {
- switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
- case 1: O << MAI->getData8bitsDirective(0); break;
- case 2: O << MAI->getData16bitsDirective(0); break;
- case 4: O << MAI->getData32bitsDirective(0); break;
- default: assert(0 && "Unknown CPV size");
- }
-
- ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
-
- if (ACPV->isLSDA()) {
- O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
- } else if (ACPV->isBlockAddress()) {
- O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
- } else if (ACPV->isGlobalValue()) {
- const GlobalValue *GV = ACPV->getGV();
- bool isIndirect = Subtarget->isTargetDarwin() &&
- Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
- if (!isIndirect)
- O << *Mang->getSymbol(GV);
- else {
- // FIXME: Remove this when Darwin transition to @GOT like syntax.
- MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
- O << *Sym;
-
- MachineModuleInfoMachO &MMIMachO =
- MMI->getObjFileInfo<MachineModuleInfoMachO>();
- MachineModuleInfoImpl::StubValueTy &StubSym =
- GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
- MMIMachO.getGVStubEntry(Sym);
- if (StubSym.getPointer() == 0)
- StubSym = MachineModuleInfoImpl::
- StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
- }
- } else {
- assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
- O << *GetExternalSymbolSymbol(ACPV->getSymbol());
- }
-
- if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
- if (ACPV->getPCAdjustment() != 0) {
- O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
- << getFunctionNumber() << "_" << ACPV->getLabelId()
- << "+" << (unsigned)ACPV->getPCAdjustment();
- if (ACPV->mustAddCurrentAddress())
- O << "-.";
- O << ')';
- }
- }
- };
-} // end of anonymous namespace
-
-#include "ARMGenAsmWriter.inc"
-
-void ARMAsmPrinter::EmitFunctionEntryLabel() {
- if (AFI->isThumbFunction()) {
- OutStreamer.EmitRawText(StringRef("\t.code\t16"));
- if (!Subtarget->isTargetDarwin())
- OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
- else {
- // This needs to emit to a temporary string to get properly quoted
- // MCSymbols when they have spaces in them.
- SmallString<128> Tmp;
- raw_svector_ostream OS(Tmp);
- OS << "\t.thumb_func\t" << *CurrentFnSym;
- OutStreamer.EmitRawText(OS.str());
- }
- }
-
- OutStreamer.EmitLabel(CurrentFnSym);
-}
-
-/// runOnMachineFunction - This uses the printInstruction()
-/// method to print assembly for each instruction.
-///
-bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- AFI = MF.getInfo<ARMFunctionInfo>();
- MCP = MF.getConstantPool();
-
- return AsmPrinter::runOnMachineFunction(MF);
-}
-
-void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O, const char *Modifier) {
- const MachineOperand &MO = MI->getOperand(OpNum);
- unsigned TF = MO.getTargetFlags();
-
- switch (MO.getType()) {
- default:
- assert(0 && "<unknown operand type>");
- case MachineOperand::MO_Register: {
- unsigned Reg = MO.getReg();
- assert(TargetRegisterInfo::isPhysicalRegister(Reg));
- if (Modifier && strcmp(Modifier, "dregpair") == 0) {
- unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
- unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
- O << '{'
- << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
- << '}';
- } else if (Modifier && strcmp(Modifier, "lane") == 0) {
- unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
- unsigned DReg =
- TM.getRegisterInfo()->getMatchingSuperReg(Reg,
- RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
- O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
- } else {
- assert(!MO.getSubReg() && "Subregs should be eliminated!");
- O << getRegisterName(Reg);
- }
- break;
- }
- case MachineOperand::MO_Immediate: {
- int64_t Imm = MO.getImm();
- O << '#';
- if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
- (TF & ARMII::MO_LO16))
- O << ":lower16:";
- else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
- (TF & ARMII::MO_HI16))
- O << ":upper16:";
- O << Imm;
- break;
- }
- case MachineOperand::MO_MachineBasicBlock:
- O << *MO.getMBB()->getSymbol();
- return;
- case MachineOperand::MO_GlobalAddress: {
- bool isCallOp = Modifier && !strcmp(Modifier, "call");
- const GlobalValue *GV = MO.getGlobal();
-
- if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
- (TF & ARMII::MO_LO16))
- O << ":lower16:";
- else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
- (TF & ARMII::MO_HI16))
- O << ":upper16:";
- O << *Mang->getSymbol(GV);
-
- printOffset(MO.getOffset(), O);
-
- if (isCallOp && Subtarget->isTargetELF() &&
- TM.getRelocationModel() == Reloc::PIC_)
- O << "(PLT)";
- break;
- }
- case MachineOperand::MO_ExternalSymbol: {
- bool isCallOp = Modifier && !strcmp(Modifier, "call");
- O << *GetExternalSymbolSymbol(MO.getSymbolName());
-
- if (isCallOp && Subtarget->isTargetELF() &&
- TM.getRelocationModel() == Reloc::PIC_)
- O << "(PLT)";
- break;
- }
- case MachineOperand::MO_ConstantPoolIndex:
- O << *GetCPISymbol(MO.getIndex());
- break;
- case MachineOperand::MO_JumpTableIndex:
- O << *GetJTISymbol(MO.getIndex());
- break;
- }
-}
-
-static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
- const MCAsmInfo *MAI) {
- // Break it up into two parts that make up a shifter immediate.
- V = ARM_AM::getSOImmVal(V);
- assert(V != -1 && "Not a valid so_imm value!");
-
- unsigned Imm = ARM_AM::getSOImmValImm(V);
- unsigned Rot = ARM_AM::getSOImmValRot(V);
-
- // Print low-level immediate formation info, per
- // A5.1.3: "Data-processing operands - Immediate".
- if (Rot) {
- O << "#" << Imm << ", " << Rot;
- // Pretty printed version.
- if (VerboseAsm) {
- O << "\t" << MAI->getCommentString() << ' ';
- O << (int)ARM_AM::rotr32(Imm, Rot);
- }
- } else {
- O << "#" << Imm;
- }
-}
-
-/// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
-/// immediate in bits 0-7.
-void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO = MI->getOperand(OpNum);
- assert(MO.isImm() && "Not a valid so_imm value!");
- printSOImm(O, MO.getImm(), isVerbose(), MAI);
-}
-
-/// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
-/// followed by an 'orr' to materialize.
-void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO = MI->getOperand(OpNum);
- assert(MO.isImm() && "Not a valid so_imm value!");
- unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
- unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
- printSOImm(O, V1, isVerbose(), MAI);
- O << "\n\torr";
- printPredicateOperand(MI, 2, O);
- O << "\t";
- printOperand(MI, 0, O);
- O << ", ";
- printOperand(MI, 0, O);
- O << ", ";
- printSOImm(O, V2, isVerbose(), MAI);
-}
-
-// so_reg is a 4-operand unit corresponding to register forms of the A5.1
-// "Addressing Mode 1 - Data-processing operands" forms. This includes:
-// REG 0 0 - e.g. R5
-// REG REG 0,SH_OPC - e.g. R5, ROR R3
-// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
-void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- const MachineOperand &MO3 = MI->getOperand(Op+2);
-
- O << getRegisterName(MO1.getReg());
-
- // Print the shift opc.
- O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
- << " ";
-
- if (MO2.getReg()) {
- O << getRegisterName(MO2.getReg());
- assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
- } else {
- O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
- }
-}
-
-void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- const MachineOperand &MO3 = MI->getOperand(Op+2);
-
- if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
- printOperand(MI, Op, O);
- return;
- }
-
- O << "[" << getRegisterName(MO1.getReg());
-
- if (!MO2.getReg()) {
- if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
- O << ", #"
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
- << ARM_AM::getAM2Offset(MO3.getImm());
- O << "]";
- return;
- }
-
- O << ", "
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
- << getRegisterName(MO2.getReg());
-
- if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
- O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
- << " #" << ShImm;
- O << "]";
-}
-
-void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
-
- if (!MO1.getReg()) {
- unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
- O << "#"
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
- << ImmOffs;
- return;
- }
-
- O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
- << getRegisterName(MO1.getReg());
-
- if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
- O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
- << " #" << ShImm;
-}
-
-void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- const MachineOperand &MO3 = MI->getOperand(Op+2);
-
- assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[" << getRegisterName(MO1.getReg());
-
- if (MO2.getReg()) {
- O << ", "
- << (char)ARM_AM::getAM3Op(MO3.getImm())
- << getRegisterName(MO2.getReg())
- << "]";
- return;
- }
-
- if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
- O << ", #"
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
- << ImmOffs;
- O << "]";
-}
-
-void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
- raw_ostream &O){
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
-
- if (MO1.getReg()) {
- O << (char)ARM_AM::getAM3Op(MO2.getImm())
- << getRegisterName(MO1.getReg());
- return;
- }
-
- unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
- O << "#"
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
- << ImmOffs;
-}
-
-void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
- raw_ostream &O,
- const char *Modifier) {
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
- if (Modifier && strcmp(Modifier, "submode") == 0) {
- O << ARM_AM::getAMSubModeStr(Mode);
- } else if (Modifier && strcmp(Modifier, "wide") == 0) {
- ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
- if (Mode == ARM_AM::ia)
- O << ".w";
- } else {
- printOperand(MI, Op, O);
- }
-}
-
-void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
- raw_ostream &O,
- const char *Modifier) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
-
- if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
- printOperand(MI, Op, O);
- return;
- }
-
- assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
-
- if (Modifier && strcmp(Modifier, "submode") == 0) {
- ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
- O << ARM_AM::getAMSubModeStr(Mode);
- return;
- } else if (Modifier && strcmp(Modifier, "base") == 0) {
- // Used for FSTM{D|S} and LSTM{D|S} operations.
- O << getRegisterName(MO1.getReg());
- return;
- }
-
- O << "[" << getRegisterName(MO1.getReg());
-
- if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
- O << ", #"
- << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
- << ImmOffs*4;
- }
- O << "]";
-}
-
-void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
-
- O << "[" << getRegisterName(MO1.getReg());
- if (MO2.getImm()) {
- // FIXME: Both darwin as and GNU as violate ARM docs here.
- O << ", :" << (MO2.getImm() << 3);
- }
- O << "]";
-}
-
-void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
- raw_ostream &O){
- const MachineOperand &MO = MI->getOperand(Op);
- if (MO.getReg() == 0)
- O << "!";
- else
- O << ", " << getRegisterName(MO.getReg());
-}
-
-void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
- raw_ostream &O,
- const char *Modifier) {
- if (Modifier && strcmp(Modifier, "label") == 0) {
- printPCLabel(MI, Op+1, O);
- return;
- }
-
- const MachineOperand &MO1 = MI->getOperand(Op);
- assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
-}
-
-void
-ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO = MI->getOperand(Op);
- uint32_t v = ~MO.getImm();
- int32_t lsb = CountTrailingZeros_32(v);
- int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
- assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
- O << "#" << lsb << ", #" << width;
-}
-
-//===--------------------------------------------------------------------===//
-
-void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- O << "#" << MI->getOperand(Op).getImm() * 4;
-}
-
-void
-ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- // (3 - the number of trailing zeros) is the number of then / else.
- unsigned Mask = MI->getOperand(Op).getImm();
- unsigned CondBit0 = Mask >> 4 & 1;
- unsigned NumTZ = CountTrailingZeros_32(Mask);
- assert(NumTZ <= 3 && "Invalid IT mask!");
- for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
- bool T = ((Mask >> Pos) & 1) == CondBit0;
- if (T)
- O << 't';
- else
- O << 'e';
- }
-}
-
-void
-ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << getRegisterName(MO1.getReg());
- O << ", " << getRegisterName(MO2.getReg()) << "]";
-}
-
-void
-ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
- raw_ostream &O,
- unsigned Scale) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- const MachineOperand &MO3 = MI->getOperand(Op+2);
-
- if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
- printOperand(MI, Op, O);
- return;
- }
-
- O << "[" << getRegisterName(MO1.getReg());
- if (MO3.getReg())
- O << ", " << getRegisterName(MO3.getReg());
- else if (unsigned ImmOffs = MO2.getImm())
- O << ", #" << ImmOffs * Scale;
- O << "]";
-}
-
-void
-ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- printThumbAddrModeRI5Operand(MI, Op, O, 1);
-}
-void
-ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- printThumbAddrModeRI5Operand(MI, Op, O, 2);
-}
-void
-ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
- raw_ostream &O) {
- printThumbAddrModeRI5Operand(MI, Op, O, 4);
-}
-
-void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(Op);
- const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << getRegisterName(MO1.getReg());
- if (unsigned ImmOffs = MO2.getImm())
- O << ", #" << ImmOffs*4;
- O << "]";
-}
-
-//===--------------------------------------------------------------------===//
-
-// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
-// register with shift forms.
-// REG 0 0 - e.g. R5
-// REG IMM, SH_OPC - e.g. R5, LSL #3
-void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1);
-
- unsigned Reg = MO1.getReg();
- assert(TargetRegisterInfo::isPhysicalRegister(Reg));
- O << getRegisterName(Reg);
-
- // Print the shift opc.
- O << ", "
- << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
- << " ";
-
- assert(MO2.isImm() && "Not a valid t2_so_reg value!");
- O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
-}
-
-void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1);
-
- O << "[" << getRegisterName(MO1.getReg());
-
- unsigned OffImm = MO2.getImm();
- if (OffImm) // Don't print +0.
- O << ", #" << OffImm;
- O << "]";
-}
-
-void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1);
-
- O << "[" << getRegisterName(MO1.getReg());
-
- int32_t OffImm = (int32_t)MO2.getImm();
- // Don't print +0.
- if (OffImm < 0)
- O << ", #-" << -OffImm;
- else if (OffImm > 0)
- O << ", #" << OffImm;
- O << "]";
-}
-
-void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1);
-
- O << "[" << getRegisterName(MO1.getReg());
-
- int32_t OffImm = (int32_t)MO2.getImm() / 4;
- // Don't print +0.
- if (OffImm < 0)
- O << ", #-" << -OffImm * 4;
- else if (OffImm > 0)
- O << ", #" << OffImm * 4;
- O << "]";
-}
-
-void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- int32_t OffImm = (int32_t)MO1.getImm();
- // Don't print +0.
- if (OffImm < 0)
- O << "#-" << -OffImm;
- else if (OffImm > 0)
- O << "#" << OffImm;
-}
-
-void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- const MachineOperand &MO3 = MI->getOperand(OpNum+2);
-
- O << "[" << getRegisterName(MO1.getReg());
-
- assert(MO2.getReg() && "Invalid so_reg load / store address!");
- O << ", " << getRegisterName(MO2.getReg());
-
- unsigned ShAmt = MO3.getImm();
- if (ShAmt) {
- assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
- O << ", lsl #" << ShAmt;
- }
- O << "]";
-}
-
-
-//===--------------------------------------------------------------------===//
-
-void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
- if (CC != ARMCC::AL)
- O << ARMCondCodeToString(CC);
-}
-
-void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
- int OpNum,
- raw_ostream &O) {
- ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
- O << ARMCondCodeToString(CC);
-}
-
-void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O){
- unsigned Reg = MI->getOperand(OpNum).getReg();
- if (Reg) {
- assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
- O << 's';
- }
-}
-
-void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- int Id = (int)MI->getOperand(OpNum).getImm();
- O << MAI->getPrivateGlobalPrefix()
- << "PC" << getFunctionNumber() << "_" << Id;
-}
-
-void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- O << "{";
- for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
- if (MI->getOperand(i).isImplicit())
- continue;
- if ((int)i != OpNum) O << ", ";
- printOperand(MI, i, O);
- }
- O << "}";
-}
-
-void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O, const char *Modifier) {
- assert(Modifier && "This operand only works with a modifier!");
- // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
- // data itself.
- if (!strcmp(Modifier, "label")) {
- unsigned ID = MI->getOperand(OpNum).getImm();
- OutStreamer.EmitLabel(GetCPISymbol(ID));
- } else {
- assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
- unsigned CPI = MI->getOperand(OpNum).getIndex();
-
- const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
-
- if (MCPE.isMachineConstantPoolEntry()) {
- EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
- } else {
- EmitGlobalConstant(MCPE.Val.ConstVal);
- }
- }
-}
-
-MCSymbol *ARMAsmPrinter::
-GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
- const MachineBasicBlock *MBB) const {
- SmallString<60> Name;
- raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
- << getFunctionNumber() << '_' << uid << '_' << uid2
- << "_set_" << MBB->getNumber();
- return OutContext.GetOrCreateSymbol(Name.str());
-}
-
-MCSymbol *ARMAsmPrinter::
-GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
- SmallString<60> Name;
- raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
- << getFunctionNumber() << '_' << uid << '_' << uid2;
- return OutContext.GetOrCreateSymbol(Name.str());
-}
-
-void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
-
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
-
- unsigned JTI = MO1.getIndex();
- MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
- // Can't use EmitLabel until instprinter happens, label comes out in the wrong
- // order.
- O << *JTISymbol << ":\n";
-
- const char *JTEntryDirective = MAI->getData32bitsDirective();
-
- const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
- const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
- const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
- bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
- SmallPtrSet<MachineBasicBlock*, 8> JTSets;
- for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
- MachineBasicBlock *MBB = JTBBs[i];
- bool isNew = JTSets.insert(MBB);
-
- if (UseSet && isNew) {
- O << "\t.set\t"
- << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
- << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
- }
-
- O << JTEntryDirective << ' ';
- if (UseSet)
- O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
- else if (TM.getRelocationModel() == Reloc::PIC_)
- O << *MBB->getSymbol() << '-' << *JTISymbol;
- else
- O << *MBB->getSymbol();
-
- if (i != e-1)
- O << '\n';
- }
-}
-
-void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const MachineOperand &MO1 = MI->getOperand(OpNum);
- const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
- unsigned JTI = MO1.getIndex();
-
- MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
-
- // Can't use EmitLabel until instprinter happens, label comes out in the wrong
- // order.
- O << *JTISymbol << ":\n";
-
- const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
- const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
- const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
- bool ByteOffset = false, HalfWordOffset = false;
- if (MI->getOpcode() == ARM::t2TBB)
- ByteOffset = true;
- else if (MI->getOpcode() == ARM::t2TBH)
- HalfWordOffset = true;
-
- for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
- MachineBasicBlock *MBB = JTBBs[i];
- if (ByteOffset)
- O << MAI->getData8bitsDirective();
- else if (HalfWordOffset)
- O << MAI->getData16bitsDirective();
-
- if (ByteOffset || HalfWordOffset)
- O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
- else
- O << "\tb.w " << *MBB->getSymbol();
-
- if (i != e-1)
- O << '\n';
- }
-}
-
-void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
- if (MI->getOpcode() == ARM::t2TBH)
- O << ", lsl #1";
- O << ']';
-}
-
-void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- O << MI->getOperand(OpNum).getImm();
-}
-
-void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
- O << '#' << FP->getValueAPF().convertToFloat();
- if (isVerbose()) {
- O << "\t\t" << MAI->getCommentString() << ' ';
- WriteAsOperand(O, FP, /*PrintType=*/false);
- }
-}
-
-void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
- O << '#' << FP->getValueAPF().convertToDouble();
- if (isVerbose()) {
- O << "\t\t" << MAI->getCommentString() << ' ';
- WriteAsOperand(O, FP, /*PrintType=*/false);
- }
-}
-
-void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
- raw_ostream &O) {
- unsigned EncodedImm = MI->getOperand(OpNum).getImm();
- unsigned EltBits;
- uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
- O << "#0x" << utohexstr(Val);
-}
-
-bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O) {
- // Does this asm operand have a single letter operand modifier?
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'a': // Print as a memory address.
- if (MI->getOperand(OpNum).isReg()) {
- O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
- return false;
- }
- // Fallthrough
- case 'c': // Don't print "#" before an immediate operand.
- if (!MI->getOperand(OpNum).isImm())
- return true;
- printNoHashImmediate(MI, OpNum, O);
- return false;
- case 'P': // Print a VFP double precision register.
- case 'q': // Print a NEON quad precision register.
- printOperand(MI, OpNum, O);
- return false;
- case 'Q':
- case 'R':
- case 'H':
- report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
- return true;
- }
- }
-
- printOperand(MI, OpNum, O);
- return false;
-}
-
-bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNum, unsigned AsmVariant,
- const char *ExtraCode,
- raw_ostream &O) {
- if (ExtraCode && ExtraCode[0])
- return true; // Unknown modifier.
-
- const MachineOperand &MO = MI->getOperand(OpNum);
- assert(MO.isReg() && "unexpected inline asm memory operand");
- O << "[" << getRegisterName(MO.getReg()) << "]";
- return false;
-}
-
-void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
- if (EnableMCInst) {
- printInstructionThroughMCStreamer(MI);
- return;
- }
-
- if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
- EmitAlignment(2);
-
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
- if (MI->getOpcode() == ARM::DBG_VALUE) {
- unsigned NOps = MI->getNumOperands();
- assert(NOps==4);
- OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
- // cast away const; DIetc do not take const operands for some reason.
- DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
- OS << V.getName();
- OS << " <- ";
- // Frame address. Currently handles register +- offset only.
- assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
- OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
- OS << ']';
- OS << "+";
- printOperand(MI, NOps-2, OS);
- OutStreamer.EmitRawText(OS.str());
- return;
- }
-
- printInstruction(MI, OS);
- OutStreamer.EmitRawText(OS.str());
-
- // Make sure the instruction that follows TBB is 2-byte aligned.
- // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
- if (MI->getOpcode() == ARM::t2TBB)
- EmitAlignment(1);
-}
-
-void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
- if (Subtarget->isTargetDarwin()) {
- Reloc::Model RelocM = TM.getRelocationModel();
- if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
- // Declare all the text sections up front (before the DWARF sections
- // emitted by AsmPrinter::doInitialization) so the assembler will keep
- // them together at the beginning of the object file. This helps
- // avoid out-of-range branches that are due a fundamental limitation of
- // the way symbol offsets are encoded with the current Darwin ARM
- // relocations.
- const TargetLoweringObjectFileMachO &TLOFMacho =
- static_cast<const TargetLoweringObjectFileMachO &>(
- getObjFileLowering());
- OutStreamer.SwitchSection(TLOFMacho.getTextSection());
- OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
- OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
- if (RelocM == Reloc::DynamicNoPIC) {
- const MCSection *sect =
- OutContext.getMachOSection("__TEXT", "__symbol_stub4",
- MCSectionMachO::S_SYMBOL_STUBS,
- 12, SectionKind::getText());
- OutStreamer.SwitchSection(sect);
- } else {
- const MCSection *sect =
- OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
- MCSectionMachO::S_SYMBOL_STUBS,
- 16, SectionKind::getText());
- OutStreamer.SwitchSection(sect);
- }
- }
- }
-
- // Use unified assembler syntax.
- OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
-
- // Emit ARM Build Attributes
- if (Subtarget->isTargetELF()) {
- // CPU Type
- std::string CPUString = Subtarget->getCPUString();
- if (CPUString != "generic")
- OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
-
- // FIXME: Emit FPU type
- if (Subtarget->hasVFP2())
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::VFP_arch) + ", 2");
-
- // Signal various FP modes.
- if (!UnsafeFPMath) {
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
- }
-
- if (FiniteOnlyFPMath())
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
- else
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
-
- // 8-bytes alignment stuff.
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
-
- // Hard float. Use both S and D registers and conform to AAPCS-VFP.
- if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
- OutStreamer.EmitRawText("\t.eabi_attribute " +
- Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
- }
- // FIXME: Should we signal R9 usage?
- }
-}
-
-
-void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
- if (Subtarget->isTargetDarwin()) {
- // All darwin targets use mach-o.
- const TargetLoweringObjectFileMachO &TLOFMacho =
- static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
- MachineModuleInfoMachO &MMIMacho =
- MMI->getObjFileInfo<MachineModuleInfoMachO>();
-
- // Output non-lazy-pointers for external and common global variables.
- MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
-
- if (!Stubs.empty()) {
- // Switch with ".non_lazy_symbol_pointer" directive.
- OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
- EmitAlignment(2);
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- // L_foo$stub:
- OutStreamer.EmitLabel(Stubs[i].first);
- // .indirect_symbol _foo
- MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
- OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
-
- if (MCSym.getInt())
- // External to current translation unit.
- OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
- else
- // Internal to current translation unit.
- //
- // When we place the LSDA into the TEXT section, the type info pointers
- // need to be indirect and pc-rel. We accomplish this by using NLPs.
- // However, sometimes the types are local to the file. So we need to
- // fill in the value for the NLP in those cases.
- OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
- OutContext),
- 4/*size*/, 0/*addrspace*/);
- }
-
- Stubs.clear();
- OutStreamer.AddBlankLine();
- }
-
- Stubs = MMIMacho.GetHiddenGVStubList();
- if (!Stubs.empty()) {
- OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
- EmitAlignment(2);
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- // L_foo$stub:
- OutStreamer.EmitLabel(Stubs[i].first);
- // .long _foo
- OutStreamer.EmitValue(MCSymbolRefExpr::
- Create(Stubs[i].second.getPointer(),
- OutContext),
- 4/*size*/, 0/*addrspace*/);
- }
-
- Stubs.clear();
- OutStreamer.AddBlankLine();
- }
-
- // Funny Darwin hack: This flag tells the linker that no global symbols
- // contain code that falls through to other global symbols (e.g. the obvious
- // implementation of multiple entry points). If this doesn't occur, the
- // linker can safely perform dead code stripping. Since LLVM never
- // generates code that does this, it is always safe to set.
- OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
- }
-}
-
-//===----------------------------------------------------------------------===//
-
-void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
- ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
- switch (MI->getOpcode()) {
- case ARM::t2MOVi32imm:
- assert(0 && "Should be lowered by thumb2it pass");
- default: break;
- case ARM::PICADD: { // FIXME: Remove asm string from td file.
- // This is a pseudo op for a label + instruction sequence, which looks like:
- // LPC0:
- // add r0, pc, r0
- // This adds the address of LPC0 to r0.
-
- // Emit the label.
- // FIXME: MOVE TO SHARED PLACE.
- unsigned Id = (unsigned)MI->getOperand(2).getImm();
- const char *Prefix = MAI->getPrivateGlobalPrefix();
- MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
- + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
- OutStreamer.EmitLabel(Label);
-
-
- // Form and emit tha dd.
- MCInst AddInst;
- AddInst.setOpcode(ARM::ADDrr);
- AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
- AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
- OutStreamer.EmitInstruction(AddInst);
- return;
- }
- case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
- /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
- /// in the function. The first operand is the ID# for this instruction, the
- /// second is the index into the MachineConstantPool that this is, the third
- /// is the size in bytes of this constant pool entry.
- unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
- unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
-
- EmitAlignment(2);
- OutStreamer.EmitLabel(GetCPISymbol(LabelId));
-
- const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
- if (MCPE.isMachineConstantPoolEntry())
- EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
- else
- EmitGlobalConstant(MCPE.Val.ConstVal);
-
- return;
- }
- case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
- // This is a hack that lowers as a two instruction sequence.
- unsigned DstReg = MI->getOperand(0).getReg();
- unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
-
- unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
- unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
-
- {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::MOVi);
- TmpInst.addOperand(MCOperand::CreateReg(DstReg));
- TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
-
- // Predicate.
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
-
- TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
- OutStreamer.EmitInstruction(TmpInst);
- }
-
- {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::ORRri);
- TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
- TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
- TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
- // Predicate.
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
-
- TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
- OutStreamer.EmitInstruction(TmpInst);
- }
- return;
- }
- case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
- // This is a hack that lowers as a two instruction sequence.
- unsigned DstReg = MI->getOperand(0).getReg();
- const MachineOperand &MO = MI->getOperand(1);
- MCOperand V1, V2;
- if (MO.isImm()) {
- unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
- V1 = MCOperand::CreateImm(ImmVal & 65535);
- V2 = MCOperand::CreateImm(ImmVal >> 16);
- } else if (MO.isGlobal()) {
- MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
- const MCSymbolRefExpr *SymRef1 =
- MCSymbolRefExpr::Create(Symbol,
- MCSymbolRefExpr::VK_ARM_LO16, OutContext);
- const MCSymbolRefExpr *SymRef2 =
- MCSymbolRefExpr::Create(Symbol,
- MCSymbolRefExpr::VK_ARM_HI16, OutContext);
- V1 = MCOperand::CreateExpr(SymRef1);
- V2 = MCOperand::CreateExpr(SymRef2);
- } else {
- MI->dump();
- llvm_unreachable("cannot handle this operand");
- }
-
- {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::MOVi16);
- TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
- TmpInst.addOperand(V1); // lower16(imm)
-
- // Predicate.
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
-
- OutStreamer.EmitInstruction(TmpInst);
- }
-
- {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::MOVTi16);
- TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
- TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
- TmpInst.addOperand(V2); // upper16(imm)
-
- // Predicate.
- TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
-
- OutStreamer.EmitInstruction(TmpInst);
- }
-
- return;
- }
- }
-
- MCInst TmpInst;
- MCInstLowering.Lower(MI, TmpInst);
- OutStreamer.EmitInstruction(TmpInst);
-}
-
-//===----------------------------------------------------------------------===//
-// Target Registry Stuff
-//===----------------------------------------------------------------------===//
-
-static MCInstPrinter *createARMMCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new ARMInstPrinter(MAI, false);
- return 0;
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeARMAsmPrinter() {
- RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
- RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
-
- TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
-}
-
Removed: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp (removed)
@@ -1,162 +0,0 @@
-//===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains code to lower ARM MachineInstrs to their corresponding
-// MCInst records.
-//
-//===----------------------------------------------------------------------===//
-
-#include "ARMMCInstLower.h"
-//#include "llvm/CodeGen/MachineModuleInfoImpls.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-//#include "llvm/MC/MCStreamer.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/SmallString.h"
-using namespace llvm;
-
-
-#if 0
-const ARMSubtarget &ARMMCInstLower::getSubtarget() const {
- return AsmPrinter.getSubtarget();
-}
-
-MachineModuleInfoMachO &ARMMCInstLower::getMachOMMI() const {
- assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
- return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
-}
-#endif
-
-MCSymbol *ARMMCInstLower::
-GetGlobalAddressSymbol(const MachineOperand &MO) const {
- // FIXME: HANDLE PLT references how??
- switch (MO.getTargetFlags()) {
- default: assert(0 && "Unknown target flag on GV operand");
- case 0: break;
- }
-
- return Printer.Mang->getSymbol(MO.getGlobal());
-}
-
-MCSymbol *ARMMCInstLower::
-GetExternalSymbolSymbol(const MachineOperand &MO) const {
- // FIXME: HANDLE PLT references how??
- switch (MO.getTargetFlags()) {
- default: assert(0 && "Unknown target flag on GV operand");
- case 0: break;
- }
-
- return Printer.GetExternalSymbolSymbol(MO.getSymbolName());
-}
-
-
-
-MCSymbol *ARMMCInstLower::
-GetJumpTableSymbol(const MachineOperand &MO) const {
- SmallString<256> Name;
- raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "JTI"
- << Printer.getFunctionNumber() << '_' << MO.getIndex();
-
-#if 0
- switch (MO.getTargetFlags()) {
- default: llvm_unreachable("Unknown target flag on GV operand");
- }
-#endif
-
- // Create a symbol for the name.
- return Ctx.GetOrCreateSymbol(Name.str());
-}
-
-MCSymbol *ARMMCInstLower::
-GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
- SmallString<256> Name;
- raw_svector_ostream(Name) << Printer.MAI->getPrivateGlobalPrefix() << "CPI"
- << Printer.getFunctionNumber() << '_' << MO.getIndex();
-
-#if 0
- switch (MO.getTargetFlags()) {
- default: llvm_unreachable("Unknown target flag on GV operand");
- }
-#endif
-
- // Create a symbol for the name.
- return Ctx.GetOrCreateSymbol(Name.str());
-}
-
-MCOperand ARMMCInstLower::
-LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const {
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, Ctx);
-
-#if 0
- switch (MO.getTargetFlags()) {
- default: llvm_unreachable("Unknown target flag on GV operand");
- }
-#endif
-
- if (!MO.isJTI() && MO.getOffset())
- Expr = MCBinaryExpr::CreateAdd(Expr,
- MCConstantExpr::Create(MO.getOffset(), Ctx),
- Ctx);
- return MCOperand::CreateExpr(Expr);
-}
-
-
-void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
- OutMI.setOpcode(MI->getOpcode());
-
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
-
- MCOperand MCOp;
- switch (MO.getType()) {
- default:
- MI->dump();
- assert(0 && "unknown operand type");
- case MachineOperand::MO_Register:
- // Ignore all implicit register operands.
- if (MO.isImplicit()) continue;
- assert(!MO.getSubReg() && "Subregs should be eliminated!");
- MCOp = MCOperand::CreateReg(MO.getReg());
- break;
- case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
- break;
- case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
- MO.getMBB()->getSymbol(), Ctx));
- break;
- case MachineOperand::MO_GlobalAddress:
- MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
- break;
- case MachineOperand::MO_ExternalSymbol:
- MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
- break;
- case MachineOperand::MO_JumpTableIndex:
- MCOp = LowerSymbolOperand(MO, GetJumpTableSymbol(MO));
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO));
- break;
- case MachineOperand::MO_BlockAddress:
- MCOp = LowerSymbolOperand(MO, Printer.GetBlockAddressSymbol(
- MO.getBlockAddress()));
- break;
- }
-
- OutMI.addOperand(MCOp);
- }
-
-}
Removed: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/ARMMCInstLower.h (removed)
@@ -1,56 +0,0 @@
-//===-- ARMMCInstLower.h - Lower MachineInstr to MCInst -------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ARM_MCINSTLOWER_H
-#define ARM_MCINSTLOWER_H
-
-#include "llvm/Support/Compiler.h"
-
-namespace llvm {
- class AsmPrinter;
- class MCAsmInfo;
- class MCContext;
- class MCInst;
- class MCOperand;
- class MCSymbol;
- class MachineInstr;
- class MachineModuleInfoMachO;
- class MachineOperand;
- class Mangler;
- //class ARMSubtarget;
-
-/// ARMMCInstLower - This class is used to lower an MachineInstr into an MCInst.
-class LLVM_LIBRARY_VISIBILITY ARMMCInstLower {
- MCContext &Ctx;
- Mangler &Mang;
- AsmPrinter &Printer;
-
- //const ARMSubtarget &getSubtarget() const;
-public:
- ARMMCInstLower(MCContext &ctx, Mangler &mang, AsmPrinter &printer)
- : Ctx(ctx), Mang(mang), Printer(printer) {}
-
- void Lower(const MachineInstr *MI, MCInst &OutMI) const;
-
- //MCSymbol *GetPICBaseSymbol() const;
- MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
- MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
- MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const;
- MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
- MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
-
-/*
-private:
- MachineModuleInfoMachO &getMachOMMI() const;
- */
-};
-
-}
-
-#endif
Modified: llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/AsmPrinter/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -1,8 +1,6 @@
include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
add_llvm_library(LLVMARMAsmPrinter
- ARMAsmPrinter.cpp
ARMInstPrinter.cpp
- ARMMCInstLower.cpp
)
add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen)
Modified: llvm/branches/wendling/eh/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -11,21 +11,27 @@
tablegen(ARMGenCallingConv.inc -gen-callingconv)
tablegen(ARMGenSubtarget.inc -gen-subtarget)
tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
+tablegen(ARMGenFastISel.inc -gen-fast-isel)
add_llvm_target(ARMCodeGen
+ ARMAsmPrinter.cpp
ARMBaseInstrInfo.cpp
ARMBaseRegisterInfo.cpp
ARMCodeEmitter.cpp
ARMConstantIslandPass.cpp
ARMConstantPoolValue.cpp
ARMExpandPseudoInsts.cpp
+ ARMFastISel.cpp
+ ARMGlobalMerge.cpp
ARMISelDAGToDAG.cpp
ARMISelLowering.cpp
ARMInstrInfo.cpp
ARMJITInfo.cpp
ARMLoadStoreOptimizer.cpp
ARMMCAsmInfo.cpp
+ ARMMCInstLower.cpp
ARMRegisterInfo.cpp
+ ARMSelectionDAGInfo.cpp
ARMSubtarget.cpp
ARMTargetMachine.cpp
ARMTargetObjectFile.cpp
@@ -38,7 +44,6 @@
Thumb2InstrInfo.cpp
Thumb2RegisterInfo.cpp
Thumb2SizeReduction.cpp
- ARMSelectionDAGInfo.cpp
)
-target_link_libraries (LLVMARMCodeGen LLVMSelectionDAG)
+target_link_libraries (LLVMARMCodeGen LLVMARMAsmPrinter LLVMSelectionDAG)
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Sat Jul 31 19:59:02 2010
@@ -93,6 +93,9 @@
RegClassID = ARM::DPRRegClassID;
}
+ // For this purpose, we can treat rGPR as if it were GPR.
+ if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
+
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
unsigned RegNum =
RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
@@ -887,7 +890,6 @@
return true;
}
- assert(0 && "Unexpected BrMiscFrm Opcode");
return false;
}
@@ -989,10 +991,12 @@
// Special-case handling of BFC/BFI/SBFX/UBFX.
if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
- // TIED_TO operand skipped for BFC and Inst{3-0} (Reg) for BFI.
- MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0
- : getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(0));
+ if (Opcode == ARM::BFI) {
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
+ ++OpIdx;
+ }
uint32_t mask = 0;
if (!getBFCInvMask(insn, mask))
return false;
@@ -2244,9 +2248,10 @@
// We have homogeneous NEON registers for Load/Store.
unsigned RegClass = 0;
+ bool DRegPair = UseDRegPair(Opcode);
// Double-spaced registers have increments of 2.
- unsigned Inc = DblSpaced ? 2 : 1;
+ unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1;
unsigned Rn = decodeRn(insn);
unsigned Rm = decodeRm(insn);
@@ -2292,8 +2297,7 @@
RegClass = OpInfo[OpIdx].RegClass;
while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
- getRegisterEnum(B, RegClass, Rd,
- UseDRegPair(Opcode))));
+ getRegisterEnum(B, RegClass, Rd, DRegPair)));
Rd += Inc;
++OpIdx;
}
@@ -2312,8 +2316,7 @@
while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
- getRegisterEnum(B, RegClass, Rd,
- UseDRegPair(Opcode))));
+ getRegisterEnum(B, RegClass, Rd, DRegPair)));
Rd += Inc;
++OpIdx;
}
@@ -2351,6 +2354,11 @@
}
}
+ // Accessing registers past the end of the NEON register file is not
+ // defined.
+ if (Rd > 32)
+ return false;
+
return true;
}
@@ -2423,10 +2431,14 @@
break;
case ARM::VMOVv4i16:
case ARM::VMOVv8i16:
+ case ARM::VMVNv4i16:
+ case ARM::VMVNv8i16:
esize = ESize16;
break;
case ARM::VMOVv2i32:
case ARM::VMOVv4i32:
+ case ARM::VMVNv2i32:
+ case ARM::VMVNv4i32:
esize = ESize32;
break;
case ARM::VMOVv1i64:
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Sat Jul 31 19:59:02 2010
@@ -23,7 +23,8 @@
#include "llvm/MC/MCInst.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "ARMInstrInfo.h"
+#include "ARMBaseInstrInfo.h"
+#include "ARMRegisterInfo.h"
#include "ARMDisassembler.h"
namespace llvm {
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