[llvm-branch-commits] [llvm-branch] r109963 [2/2] - in /llvm/branches/wendling/eh: ./ autoconf/ docs/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter2/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ModuleMaker/ examples/ParallelJIT/ include/llvm-c/ include/llvm/ include/llvm/ADT/ include/llvm/Analysis/ include/llvm/CodeGen/ include/llvm/Comp...
Bill Wendling
isanbard at gmail.com
Sat Jul 31 17:59:05 PDT 2010
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Sat Jul 31 19:59:02 2010
@@ -103,7 +103,7 @@
}
static inline bool IsGPR(unsigned RegClass) {
- return RegClass == ARM::GPRRegClassID;
+ return RegClass == ARM::GPRRegClassID || RegClass == ARM::rGPRRegClassID;
}
// Utilities for 32-bit Thumb instructions.
@@ -1324,7 +1324,7 @@
&& OpInfo[1].RegClass == ARM::GPRRegClassID
&& OpInfo[2].RegClass < 0
&& OpInfo[3].RegClass < 0
- && "Exactlt 4 operands expect and first two as reg operands");
+ && "Exactly 4 operands expect and first two as reg operands");
// Only need to populate the src reg operand.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
@@ -1338,17 +1338,20 @@
OpIdx = 0;
assert(NumOps >= 2
- && OpInfo[0].RegClass == ARM::GPRRegClassID
- && OpInfo[1].RegClass == ARM::GPRRegClassID
+ && (OpInfo[0].RegClass == ARM::GPRRegClassID ||
+ OpInfo[0].RegClass == ARM::rGPRRegClassID)
+ && (OpInfo[1].RegClass == ARM::GPRRegClassID ||
+ OpInfo[1].RegClass == ARM::rGPRRegClassID)
&& "Expect >= 2 operands and first two as reg operands");
- bool ThreeReg = (NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID);
+ bool ThreeReg = (NumOps > 2 && (OpInfo[2].RegClass == ARM::GPRRegClassID ||
+ OpInfo[2].RegClass == ARM::rGPRRegClassID));
bool NoDstReg = (decodeRs(insn) == 0xF);
// Build the register operands, followed by the constant shift specifier.
MI.addOperand(MCOperand::CreateReg(
- getRegisterEnum(B, ARM::GPRRegClassID,
+ getRegisterEnum(B, OpInfo[0].RegClass,
NoDstReg ? decodeRn(insn) : decodeRs(insn))));
++OpIdx;
@@ -1359,7 +1362,7 @@
MI.addOperand(MI.getOperand(Idx));
++OpIdx;
} else if (!NoDstReg) {
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[1].RegClass,
decodeRn(insn))));
++OpIdx;
} else {
@@ -1368,7 +1371,7 @@
}
}
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
decodeRm(insn))));
++OpIdx;
@@ -1416,16 +1419,20 @@
OpIdx = 0;
- assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::GPRRegClassID
+ unsigned RdRegClassID = OpInfo[0].RegClass;
+ assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
+ RdRegClassID == ARM::rGPRRegClassID)
&& "Expect >= 2 operands and first one as reg operand");
- bool TwoReg = (OpInfo[1].RegClass == ARM::GPRRegClassID);
+ unsigned RnRegClassID = OpInfo[1].RegClass;
+ bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
+ || RnRegClassID == ARM::rGPRRegClassID);
bool NoDstReg = (decodeRs(insn) == 0xF);
// Build the register operands, followed by the modified immediate.
MI.addOperand(MCOperand::CreateReg(
- getRegisterEnum(B, ARM::GPRRegClassID,
+ getRegisterEnum(B, RdRegClassID,
NoDstReg ? decodeRn(insn) : decodeRs(insn))));
++OpIdx;
@@ -1434,7 +1441,7 @@
DEBUG(errs()<<"Thumb2 encoding error: d==15 for DPModImm 2-reg instr.\n");
return false;
}
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
decodeRn(insn))));
++OpIdx;
}
@@ -1506,14 +1513,18 @@
OpIdx = 0;
- assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::GPRRegClassID
+ unsigned RdRegClassID = OpInfo[0].RegClass;
+ assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
+ RdRegClassID == ARM::rGPRRegClassID)
&& "Expect >= 2 operands and first one as reg operand");
- bool TwoReg = (OpInfo[1].RegClass == ARM::GPRRegClassID);
+ unsigned RnRegClassID = OpInfo[1].RegClass;
+ bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
+ || RnRegClassID == ARM::rGPRRegClassID);
// Build the register operand(s), followed by the immediate(s).
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RdRegClassID,
decodeRs(insn))));
++OpIdx;
@@ -1521,7 +1532,7 @@
if (Thumb2SaturateOpcode(Opcode)) {
MI.addOperand(MCOperand::CreateImm(decodeThumb2SaturatePos(Opcode, insn)));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
decodeRn(insn))));
if (Opcode == ARM::t2SSAT16 || Opcode == ARM::t2USAT16) {
@@ -1549,12 +1560,19 @@
MI.addOperand(MI.getOperand(Idx));
} else {
// Add src reg operand.
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
decodeRn(insn))));
}
++OpIdx;
}
+ if (Opcode == ARM::t2BFI) {
+ // Add val reg operand.
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
+ decodeRn(insn))));
+ ++OpIdx;
+ }
+
assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
&& !OpInfo[OpIdx].isOptionalDef()
&& "Pure imm operand expected");
@@ -1567,7 +1585,7 @@
MI.addOperand(MCOperand::CreateImm(getIImm3Imm8(insn)));
else if (Opcode == ARM::t2MOVi16 || Opcode == ARM::t2MOVTi16)
MI.addOperand(MCOperand::CreateImm(getImm16(insn)));
- else if (Opcode == ARM::t2BFC) {
+ else if (Opcode == ARM::t2BFC || Opcode == ARM::t2BFI) {
uint32_t mask = 0;
if (getBitfieldInvMask(insn, mask))
MI.addOperand(MCOperand::CreateImm(mask));
@@ -1575,17 +1593,10 @@
return false;
} else {
// Handle the case of: lsb width
- assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX ||
- Opcode == ARM::t2BFI) && "Unexpected opcode");
+ assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX)
+ && "Unexpected opcode");
MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
- if (Opcode == ARM::t2BFI) {
- if (getMsb(insn) < getLsb(insn)) {
- DEBUG(errs() << "Encoding error: msb < lsb\n");
- return false;
- }
- MI.addOperand(MCOperand::CreateImm(getMsb(insn) - getLsb(insn) + 1));
- } else
- MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1));
+ MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1));
++OpIdx;
}
@@ -1959,25 +1970,25 @@
OpIdx = 0;
assert(NumOps >= 2 &&
- OpInfo[0].RegClass == ARM::GPRRegClassID &&
- OpInfo[1].RegClass == ARM::GPRRegClassID &&
+ OpInfo[0].RegClass == ARM::rGPRRegClassID &&
+ OpInfo[1].RegClass == ARM::rGPRRegClassID &&
"Expect >= 2 operands and first two as reg operands");
// Build the register operands, followed by the optional rotation amount.
- bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
+ bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::rGPRRegClassID;
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRs(insn))));
++OpIdx;
if (ThreeReg) {
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRn(insn))));
++OpIdx;
}
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRm(insn))));
++OpIdx;
@@ -2009,26 +2020,26 @@
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
assert(NumOps >= 3 &&
- OpInfo[0].RegClass == ARM::GPRRegClassID &&
- OpInfo[1].RegClass == ARM::GPRRegClassID &&
- OpInfo[2].RegClass == ARM::GPRRegClassID &&
+ OpInfo[0].RegClass == ARM::rGPRRegClassID &&
+ OpInfo[1].RegClass == ARM::rGPRRegClassID &&
+ OpInfo[2].RegClass == ARM::rGPRRegClassID &&
"Expect >= 3 operands and first three as reg operands");
// Build the register operands.
- bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::GPRRegClassID;
+ bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRs(insn))));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRn(insn))));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRm(insn))));
if (FourReg)
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRd(insn))));
NumOpsAdded = FourReg ? 4 : 3;
@@ -2054,26 +2065,26 @@
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
assert(NumOps >= 3 &&
- OpInfo[0].RegClass == ARM::GPRRegClassID &&
- OpInfo[1].RegClass == ARM::GPRRegClassID &&
- OpInfo[2].RegClass == ARM::GPRRegClassID &&
+ OpInfo[0].RegClass == ARM::rGPRRegClassID &&
+ OpInfo[1].RegClass == ARM::rGPRRegClassID &&
+ OpInfo[2].RegClass == ARM::rGPRRegClassID &&
"Expect >= 3 operands and first three as reg operands");
- bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::GPRRegClassID;
+ bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
// Build the register operands.
if (FourReg)
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRd(insn))));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRs(insn))));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRn(insn))));
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
decodeRm(insn))));
if (FourReg)
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Makefile (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Makefile Sat Jul 31 19:59:02 2010
@@ -17,7 +17,8 @@
ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc \
ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
- ARMGenDecoderTables.inc ARMGenEDInfo.inc
+ ARMGenDecoderTables.inc ARMGenEDInfo.inc \
+ ARMGenFastISel.inc
DIRS = AsmPrinter AsmParser Disassembler TargetInfo
Modified: llvm/branches/wendling/eh/lib/Target/ARM/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/README.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/README.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/README.txt Sat Jul 31 19:59:02 2010
@@ -611,23 +611,49 @@
//===---------------------------------------------------------------------===//
-Given the following on ARMv7:
-int test1(int A, int B) {
- return (A&-8388481)|(B&8388480);
-}
+The code generated for bswap on armv4/5 (CPUs without rev) is less than ideal:
+
+int a(int x) { return __builtin_bswap32(x); }
-We currently generate:
- bfc r0, #7, #16
- movw r2, #:lower16:8388480
- movt r2, #:upper16:8388480
- and r1, r1, r2
- orr r0, r1, r0
+a:
+ mov r1, #255, 24
+ mov r2, #255, 16
+ and r1, r1, r0, lsr #8
+ and r2, r2, r0, lsl #8
+ orr r1, r1, r0, lsr #24
+ orr r0, r2, r0, lsl #24
+ orr r0, r0, r1
bx lr
-The following is much shorter:
- lsr r1, r1, #7
- bfi r0, r1, #7, #16
+Something like the following would be better (fewer instructions/registers):
+ eor r1, r0, r0, ror #16
+ bic r1, r1, #0xff0000
+ mov r1, r1, lsr #8
+ eor r0, r1, r0, ror #8
bx lr
+A custom Thumb version would also be a slight improvement over the generic
+version.
//===---------------------------------------------------------------------===//
+
+Consider the following simple C code:
+
+void foo(unsigned char *a, unsigned char *b, int *c) {
+ if ((*a | *b) == 0) *c = 0;
+}
+
+currently llvm-gcc generates something like this (nice branchless code I'd say):
+
+ ldrb r0, [r0]
+ ldrb r1, [r1]
+ orr r0, r1, r0
+ tst r0, #255
+ moveq r0, #0
+ streq r0, [r2]
+ bx lr
+
+Note that both "tst" and "moveq" are redundant.
+
+//===---------------------------------------------------------------------===//
+
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -68,7 +68,7 @@
.addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
}
-bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
+bool Thumb1RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
// It's not always a good idea to include the call frame as part of the
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Thumb1RegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -38,7 +38,7 @@
unsigned PredReg = 0) const;
/// Code Generation virtual methods...
- bool hasReservedCallFrame(MachineFunction &MF) const;
+ bool hasReservedCallFrame(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Thumb2ITBlockPass.cpp Sat Jul 31 19:59:02 2010
@@ -91,35 +91,53 @@
}
}
+static bool isCopy(MachineInstr *MI) {
+ switch (MI->getOpcode()) {
+ default:
+ return false;
+ case ARM::MOVr:
+ case ARM::MOVr_TC:
+ case ARM::tMOVr:
+ case ARM::tMOVgpr2tgpr:
+ case ARM::tMOVtgpr2gpr:
+ case ARM::tMOVgpr2gpr:
+ case ARM::t2MOVr:
+ return true;
+ }
+}
+
bool
Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
SmallSet<unsigned, 4> &Defs,
SmallSet<unsigned, 4> &Uses) {
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
- assert(SrcSubIdx == 0 && DstSubIdx == 0 &&
- "Sub-register indices still around?");
- // llvm models select's as two-address instructions. That means a copy
- // is inserted before a t2MOVccr, etc. If the copy is scheduled in
- // between selects we would end up creating multiple IT blocks.
-
- // First check if it's safe to move it.
- if (Uses.count(DstReg) || Defs.count(SrcReg))
- return false;
-
- // Then peek at the next instruction to see if it's predicated on CC or OCC.
- // If not, then there is nothing to be gained by moving the copy.
- MachineBasicBlock::iterator I = MI; ++I;
- MachineBasicBlock::iterator E = MI->getParent()->end();
- while (I != E && I->isDebugValue())
- ++I;
- if (I != E) {
- unsigned NPredReg = 0;
- ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
- if (NCC == CC || NCC == OCC)
- return true;
- }
+ if (!isCopy(MI))
+ return false;
+ // llvm models select's as two-address instructions. That means a copy
+ // is inserted before a t2MOVccr, etc. If the copy is scheduled in
+ // between selects we would end up creating multiple IT blocks.
+ assert(MI->getOperand(0).getSubReg() == 0 &&
+ MI->getOperand(1).getSubReg() == 0 &&
+ "Sub-register indices still around?");
+
+ unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned SrcReg = MI->getOperand(1).getReg();
+
+ // First check if it's safe to move it.
+ if (Uses.count(DstReg) || Defs.count(SrcReg))
+ return false;
+
+ // Then peek at the next instruction to see if it's predicated on CC or OCC.
+ // If not, then there is nothing to be gained by moving the copy.
+ MachineBasicBlock::iterator I = MI; ++I;
+ MachineBasicBlock::iterator E = MI->getParent()->end();
+ while (I != E && I->isDebugValue())
+ ++I;
+ if (I != E) {
+ unsigned NPredReg = 0;
+ ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
+ if (NCC == CC || NCC == OCC)
+ return true;
}
return false;
}
Modified: llvm/branches/wendling/eh/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/ARM/Thumb2InstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -147,8 +147,8 @@
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
- RC == ARM::tcGPRRegisterClass) {
+ if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
+ RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
@@ -173,8 +173,8 @@
unsigned DestReg, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
- if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
- RC == ARM::tcGPRRegisterClass) {
+ if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
+ RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
Modified: llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -27,32 +27,6 @@
RI(*this) { }
-bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg, unsigned& destReg,
- unsigned& SrcSR, unsigned& DstSR) const {
- unsigned oc = MI.getOpcode();
- if (oc == Alpha::BISr ||
- oc == Alpha::CPYSS ||
- oc == Alpha::CPYST ||
- oc == Alpha::CPYSSt ||
- oc == Alpha::CPYSTs) {
- // or r1, r2, r2
- // cpys(s|t) r1 r2 r2
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isReg() &&
- "invalid Alpha BIS instruction!");
- if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- SrcSR = DstSR = 0;
- return true;
- }
- }
- return false;
-}
-
unsigned
AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
Modified: llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Alpha/AlphaInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -30,12 +30,6 @@
///
virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
Modified: llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -28,34 +28,6 @@
RI(ST, *this),
Subtarget(ST) {}
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg,
- unsigned &DstReg,
- unsigned &SrcSR,
- unsigned &DstSR) const {
- SrcSR = DstSR = 0; // No sub-registers.
- switch (MI.getOpcode()) {
- case BF::MOVE:
- case BF::MOVE_ncccc:
- case BF::MOVE_ccncc:
- case BF::MOVECC_zext:
- case BF::MOVECC_nz:
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- case BF::SLL16i:
- if (MI.getOperand(2).getImm()!=0)
- return false;
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- default:
- return false;
- }
-}
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Blackfin/BlackfinInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -30,10 +30,6 @@
/// always be able to get register info as well (through this method).
virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -54,148 +54,6 @@
RI(*TM.getSubtargetImpl(), *this)
{ /* NOP */ }
-bool
-SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg,
- unsigned& destReg,
- unsigned& SrcSR, unsigned& DstSR) const {
- SrcSR = DstSR = 0; // No sub-registers.
-
- switch (MI.getOpcode()) {
- default:
- break;
- case SPU::ORIv4i32:
- case SPU::ORIr32:
- case SPU::ORHIv8i16:
- case SPU::ORHIr16:
- case SPU::ORHIi8i16:
- case SPU::ORBIv16i8:
- case SPU::ORBIr8:
- case SPU::ORIi16i32:
- case SPU::ORIi8i32:
- case SPU::AHIvec:
- case SPU::AHIr16:
- case SPU::AIv4i32:
- assert(MI.getNumOperands() == 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isImm() &&
- "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
- if (MI.getOperand(2).getImm() == 0) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- break;
- case SPU::AIr32:
- assert(MI.getNumOperands() == 3 &&
- "wrong number of operands to AIr32");
- if (MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- (MI.getOperand(2).isImm() &&
- MI.getOperand(2).getImm() == 0)) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- break;
- case SPU::LRr8:
- case SPU::LRr16:
- case SPU::LRr32:
- case SPU::LRf32:
- case SPU::LRr64:
- case SPU::LRf64:
- case SPU::LRr128:
- case SPU::LRv16i8:
- case SPU::LRv8i16:
- case SPU::LRv4i32:
- case SPU::LRv4f32:
- case SPU::LRv2i64:
- case SPU::LRv2f64:
- case SPU::ORv16i8_i8:
- case SPU::ORv8i16_i16:
- case SPU::ORv4i32_i32:
- case SPU::ORv2i64_i64:
- case SPU::ORv4f32_f32:
- case SPU::ORv2f64_f64:
- case SPU::ORi8_v16i8:
- case SPU::ORi16_v8i16:
- case SPU::ORi32_v4i32:
- case SPU::ORi64_v2i64:
- case SPU::ORf32_v4f32:
- case SPU::ORf64_v2f64:
-/*
- case SPU::ORi128_r64:
- case SPU::ORi128_f64:
- case SPU::ORi128_r32:
- case SPU::ORi128_f32:
- case SPU::ORi128_r16:
- case SPU::ORi128_r8:
-*/
- case SPU::ORi128_vec:
-/*
- case SPU::ORr64_i128:
- case SPU::ORf64_i128:
- case SPU::ORr32_i128:
- case SPU::ORf32_i128:
- case SPU::ORr16_i128:
- case SPU::ORr8_i128:
-*/
- case SPU::ORvec_i128:
-/*
- case SPU::ORr16_r32:
- case SPU::ORr8_r32:
- case SPU::ORf32_r32:
- case SPU::ORr32_f32:
- case SPU::ORr32_r16:
- case SPU::ORr32_r8:
- case SPU::ORr16_r64:
- case SPU::ORr8_r64:
- case SPU::ORr64_r16:
- case SPU::ORr64_r8:
-*/
- case SPU::ORr64_r32:
- case SPU::ORr32_r64:
- case SPU::ORf32_r32:
- case SPU::ORr32_f32:
- case SPU::ORf64_r64:
- case SPU::ORr64_f64: {
- assert(MI.getNumOperands() == 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid SPU OR<type>_<vec> or LR instruction!");
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- break;
- }
- case SPU::ORv16i8:
- case SPU::ORv8i16:
- case SPU::ORv4i32:
- case SPU::ORv2i64:
- case SPU::ORr8:
- case SPU::ORr16:
- case SPU::ORr32:
- case SPU::ORr64:
- case SPU::ORr128:
- case SPU::ORf32:
- case SPU::ORf64:
- assert(MI.getNumOperands() == 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isReg() &&
- "invalid SPU OR(vec|r32|r64|gprc) instruction!");
- if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- break;
- }
-
- return false;
-}
-
unsigned
SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPUInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -32,12 +32,6 @@
///
virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
Modified: llvm/branches/wendling/eh/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CellSPU/SPURegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -417,7 +417,7 @@
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
}
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
@@ -476,7 +476,7 @@
// Mark effective beginning of when frame pointer is ready.
MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(ReadyLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel);
MachineLocation FPDst(SPU::R1);
MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -491,7 +491,7 @@
dl = MBBI->getDebugLoc();
// Insert terminator label
- BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL))
+ BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL))
.addSym(MMI.getContext().CreateTempSymbol());
}
}
Modified: llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/CppBackend/CPPBackend.cpp Sat Jul 31 19:59:02 2010
@@ -471,14 +471,22 @@
HANDLE_ATTR(Nest);
HANDLE_ATTR(ReadNone);
HANDLE_ATTR(ReadOnly);
- HANDLE_ATTR(InlineHint);
HANDLE_ATTR(NoInline);
HANDLE_ATTR(AlwaysInline);
HANDLE_ATTR(OptimizeForSize);
HANDLE_ATTR(StackProtect);
HANDLE_ATTR(StackProtectReq);
HANDLE_ATTR(NoCapture);
+ HANDLE_ATTR(NoRedZone);
+ HANDLE_ATTR(NoImplicitFloat);
+ HANDLE_ATTR(Naked);
+ HANDLE_ATTR(InlineHint);
#undef HANDLE_ATTR
+ if (attrs & Attribute::StackAlignment)
+ Out << " | Attribute::constructStackAlignmentFromInt("
+ << Attribute::getStackAlignmentFromAttrs(attrs)
+ << ")";
+ attrs &= ~Attribute::StackAlignment;
assert(attrs == 0 && "Unhandled attribute!");
Out << ";";
nl(Out);
@@ -1404,7 +1412,8 @@
nl(Out);
}
Out << "CallInst* " << iName << " = CallInst::Create("
- << opNames[call->getNumArgOperands()] << ", " << iName << "_params.begin(), "
+ << opNames[call->getNumArgOperands()] << ", "
+ << iName << "_params.begin(), "
<< iName << "_params.end(), \"";
} else if (call->getNumArgOperands() == 1) {
Out << "CallInst* " << iName << " = CallInst::Create("
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -30,41 +30,6 @@
return op.isImm() && op.getImm() == 0;
}
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-bool MBlazeInstrInfo::
-isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
- SrcSubIdx = DstSubIdx = 0; // No sub-registers.
-
- // add $dst, $src, $zero || addu $dst, $zero, $src
- // or $dst, $src, $zero || or $dst, $zero, $src
- if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) {
- if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(2).getReg();
- return true;
- } else if (MI.getOperand(2).isReg() &&
- MI.getOperand(2).getReg() == MBlaze::R0) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- }
-
- // addi $dst, $src, 0
- // ori $dst, $src, 0
- if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) {
- if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- }
-
- return false;
-}
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MBlaze/MBlazeInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -173,12 +173,6 @@
///
virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430BranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430BranchSelector.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430BranchSelector.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430BranchSelector.cpp Sat Jul 31 19:59:02 2010
@@ -52,7 +52,8 @@
}
bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) {
- const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
+ const MSP430InstrInfo *TII =
+ static_cast<const MSP430InstrInfo*>(Fn.getTarget().getInstrInfo());
// Give the blocks of the function a dense, in-order, numbering.
Fn.RenumberBlocks();
BlockSizes.resize(Fn.getNumBlockIDs());
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -100,27 +100,6 @@
}
bool
-MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
- SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
-
- switch (MI.getOpcode()) {
- default:
- return false;
- case MSP430::MOV8rr:
- case MSP430::MOV16rr:
- assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid register-register move instruction");
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- return true;
- }
-}
-
-bool
MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
@@ -361,7 +340,7 @@
switch (Desc.getOpcode()) {
default:
assert(0 && "Unknown instruction size!");
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430InstrInfo.h Sat Jul 31 19:59:02 2010
@@ -54,10 +54,6 @@
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
- bool isMoveInstr(const MachineInstr& MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill,
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -101,7 +101,7 @@
MFI->isFrameAddressTaken());
}
-bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
+bool MSP430RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo()->hasVarSizedObjects();
}
Modified: llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/MSP430/MSP430RegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -40,7 +40,7 @@
const TargetRegisterClass* getPointerRegClass(unsigned Kind = 0) const;
bool hasFP(const MachineFunction &MF) const;
- bool hasReservedCallFrame(MachineFunction &MF) const;
+ bool hasReservedCallFrame(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
Modified: llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -18,6 +18,8 @@
#include "MipsInstrInfo.h"
#include "MipsTargetMachine.h"
#include "MipsMachineFunction.h"
+#include "llvm/BasicBlock.h"
+#include "llvm/Instructions.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineConstantPool.h"
@@ -75,6 +77,7 @@
}
virtual void EmitFunctionBodyStart();
virtual void EmitFunctionBodyEnd();
+ virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
static const char *getRegisterName(unsigned RegNo);
virtual void EmitFunctionEntryLabel();
@@ -227,6 +230,23 @@
}
+/// isBlockOnlyReachableByFallthough - Return true if the basic block has
+/// exactly one predecessor and the control transfer mechanism between
+/// the predecessor and this block is a fall-through.
+bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
+ const {
+ // The predecessor has to be immediately before this block.
+ const MachineBasicBlock *Pred = *MBB->pred_begin();
+
+ // If the predecessor is a switch statement, assume a jump table
+ // implementation, so it is not a fall through.
+ if (const BasicBlock *bb = Pred->getBasicBlock())
+ if (isa<SwitchInst>(bb->getTerminator()))
+ return false;
+
+ return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
+}
+
// Print out an operand for an inline asm expression.
bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant,const char *ExtraCode,
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsISelLowering.cpp Sat Jul 31 19:59:02 2010
@@ -317,13 +317,13 @@
BB->addSuccessor(sinkMBB);
// sinkMBB:
- // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
+ // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
// ...
BB = sinkMBB;
BuildMI(*BB, BB->begin(), dl,
TII->get(Mips::PHI), MI->getOperand(0).getReg())
- .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
- .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
+ .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
+ .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
@@ -542,7 +542,7 @@
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
- if (IsPIC) {
+ if (!IsPIC) {
SDValue Ops[] = { JTI };
HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
} else // Emit Load from Global Pointer
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -30,53 +30,6 @@
return op.isImm() && op.getImm() == 0;
}
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-bool MipsInstrInfo::
-isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const
-{
- SrcSubIdx = DstSubIdx = 0; // No sub-registers.
-
- // addu $dst, $src, $zero || addu $dst, $zero, $src
- // or $dst, $src, $zero || or $dst, $zero, $src
- if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
- if (MI.getOperand(1).getReg() == Mips::ZERO) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(2).getReg();
- return true;
- } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- }
-
- // mov $fpDst, $fpSrc
- // mfc $gpDst, $fpSrc
- // mtc $fpDst, $gpSrc
- if (MI.getOpcode() == Mips::FMOV_S32 ||
- MI.getOpcode() == Mips::FMOV_D32 ||
- MI.getOpcode() == Mips::MFC1 ||
- MI.getOpcode() == Mips::MTC1 ||
- MI.getOpcode() == Mips::MOVCCRToCCR) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
-
- // addiu $dst, $src, 0
- if (MI.getOpcode() == Mips::ADDiu) {
- if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- }
-
- return false;
-}
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Mips/MipsInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -174,12 +174,6 @@
///
virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16.h Sat Jul 31 19:59:02 2010
@@ -58,13 +58,10 @@
ESNames() {}
public:
~ESNames() {
- std::vector<char*>::iterator it = stk.end();
- it--;
- while(stk.end() != stk.begin())
+ while (!stk.empty())
{
- char* p = *it;
+ char* p = stk.back();
delete [] p;
- it--;
stk.pop_back();
}
}
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.cpp Sat Jul 31 19:59:02 2010
@@ -312,6 +312,16 @@
computeRegisterProperties();
}
+std::pair<const TargetRegisterClass*, uint8_t>
+PIC16TargetLowering::findRepresentativeClass(EVT VT) const {
+ switch (VT.getSimpleVT().SimpleTy) {
+ default:
+ return TargetLowering::findRepresentativeClass(VT);
+ case MVT::i16:
+ return std::make_pair(PIC16::FSR16RegisterClass, 1);
+ }
+}
+
// getOutFlag - Extract the flag result if the Op has it.
static SDValue getOutFlag(SDValue &Op) {
// Flag is the last value of the node.
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16ISelLowering.h Sat Jul 31 19:59:02 2010
@@ -181,6 +181,9 @@
// FIXME: The function never seems to be aligned.
return 1;
}
+ protected:
+ std::pair<const TargetRegisterClass*, uint8_t>
+ findRepresentativeClass(EVT VT) const;
private:
// If the Node is a BUILD_PAIR representing a direct Address,
// then this function will return true.
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -167,21 +167,6 @@
.addReg(SrcReg, getKillRegState(KillSrc));
}
-bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DestReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
- SrcSubIdx = DstSubIdx = 0; // No sub-registers.
-
- if (MI.getOpcode() == PIC16::copy_fsr
- || MI.getOpcode() == PIC16::copy_w) {
- DestReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
-
- return false;
-}
-
/// InsertBranch - Insert a branch into the end of the specified
/// MachineBasicBlock. This operands to this method are the same as those
/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16InstrInfo.h Sat Jul 31 19:59:02 2010
@@ -61,10 +61,6 @@
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
virtual
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
Modified: llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/PIC16Overlay.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/PIC16Overlay.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/PIC16Overlay.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PIC16/PIC16Passes/PIC16Overlay.cpp Sat Jul 31 19:59:02 2010
@@ -171,8 +171,9 @@
for (Module::iterator MI = M.begin(), E = M.end(); MI != E; ++MI) {
for (Value::use_iterator I = MI->use_begin(), E = MI->use_end(); I != E;
++I) {
- if ((!isa<CallInst>(I) && !isa<InvokeInst>(I))
- || !CallSite(cast<Instruction>(I)).isCallee(I)) {
+ User *U = *I;
+ if ((!isa<CallInst>(U) && !isa<InvokeInst>(U))
+ || !CallSite(cast<Instruction>(U)).isCallee(I)) {
setColor(MI, ++IndirectCallColor);
break;
}
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCBranchSelector.cpp Sat Jul 31 19:59:02 2010
@@ -53,7 +53,8 @@
}
bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
- const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
+ const PPCInstrInfo *TII =
+ static_cast<const PPCInstrInfo*>(Fn.getTarget().getInstrInfo());
// Give the blocks of the function a dense, in-order, numbering.
Fn.RenumberBlocks();
BlockSizes.resize(Fn.getNumBlockIDs());
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCCodeEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -110,7 +110,7 @@
default:
MCE.emitWordBE(getBinaryCodeForInstr(MI));
break;
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getMCSymbol());
break;
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -18,8 +18,11 @@
#include "PPCGenInstrInfo.inc"
#include "PPCTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@@ -36,67 +39,6 @@
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
RI(*TM.getSubtargetImpl(), *this) {}
-bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg,
- unsigned& destReg,
- unsigned& sourceSubIdx,
- unsigned& destSubIdx) const {
- sourceSubIdx = destSubIdx = 0; // No sub-registers.
-
- unsigned oc = MI.getOpcode();
- if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
- oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isReg() &&
- "invalid PPC OR instruction!");
- if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- } else if (oc == PPC::ADDI) { // addi r1, r2, 0
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(2).isImm() &&
- "invalid PPC ADDI instruction!");
- if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- } else if (oc == PPC::ORI) { // ori r1, r2, 0
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isImm() &&
- "invalid PPC ORI instruction!");
- if (MI.getOperand(2).getImm() == 0) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
- assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid PPC FMR instruction");
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
- assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid PPC MCRF instruction");
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
- }
- return false;
-}
-
unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
@@ -524,6 +466,14 @@
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
MBB.insert(MI, NewMIs[i]);
+
+ const MachineFrameInfo &MFI = *MF.getFrameInfo();
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
+ MachineMemOperand::MOStore, /*Offset=*/0,
+ MFI.getObjectSize(FrameIdx),
+ MFI.getObjectAlignment(FrameIdx));
+ NewMIs.back()->addMemOperand(MF, MMO);
}
void
@@ -637,6 +587,14 @@
LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
MBB.insert(MI, NewMIs[i]);
+
+ const MachineFrameInfo &MFI = *MF.getFrameInfo();
+ MachineMemOperand *MMO =
+ MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
+ MachineMemOperand::MOLoad, /*Offset=*/0,
+ MFI.getObjectSize(FrameIdx),
+ MFI.getObjectAlignment(FrameIdx));
+ NewMIs.back()->addMemOperand(MF, MMO);
}
MachineInstr*
@@ -667,7 +625,7 @@
const char *AsmStr = MI->getOperand(0).getSymbolName();
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
}
- case PPC::DBG_LABEL:
+ case PPC::PROLOG_LABEL:
case PPC::EH_LABEL:
case PPC::GC_LABEL:
case PPC::DBG_VALUE:
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -82,12 +82,6 @@
///
virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCInstrInfo.td Sat Jul 31 19:59:02 2010
@@ -1022,9 +1022,7 @@
}
}
-/// FMR is split into 2 versions, one for 4/8 byte FP, and one for extending.
-///
-/// Note that these are defined as pseudo-ops on the PPC970 because they are
+/// Note that FMR is defined as pseudo-ops on the PPC970 because they are
/// often coalesced away and we don't want the dispatch group builder to think
/// that they will fill slots (which could cause the load of a LSU reject to
/// sneak into a d-group with a store).
@@ -1032,10 +1030,6 @@
"fmr $frD, $frB", FPGeneral,
[]>, // (set F4RC:$frD, F4RC:$frB)
PPC970_Unit_Pseudo;
-def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
- "fmr $frD, $frB", FPGeneral,
- [(set F8RC:$frD, (fextend F4RC:$frB))]>,
- PPC970_Unit_Pseudo;
let PPC970_Unit = 3 in { // FPU Operations.
// These are artificially split into two different forms, for 4/8 byte FP.
@@ -1476,10 +1470,13 @@
(LHZ iaddr:$src)>;
def : Pat<(extloadi16 xaddr:$src),
(LHZX xaddr:$src)>;
-def : Pat<(extloadf32 iaddr:$src),
- (FMRSD (LFS iaddr:$src))>;
-def : Pat<(extloadf32 xaddr:$src),
- (FMRSD (LFSX xaddr:$src))>;
+def : Pat<(f64 (extloadf32 iaddr:$src)),
+ (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
+def : Pat<(f64 (extloadf32 xaddr:$src)),
+ (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
+
+def : Pat<(f64 (fextend F4RC:$src)),
+ (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
// Memory barriers
def : Pat<(membarrier (i32 imm /*ll*/),
Modified: llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/PowerPC/PPCRegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -449,8 +449,8 @@
// Get stack alignments.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned MaxAlign = MFI->getMaxAlignment();
- assert(MaxAlign <= TargetAlign &&
- "Dynamic alloca with large aligns not supported");
+ if (MaxAlign > TargetAlign)
+ report_fatal_error("Dynamic alloca with large aligns not supported");
// Determine the previous frame's address. If FrameSize can't be
// represented as 16 bits or we need special alignment, then we load the
@@ -1318,7 +1318,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
// Show update of SP.
if (NegFrameSize) {
@@ -1361,7 +1361,7 @@
ReadyLabel = MMI.getContext().CreateTempSymbol();
// Mark effective beginning of when frame pointer is ready.
- BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
(isPPC64 ? PPC::X1 : PPC::R1));
Modified: llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -28,46 +28,6 @@
RI(ST, *this), Subtarget(ST) {
}
-static bool isZeroImm(const MachineOperand &op) {
- return op.isImm() && op.getImm() == 0;
-}
-
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-///
-bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSR, unsigned &DstSR) const {
- SrcSR = DstSR = 0; // No sub-registers.
-
- // We look for 3 kinds of patterns here:
- // or with G0 or 0
- // add with G0 or 0
- // fmovs or FpMOVD (pseudo double move).
- if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
- if (MI.getOperand(1).getReg() == SP::G0) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(2).getReg();
- return true;
- } else if (MI.getOperand(2).getReg() == SP::G0) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
- isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
- MI.getOpcode() == SP::FMOVD) {
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- return true;
- }
- return false;
-}
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/Sparc/SparcInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -43,12 +43,6 @@
///
virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -141,31 +141,6 @@
.addReg(SrcReg, getKillRegState(KillSrc));
}
-bool
-SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
- switch (MI.getOpcode()) {
- default:
- return false;
- case SystemZ::MOV32rr:
- case SystemZ::MOV64rr:
- case SystemZ::MOV64rrP:
- case SystemZ::MOV128rr:
- case SystemZ::FMOV32rr:
- case SystemZ::FMOV64rr:
- assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid register-register move instruction");
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
- return true;
- }
-}
-
unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
switch (MI->getOpcode()) {
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -65,9 +65,6 @@
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
- bool isMoveInstr(const MachineInstr& MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
Modified: llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/SystemZ/SystemZRegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -34,7 +34,7 @@
BitVector getReservedRegs(const MachineFunction &MF) const;
- bool hasReservedCallFrame(MachineFunction &MF) const { return true; }
+ bool hasReservedCallFrame(const MachineFunction &MF) const { return true; }
bool hasFP(const MachineFunction &MF) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
Modified: llvm/branches/wendling/eh/lib/Target/TargetData.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/TargetData.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/TargetData.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/TargetData.cpp Sat Jul 31 19:59:02 2010
@@ -34,8 +34,7 @@
// Handle the Pass registration stuff necessary to use TargetData's.
// Register the default SparcV9 implementation...
-static RegisterPass<TargetData> X("targetdata", "Target Data Layout", false,
- true);
+INITIALIZE_PASS(TargetData, "targetdata", "Target Data Layout", false, true);
char TargetData::ID = 0;
//===----------------------------------------------------------------------===//
@@ -626,7 +625,7 @@
// Get the array index and the size of each array element.
if (int64_t arrayIdx = cast<ConstantInt>(Indices[CurIDX])->getSExtValue())
- Result += arrayIdx * (int64_t)getTypeAllocSize(Ty);
+ Result += (uint64_t)arrayIdx * getTypeAllocSize(Ty);
}
}
Modified: llvm/branches/wendling/eh/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/TargetMachine.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/TargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/TargetMachine.cpp Sat Jul 31 19:59:02 2010
@@ -30,7 +30,8 @@
bool NoFramePointerElimNonLeaf;
bool NoExcessFPPrecision;
bool UnsafeFPMath;
- bool FiniteOnlyFPMathOption;
+ bool NoInfsFPMath;
+ bool NoNaNsFPMath;
bool HonorSignDependentRoundingFPMathOption;
bool UseSoftFloat;
FloatABI::ABIType FloatABIType;
@@ -80,9 +81,14 @@
cl::location(UnsafeFPMath),
cl::init(false));
static cl::opt<bool, true>
-EnableFiniteOnlyFPMath("enable-finite-only-fp-math",
- cl::desc("Enable optimizations that assumes non- NaNs / +-Infs"),
- cl::location(FiniteOnlyFPMathOption),
+EnableNoInfsFPMath("enable-no-infs-fp-math",
+ cl::desc("Enable FP math optimizations that assume no +-Infs"),
+ cl::location(NoInfsFPMath),
+ cl::init(false));
+static cl::opt<bool, true>
+EnableNoNaNsFPMath("enable-no-nans-fp-math",
+ cl::desc("Enable FP math optimizations that assume no NaNs"),
+ cl::location(NoNaNsFPMath),
cl::init(false));
static cl::opt<bool, true>
EnableHonorSignDependentRoundingFPMath("enable-sign-dependent-rounding-fp-math",
@@ -290,12 +296,6 @@
/// result is "less precise" than doing those operations individually.
bool LessPreciseFPMAD() { return UnsafeFPMath || LessPreciseFPMADOption; }
- /// FiniteOnlyFPMath - This returns true when the -enable-finite-only-fp-math
- /// option is specified on the command line. If this returns false (default),
- /// the code generator is not allowed to assume that FP arithmetic arguments
- /// and results are never NaNs or +-Infs.
- bool FiniteOnlyFPMath() { return FiniteOnlyFPMathOption; }
-
/// HonorSignDependentRoundingFPMath - Return true if the codegen must assume
/// that the rounding mode of the FPU can change from its default.
bool HonorSignDependentRoundingFPMath() {
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Jul 31 19:59:02 2010
@@ -9,6 +9,7 @@
#include "llvm/Target/TargetAsmParser.h"
#include "X86.h"
+#include "X86Subtarget.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
@@ -28,6 +29,7 @@
class X86ATTAsmParser : public TargetAsmParser {
MCAsmParser &Parser;
+ TargetMachine &TM;
protected:
unsigned Is64Bit : 1;
@@ -48,13 +50,13 @@
bool ParseDirectiveWord(unsigned Size, SMLoc L);
- void InstructionCleanup(MCInst &Inst);
+ bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
+ MCInst &Inst);
- /// @name Auto-generated Match Functions
+ /// @name Auto-generated Matcher Functions
/// {
- bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- MCInst &Inst);
+ unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const;
bool MatchInstructionImpl(
const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst);
@@ -62,27 +64,32 @@
/// }
public:
- X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
- : TargetAsmParser(T), Parser(_Parser) {}
+ X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
+ : TargetAsmParser(T), Parser(_Parser), TM(TM) {
+
+ // Initialize the set of available features.
+ setAvailableFeatures(ComputeAvailableFeatures(
+ &TM.getSubtarget<X86Subtarget>()));
+ }
virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
virtual bool ParseDirective(AsmToken DirectiveID);
};
-
+
class X86_32ATTAsmParser : public X86ATTAsmParser {
public:
- X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser)
- : X86ATTAsmParser(T, _Parser) {
+ X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
+ : X86ATTAsmParser(T, _Parser, TM) {
Is64Bit = false;
}
};
class X86_64ATTAsmParser : public X86ATTAsmParser {
public:
- X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser)
- : X86ATTAsmParser(T, _Parser) {
+ X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM)
+ : X86ATTAsmParser(T, _Parser, TM) {
Is64Bit = true;
}
};
@@ -90,7 +97,7 @@
} // end anonymous namespace
/// @name Auto-generated Match Functions
-/// {
+/// {
static unsigned MatchRegisterName(StringRef Name);
@@ -109,7 +116,7 @@
} Kind;
SMLoc StartLoc, EndLoc;
-
+
union {
struct {
const char *Data;
@@ -185,7 +192,7 @@
bool isToken() const {return Kind == Token; }
bool isImm() const { return Kind == Immediate; }
-
+
bool isImmSExti16i8() const {
if (!isImm())
return false;
@@ -376,13 +383,19 @@
// FIXME: Validate register for the current architecture; we have to do
// validation later, so maybe there is no need for this here.
RegNo = MatchRegisterName(Tok.getString());
-
+
+ // FIXME: This should be done using Requires<In32BitMode> and
+ // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
+ // can be also checked.
+ if (RegNo == X86::RIZ && !Is64Bit)
+ return Error(Tok.getLoc(), "riz register in 64-bit mode only");
+
// Parse %st(1) and "%st" as "%st(0)"
if (RegNo == 0 && Tok.getString() == "st") {
RegNo = X86::ST0;
EndLoc = Tok.getLoc();
Parser.Lex(); // Eat 'st'
-
+
// Check to see if we have '(4)' after %st.
if (getLexer().isNot(AsmToken::LParen))
return false;
@@ -403,15 +416,15 @@
case 7: RegNo = X86::ST7; break;
default: return Error(IntTok.getLoc(), "invalid stack index");
}
-
+
if (getParser().Lex().isNot(AsmToken::RParen))
return Error(Parser.getTok().getLoc(), "expected ')'");
-
+
EndLoc = Tok.getLoc();
Parser.Lex(); // Eat ')'
return false;
}
-
+
// If this is "db[0-7]", match it as an alias
// for dr[0-7].
if (RegNo == 0 && Tok.getString().size() == 3 &&
@@ -426,14 +439,14 @@
case '6': RegNo = X86::DR6; break;
case '7': RegNo = X86::DR7; break;
}
-
+
if (RegNo != 0) {
EndLoc = Tok.getLoc();
Parser.Lex(); // Eat it.
return false;
}
}
-
+
if (RegNo == 0)
return Error(Tok.getLoc(), "invalid register name");
@@ -452,13 +465,17 @@
unsigned RegNo;
SMLoc Start, End;
if (ParseRegister(RegNo, Start, End)) return 0;
-
+ if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
+ Error(Start, "eiz and riz can only be used as index registers");
+ return 0;
+ }
+
// If this is a segment register followed by a ':', then this is the start
// of a memory reference, otherwise this is a normal register reference.
if (getLexer().isNot(AsmToken::Colon))
return X86Operand::CreateReg(RegNo, Start, End);
-
-
+
+
getParser().Lex(); // Eat the colon.
return ParseMemOperand(RegNo, Start);
}
@@ -477,7 +494,7 @@
/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
/// has already been parsed if present.
X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
-
+
// We have to disambiguate a parenthesized expression "(4+5)" from the start
// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
// only way to do this without lookahead is to eat the '(' and see what is
@@ -486,7 +503,7 @@
if (getLexer().isNot(AsmToken::LParen)) {
SMLoc ExprEnd;
if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
-
+
// After parsing the base expression we could either have a parenthesized
// memory address or not. If not, return now. If so, eat the (.
if (getLexer().isNot(AsmToken::LParen)) {
@@ -495,7 +512,7 @@
return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
}
-
+
// Eat the '('.
Parser.Lex();
} else {
@@ -503,17 +520,17 @@
// so we have to eat the ( to see beyond it.
SMLoc LParenLoc = Parser.getTok().getLoc();
Parser.Lex(); // Eat the '('.
-
+
if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
// Nothing to do here, fall into the code below with the '(' part of the
// memory operand consumed.
} else {
SMLoc ExprEnd;
-
+
// It must be an parenthesized expression, parse it now.
if (getParser().ParseParenExpression(Disp, ExprEnd))
return 0;
-
+
// After parsing the base expression we could either have a parenthesized
// memory address or not. If not, return now. If so, eat the (.
if (getLexer().isNot(AsmToken::LParen)) {
@@ -522,21 +539,25 @@
return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
}
-
+
// Eat the '('.
Parser.Lex();
}
}
-
+
// If we reached here, then we just ate the ( of the memory operand. Process
// the rest of the memory operand.
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
-
+
if (getLexer().is(AsmToken::Percent)) {
SMLoc L;
if (ParseRegister(BaseReg, L, L)) return 0;
+ if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
+ Error(L, "eiz and riz can only be used as index registers");
+ return 0;
+ }
}
-
+
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex(); // Eat the comma.
@@ -545,11 +566,11 @@
// correctly.
//
// Not that even though it would be completely consistent to support syntax
- // like "1(%eax,,1)", the assembler doesn't.
+ // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
if (getLexer().is(AsmToken::Percent)) {
SMLoc L;
if (ParseRegister(IndexReg, L, L)) return 0;
-
+
if (getLexer().isNot(AsmToken::RParen)) {
// Parse the scale amount:
// ::= ',' [scale-expression]
@@ -566,7 +587,7 @@
int64_t ScaleVal;
if (getParser().ParseAbsoluteExpression(ScaleVal))
return 0;
-
+
// Validate the scale amount.
if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
@@ -583,12 +604,12 @@
int64_t Value;
if (getParser().ParseAbsoluteExpression(Value))
return 0;
-
+
Error(Loc, "cannot have scale factor without index register");
return 0;
}
}
-
+
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
if (getLexer().isNot(AsmToken::RParen)) {
Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
@@ -596,7 +617,7 @@
}
SMLoc MemEnd = Parser.getTok().getLoc();
Parser.Lex(); // Eat the ')'.
-
+
return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
MemStart, MemEnd);
}
@@ -743,6 +764,23 @@
}
}
}
+
+ // FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
+ if (PatchedName.startswith("vpclmul")) {
+ unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
+ PatchedName.slice(7, PatchedName.size() - 2))
+ .Case("lqlq", 0x00) // src1[63:0], src2[63:0]
+ .Case("hqlq", 0x01) // src1[127:64], src2[63:0]
+ .Case("lqhq", 0x10) // src1[63:0], src2[127:64]
+ .Case("hqhq", 0x11) // src1[127:64], src2[127:64]
+ .Default(~0U);
+ if (CLMULQuadWordSelect != ~0U) {
+ ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
+ getParser().getContext());
+ assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
+ PatchedName = "vpclmulqdq";
+ }
+ }
Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
if (ExtraImmOp)
@@ -819,7 +857,7 @@
if (getLexer().is(AsmToken::EndOfStatement))
break;
-
+
// FIXME: Improve diagnostic.
if (getLexer().isNot(AsmToken::Comma))
return Error(L, "unexpected token in directive");
@@ -831,57 +869,6 @@
return false;
}
-/// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
-/// imm operand, to having "rm" or "mr" operands with the offset in the disp
-/// field.
-static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
- bool isMR) {
- MCOperand Disp = Inst.getOperand(0);
-
- // Start over with an empty instruction.
- Inst = MCInst();
- Inst.setOpcode(Opc);
-
- if (!isMR)
- Inst.addOperand(MCOperand::CreateReg(RegNo));
-
- // Add the mem operand.
- Inst.addOperand(MCOperand::CreateReg(0)); // Segment
- Inst.addOperand(MCOperand::CreateImm(1)); // Scale
- Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
- Inst.addOperand(Disp); // Displacement
- Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
-
- if (isMR)
- Inst.addOperand(MCOperand::CreateReg(RegNo));
-}
-
-// FIXME: Custom X86 cleanup function to implement a temporary hack to handle
-// matching INCL/DECL correctly for x86_64. This needs to be replaced by a
-// proper mechanism for supporting (ambiguous) feature dependent instructions.
-void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
- if (!Is64Bit) return;
-
- switch (Inst.getOpcode()) {
- case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
- case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
- case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
- case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
- case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
- case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
- case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
- case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
-
- // moffset instructions are x86-32 only.
- case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
- case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
- case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
- case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
- case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
- case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
- }
-}
-
bool
X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
&Operands,
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -2,8 +2,6 @@
add_llvm_library(LLVMX86AsmPrinter
X86ATTInstPrinter.cpp
- X86AsmPrinter.cpp
X86IntelInstPrinter.cpp
- X86MCInstLower.cpp
)
add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen)
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h Sat Jul 31 19:59:02 2010
@@ -56,6 +56,9 @@
void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
printMemReference(MI, OpNo, O);
}
+ void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+ printMemReference(MI, OpNo, O);
+ }
void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
printMemReference(MI, OpNo, O);
}
Removed: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (removed)
@@ -1,680 +0,0 @@
-//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to AT&T assembly --------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to X86 machine code.
-//
-//===----------------------------------------------------------------------===//
-
-#include "X86AsmPrinter.h"
-#include "X86ATTInstPrinter.h"
-#include "X86IntelInstPrinter.h"
-#include "X86MCInstLower.h"
-#include "X86.h"
-#include "X86COFFMachineModuleInfo.h"
-#include "X86MachineFunctionInfo.h"
-#include "X86TargetMachine.h"
-#include "llvm/CallingConv.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCSectionMachO.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/CodeGen/MachineModuleInfoImpls.h"
-#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/Support/COFF.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetRegistry.h"
-#include "llvm/ADT/SmallString.h"
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// Primitive Helper Functions.
-//===----------------------------------------------------------------------===//
-
-void X86AsmPrinter::PrintPICBaseSymbol(raw_ostream &O) const {
- const TargetLowering *TLI = TM.getTargetLowering();
- O << *static_cast<const X86TargetLowering*>(TLI)->getPICBaseSymbol(MF,
- OutContext);
-}
-
-/// runOnMachineFunction - Emit the function body.
-///
-bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- SetupMachineFunction(MF);
-
- if (Subtarget->isTargetCOFF()) {
- bool Intrn = MF.getFunction()->hasInternalLinkage();
- OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
- OutStreamer.EmitCOFFSymbolStorageClass(Intrn ? COFF::IMAGE_SYM_CLASS_STATIC
- : COFF::IMAGE_SYM_CLASS_EXTERNAL);
- OutStreamer.EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION
- << COFF::SCT_COMPLEX_TYPE_SHIFT);
- OutStreamer.EndCOFFSymbolDef();
- }
-
- // Have common code print out the function header with linkage info etc.
- EmitFunctionHeader();
-
- // Emit the rest of the function body.
- EmitFunctionBody();
-
- // We didn't modify anything.
- return false;
-}
-
-/// printSymbolOperand - Print a raw symbol reference operand. This handles
-/// jump tables, constant pools, global address and external symbols, all of
-/// which print to a label with various suffixes for relocation types etc.
-void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO,
- raw_ostream &O) {
- switch (MO.getType()) {
- default: llvm_unreachable("unknown symbol type!");
- case MachineOperand::MO_JumpTableIndex:
- O << *GetJTISymbol(MO.getIndex());
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- O << *GetCPISymbol(MO.getIndex());
- printOffset(MO.getOffset(), O);
- break;
- case MachineOperand::MO_GlobalAddress: {
- const GlobalValue *GV = MO.getGlobal();
-
- MCSymbol *GVSym;
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB)
- GVSym = GetSymbolWithGlobalValueBase(GV, "$stub");
- else if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- GVSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
- else
- GVSym = Mang->getSymbol(GV);
-
- // Handle dllimport linkage.
- if (MO.getTargetFlags() == X86II::MO_DLLIMPORT)
- GVSym = OutContext.GetOrCreateSymbol(Twine("__imp_") + GVSym->getName());
-
- if (MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE) {
- MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
- MachineModuleInfoImpl::StubValueTy &StubSym =
- MMI->getObjFileInfo<MachineModuleInfoMachO>().getGVStubEntry(Sym);
- if (StubSym.getPointer() == 0)
- StubSym = MachineModuleInfoImpl::
- StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
- } else if (MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE){
- MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
- MachineModuleInfoImpl::StubValueTy &StubSym =
- MMI->getObjFileInfo<MachineModuleInfoMachO>().getHiddenGVStubEntry(Sym);
- if (StubSym.getPointer() == 0)
- StubSym = MachineModuleInfoImpl::
- StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
- } else if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
- MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$stub");
- MachineModuleInfoImpl::StubValueTy &StubSym =
- MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
- if (StubSym.getPointer() == 0)
- StubSym = MachineModuleInfoImpl::
- StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
- }
-
- // If the name begins with a dollar-sign, enclose it in parens. We do this
- // to avoid having it look like an integer immediate to the assembler.
- if (GVSym->getName()[0] != '$')
- O << *GVSym;
- else
- O << '(' << *GVSym << ')';
- printOffset(MO.getOffset(), O);
- break;
- }
- case MachineOperand::MO_ExternalSymbol: {
- const MCSymbol *SymToPrint;
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB) {
- SmallString<128> TempNameStr;
- TempNameStr += StringRef(MO.getSymbolName());
- TempNameStr += StringRef("$stub");
-
- MCSymbol *Sym = GetExternalSymbolSymbol(TempNameStr.str());
- MachineModuleInfoImpl::StubValueTy &StubSym =
- MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
- if (StubSym.getPointer() == 0) {
- TempNameStr.erase(TempNameStr.end()-5, TempNameStr.end());
- StubSym = MachineModuleInfoImpl::
- StubValueTy(OutContext.GetOrCreateSymbol(TempNameStr.str()),
- true);
- }
- SymToPrint = StubSym.getPointer();
- } else {
- SymToPrint = GetExternalSymbolSymbol(MO.getSymbolName());
- }
-
- // If the name begins with a dollar-sign, enclose it in parens. We do this
- // to avoid having it look like an integer immediate to the assembler.
- if (SymToPrint->getName()[0] != '$')
- O << *SymToPrint;
- else
- O << '(' << *SymToPrint << '(';
- break;
- }
- }
-
- switch (MO.getTargetFlags()) {
- default:
- llvm_unreachable("Unknown target flag on GV operand");
- case X86II::MO_NO_FLAG: // No flag.
- break;
- case X86II::MO_DARWIN_NONLAZY:
- case X86II::MO_DLLIMPORT:
- case X86II::MO_DARWIN_STUB:
- // These affect the name of the symbol, not any suffix.
- break;
- case X86II::MO_GOT_ABSOLUTE_ADDRESS:
- O << " + [.-";
- PrintPICBaseSymbol(O);
- O << ']';
- break;
- case X86II::MO_PIC_BASE_OFFSET:
- case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
- O << '-';
- PrintPICBaseSymbol(O);
- break;
- case X86II::MO_TLSGD: O << "@TLSGD"; break;
- case X86II::MO_GOTTPOFF: O << "@GOTTPOFF"; break;
- case X86II::MO_INDNTPOFF: O << "@INDNTPOFF"; break;
- case X86II::MO_TPOFF: O << "@TPOFF"; break;
- case X86II::MO_NTPOFF: O << "@NTPOFF"; break;
- case X86II::MO_GOTPCREL: O << "@GOTPCREL"; break;
- case X86II::MO_GOT: O << "@GOT"; break;
- case X86II::MO_GOTOFF: O << "@GOTOFF"; break;
- case X86II::MO_PLT: O << "@PLT"; break;
- case X86II::MO_TLVP: O << "@TLVP"; break;
- case X86II::MO_TLVP_PIC_BASE:
- O << "@TLVP" << '-';
- PrintPICBaseSymbol(O);
- break;
- }
-}
-
-/// print_pcrel_imm - This is used to print an immediate value that ends up
-/// being encoded as a pc-relative value. These print slightly differently, for
-/// example, a $ is not emitted.
-void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo,
- raw_ostream &O) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- switch (MO.getType()) {
- default: llvm_unreachable("Unknown pcrel immediate operand");
- case MachineOperand::MO_Immediate:
- O << MO.getImm();
- return;
- case MachineOperand::MO_MachineBasicBlock:
- O << *MO.getMBB()->getSymbol();
- return;
- case MachineOperand::MO_GlobalAddress:
- case MachineOperand::MO_ExternalSymbol:
- printSymbolOperand(MO, O);
- return;
- }
-}
-
-
-void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
- raw_ostream &O, const char *Modifier) {
- const MachineOperand &MO = MI->getOperand(OpNo);
- switch (MO.getType()) {
- default: llvm_unreachable("unknown operand type!");
- case MachineOperand::MO_Register: {
- O << '%';
- unsigned Reg = MO.getReg();
- if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
- EVT VT = (strcmp(Modifier+6,"64") == 0) ?
- MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
- ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
- Reg = getX86SubSuperRegister(Reg, VT);
- }
- O << X86ATTInstPrinter::getRegisterName(Reg);
- return;
- }
-
- case MachineOperand::MO_Immediate:
- O << '$' << MO.getImm();
- return;
-
- case MachineOperand::MO_JumpTableIndex:
- case MachineOperand::MO_ConstantPoolIndex:
- case MachineOperand::MO_GlobalAddress:
- case MachineOperand::MO_ExternalSymbol: {
- O << '$';
- printSymbolOperand(MO, O);
- break;
- }
- }
-}
-
-void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op,
- raw_ostream &O) {
- unsigned char value = MI->getOperand(Op).getImm();
- assert(value <= 7 && "Invalid ssecc argument!");
- switch (value) {
- case 0: O << "eq"; break;
- case 1: O << "lt"; break;
- case 2: O << "le"; break;
- case 3: O << "unord"; break;
- case 4: O << "neq"; break;
- case 5: O << "nlt"; break;
- case 6: O << "nle"; break;
- case 7: O << "ord"; break;
- }
-}
-
-void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
- raw_ostream &O, const char *Modifier) {
- const MachineOperand &BaseReg = MI->getOperand(Op);
- const MachineOperand &IndexReg = MI->getOperand(Op+2);
- const MachineOperand &DispSpec = MI->getOperand(Op+3);
-
- // If we really don't want to print out (rip), don't.
- bool HasBaseReg = BaseReg.getReg() != 0;
- if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
- BaseReg.getReg() == X86::RIP)
- HasBaseReg = false;
-
- // HasParenPart - True if we will print out the () part of the mem ref.
- bool HasParenPart = IndexReg.getReg() || HasBaseReg;
-
- if (DispSpec.isImm()) {
- int DispVal = DispSpec.getImm();
- if (DispVal || !HasParenPart)
- O << DispVal;
- } else {
- assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
- DispSpec.isJTI() || DispSpec.isSymbol());
- printSymbolOperand(MI->getOperand(Op+3), O);
- }
-
- if (HasParenPart) {
- assert(IndexReg.getReg() != X86::ESP &&
- "X86 doesn't allow scaling by ESP");
-
- O << '(';
- if (HasBaseReg)
- printOperand(MI, Op, O, Modifier);
-
- if (IndexReg.getReg()) {
- O << ',';
- printOperand(MI, Op+2, O, Modifier);
- unsigned ScaleVal = MI->getOperand(Op+1).getImm();
- if (ScaleVal != 1)
- O << ',' << ScaleVal;
- }
- O << ')';
- }
-}
-
-void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
- raw_ostream &O, const char *Modifier) {
- assert(isMem(MI, Op) && "Invalid memory reference!");
- const MachineOperand &Segment = MI->getOperand(Op+4);
- if (Segment.getReg()) {
- printOperand(MI, Op+4, O, Modifier);
- O << ':';
- }
- printLeaMemReference(MI, Op, O, Modifier);
-}
-
-void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op,
- raw_ostream &O) {
- PrintPICBaseSymbol(O);
- O << '\n';
- PrintPICBaseSymbol(O);
- O << ':';
-}
-
-bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
- raw_ostream &O) {
- unsigned Reg = MO.getReg();
- switch (Mode) {
- default: return true; // Unknown mode.
- case 'b': // Print QImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
- break;
- case 'h': // Print QImode high register
- Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
- break;
- case 'w': // Print HImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i16);
- break;
- case 'k': // Print SImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i32);
- break;
- case 'q': // Print DImode register
- Reg = getX86SubSuperRegister(Reg, MVT::i64);
- break;
- }
-
- O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
- return false;
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode, raw_ostream &O) {
- // Does this asm operand have a single letter operand modifier?
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- const MachineOperand &MO = MI->getOperand(OpNo);
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'a': // This is an address. Currently only 'i' and 'r' are expected.
- if (MO.isImm()) {
- O << MO.getImm();
- return false;
- }
- if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) {
- printSymbolOperand(MO, O);
- if (Subtarget->isPICStyleRIPRel())
- O << "(%rip)";
- return false;
- }
- if (MO.isReg()) {
- O << '(';
- printOperand(MI, OpNo, O);
- O << ')';
- return false;
- }
- return true;
-
- case 'c': // Don't print "$" before a global var name or constant.
- if (MO.isImm())
- O << MO.getImm();
- else if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol())
- printSymbolOperand(MO, O);
- else
- printOperand(MI, OpNo, O);
- return false;
-
- case 'A': // Print '*' before a register (it must be a register)
- if (MO.isReg()) {
- O << '*';
- printOperand(MI, OpNo, O);
- return false;
- }
- return true;
-
- case 'b': // Print QImode register
- case 'h': // Print QImode high register
- case 'w': // Print HImode register
- case 'k': // Print SImode register
- case 'q': // Print DImode register
- if (MO.isReg())
- return printAsmMRegister(MO, ExtraCode[0], O);
- printOperand(MI, OpNo, O);
- return false;
-
- case 'P': // This is the operand of a call, treat specially.
- print_pcrel_imm(MI, OpNo, O);
- return false;
-
- case 'n': // Negate the immediate or print a '-' before the operand.
- // Note: this is a temporary solution. It should be handled target
- // independently as part of the 'MC' work.
- if (MO.isImm()) {
- O << -MO.getImm();
- return false;
- }
- O << '-';
- }
- }
-
- printOperand(MI, OpNo, O);
- return false;
-}
-
-bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo, unsigned AsmVariant,
- const char *ExtraCode,
- raw_ostream &O) {
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'b': // Print QImode register
- case 'h': // Print QImode high register
- case 'w': // Print HImode register
- case 'k': // Print SImode register
- case 'q': // Print SImode register
- // These only apply to registers, ignore on mem.
- break;
- case 'P': // Don't print @PLT, but do print as memory.
- printMemReference(MI, OpNo, O, "no-rip");
- return false;
- }
- }
- printMemReference(MI, OpNo, O);
- return false;
-}
-
-void X86AsmPrinter::EmitStartOfAsmFile(Module &M) {
- if (Subtarget->isTargetDarwin())
- OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
-}
-
-
-void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
- if (Subtarget->isTargetDarwin()) {
- // All darwin targets use mach-o.
- MachineModuleInfoMachO &MMIMacho =
- MMI->getObjFileInfo<MachineModuleInfoMachO>();
-
- // Output stubs for dynamically-linked functions.
- MachineModuleInfoMachO::SymbolListTy Stubs;
-
- Stubs = MMIMacho.GetFnStubList();
- if (!Stubs.empty()) {
- const MCSection *TheSection =
- OutContext.getMachOSection("__IMPORT", "__jump_table",
- MCSectionMachO::S_SYMBOL_STUBS |
- MCSectionMachO::S_ATTR_SELF_MODIFYING_CODE |
- MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
- 5, SectionKind::getMetadata());
- OutStreamer.SwitchSection(TheSection);
-
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- // L_foo$stub:
- OutStreamer.EmitLabel(Stubs[i].first);
- // .indirect_symbol _foo
- OutStreamer.EmitSymbolAttribute(Stubs[i].second.getPointer(),
- MCSA_IndirectSymbol);
- // hlt; hlt; hlt; hlt; hlt hlt = 0xf4 = -12.
- const char HltInsts[] = { -12, -12, -12, -12, -12 };
- OutStreamer.EmitBytes(StringRef(HltInsts, 5), 0/*addrspace*/);
- }
-
- Stubs.clear();
- OutStreamer.AddBlankLine();
- }
-
- // Output stubs for external and common global variables.
- Stubs = MMIMacho.GetGVStubList();
- if (!Stubs.empty()) {
- const MCSection *TheSection =
- OutContext.getMachOSection("__IMPORT", "__pointers",
- MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS,
- SectionKind::getMetadata());
- OutStreamer.SwitchSection(TheSection);
-
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- // L_foo$non_lazy_ptr:
- OutStreamer.EmitLabel(Stubs[i].first);
- // .indirect_symbol _foo
- MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
- OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),
- MCSA_IndirectSymbol);
- // .long 0
- if (MCSym.getInt())
- // External to current translation unit.
- OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
- else
- // Internal to current translation unit.
- //
- // When we place the LSDA into the TEXT section, the type info
- // pointers need to be indirect and pc-rel. We accomplish this by
- // using NLPs. However, sometimes the types are local to the file. So
- // we need to fill in the value for the NLP in those cases.
- OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
- OutContext),
- 4/*size*/, 0/*addrspace*/);
- }
- Stubs.clear();
- OutStreamer.AddBlankLine();
- }
-
- Stubs = MMIMacho.GetHiddenGVStubList();
- if (!Stubs.empty()) {
- OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
- EmitAlignment(2);
-
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- // L_foo$non_lazy_ptr:
- OutStreamer.EmitLabel(Stubs[i].first);
- // .long _foo
- OutStreamer.EmitValue(MCSymbolRefExpr::
- Create(Stubs[i].second.getPointer(),
- OutContext),
- 4/*size*/, 0/*addrspace*/);
- }
- Stubs.clear();
- OutStreamer.AddBlankLine();
- }
-
- // Funny Darwin hack: This flag tells the linker that no global symbols
- // contain code that falls through to other global symbols (e.g. the obvious
- // implementation of multiple entry points). If this doesn't occur, the
- // linker can safely perform dead code stripping. Since LLVM never
- // generates code that does this, it is always safe to set.
- OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
- }
-
- if (Subtarget->isTargetCOFF()) {
- X86COFFMachineModuleInfo &COFFMMI =
- MMI->getObjFileInfo<X86COFFMachineModuleInfo>();
-
- // Emit type information for external functions
- typedef X86COFFMachineModuleInfo::externals_iterator externals_iterator;
- for (externals_iterator I = COFFMMI.externals_begin(),
- E = COFFMMI.externals_end();
- I != E; ++I) {
- OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
- OutStreamer.EmitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_EXTERNAL);
- OutStreamer.EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION
- << COFF::SCT_COMPLEX_TYPE_SHIFT);
- OutStreamer.EndCOFFSymbolDef();
- }
-
- // Necessary for dllexport support
- std::vector<const MCSymbol*> DLLExportedFns, DLLExportedGlobals;
-
- const TargetLoweringObjectFileCOFF &TLOFCOFF =
- static_cast<const TargetLoweringObjectFileCOFF&>(getObjFileLowering());
-
- for (Module::const_iterator I = M.begin(), E = M.end(); I != E; ++I)
- if (I->hasDLLExportLinkage())
- DLLExportedFns.push_back(Mang->getSymbol(I));
-
- for (Module::const_global_iterator I = M.global_begin(),
- E = M.global_end(); I != E; ++I)
- if (I->hasDLLExportLinkage())
- DLLExportedGlobals.push_back(Mang->getSymbol(I));
-
- // Output linker support code for dllexported globals on windows.
- if (!DLLExportedGlobals.empty() || !DLLExportedFns.empty()) {
- OutStreamer.SwitchSection(TLOFCOFF.getDrectveSection());
- SmallString<128> name;
- for (unsigned i = 0, e = DLLExportedGlobals.size(); i != e; ++i) {
- if (Subtarget->isTargetWindows())
- name = " /EXPORT:";
- else
- name = " -export:";
- name += DLLExportedGlobals[i]->getName();
- if (Subtarget->isTargetWindows())
- name += ",DATA";
- else
- name += ",data";
- OutStreamer.EmitBytes(name, 0);
- }
-
- for (unsigned i = 0, e = DLLExportedFns.size(); i != e; ++i) {
- if (Subtarget->isTargetWindows())
- name = " /EXPORT:";
- else
- name = " -export:";
- name += DLLExportedFns[i]->getName();
- OutStreamer.EmitBytes(name, 0);
- }
- }
- }
-
- if (Subtarget->isTargetELF()) {
- const TargetLoweringObjectFileELF &TLOFELF =
- static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
-
- MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
-
- // Output stubs for external and common global variables.
- MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
- if (!Stubs.empty()) {
- OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
- const TargetData *TD = TM.getTargetData();
-
- for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
- OutStreamer.EmitLabel(Stubs[i].first);
- OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
- TD->getPointerSize(), 0);
- }
- Stubs.clear();
- }
- }
-}
-
-
-//===----------------------------------------------------------------------===//
-// Target Registry Stuff
-//===----------------------------------------------------------------------===//
-
-static MCInstPrinter *createX86MCInstPrinter(const Target &T,
- unsigned SyntaxVariant,
- const MCAsmInfo &MAI) {
- if (SyntaxVariant == 0)
- return new X86ATTInstPrinter(MAI);
- if (SyntaxVariant == 1)
- return new X86IntelInstPrinter(MAI);
- return 0;
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeX86AsmPrinter() {
- RegisterAsmPrinter<X86AsmPrinter> X(TheX86_32Target);
- RegisterAsmPrinter<X86AsmPrinter> Y(TheX86_64Target);
-
- TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,createX86MCInstPrinter);
- TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,createX86MCInstPrinter);
-}
Removed: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86AsmPrinter.h (removed)
@@ -1,89 +0,0 @@
-//===-- X86AsmPrinter.h - Convert X86 LLVM code to assembly -----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// AT&T assembly code printer class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef X86ASMPRINTER_H
-#define X86ASMPRINTER_H
-
-#include "../X86.h"
-#include "../X86MachineFunctionInfo.h"
-#include "../X86TargetMachine.h"
-#include "llvm/ADT/StringSet.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/Support/Compiler.h"
-
-namespace llvm {
-
-class MachineJumpTableInfo;
-class MCContext;
-class MCInst;
-class MCStreamer;
-class MCSymbol;
-
-class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
- const X86Subtarget *Subtarget;
- public:
- explicit X86AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
- : AsmPrinter(TM, Streamer) {
- Subtarget = &TM.getSubtarget<X86Subtarget>();
- }
-
- virtual const char *getPassName() const {
- return "X86 AT&T-Style Assembly Printer";
- }
-
- const X86Subtarget &getSubtarget() const { return *Subtarget; }
-
- virtual void EmitStartOfAsmFile(Module &M);
-
- virtual void EmitEndOfAsmFile(Module &M);
-
- virtual void EmitInstruction(const MachineInstr *MI);
-
- void printSymbolOperand(const MachineOperand &MO, raw_ostream &O);
-
- // These methods are used by the tablegen'erated instruction printer.
- void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
- const char *Modifier = 0);
- void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
-
- bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &OS);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &OS);
-
- void printMachineInstruction(const MachineInstr *MI);
- void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
- void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
- const char *Modifier=NULL);
- void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
- const char *Modifier=NULL);
-
- void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
-
- void PrintPICBaseSymbol(raw_ostream &O) const;
-
- bool runOnMachineFunction(MachineFunction &F);
-
- void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
-
- MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
-};
-
-} // end namespace llvm
-
-#endif
Modified: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h Sat Jul 31 19:59:02 2010
@@ -64,6 +64,10 @@
O << "XMMWORD PTR ";
printMemReference(MI, OpNo, O);
}
+ void printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
+ O << "YMMWORD PTR ";
+ printMemReference(MI, OpNo, O);
+ }
void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
O << "DWORD PTR ";
printMemReference(MI, OpNo, O);
Removed: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (removed)
@@ -1,632 +0,0 @@
-//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains code to lower X86 MachineInstrs to their corresponding
-// MCInst records.
-//
-//===----------------------------------------------------------------------===//
-
-#include "X86MCInstLower.h"
-#include "X86AsmPrinter.h"
-#include "X86COFFMachineModuleInfo.h"
-#include "X86MCAsmInfo.h"
-#include "llvm/Analysis/DebugInfo.h"
-#include "llvm/CodeGen/MachineModuleInfoImpls.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/Type.h"
-using namespace llvm;
-
-
-const X86Subtarget &X86MCInstLower::getSubtarget() const {
- return AsmPrinter.getSubtarget();
-}
-
-MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
- assert(getSubtarget().isTargetDarwin() &&"Can only get MachO info on darwin");
- return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
-}
-
-
-MCSymbol *X86MCInstLower::GetPICBaseSymbol() const {
- const TargetLowering *TLI = AsmPrinter.TM.getTargetLowering();
- return static_cast<const X86TargetLowering*>(TLI)->
- getPICBaseSymbol(AsmPrinter.MF, Ctx);
-}
-
-/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
-/// operand to an MCSymbol.
-MCSymbol *X86MCInstLower::
-GetSymbolFromOperand(const MachineOperand &MO) const {
- assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
-
- SmallString<128> Name;
-
- if (!MO.isGlobal()) {
- assert(MO.isSymbol());
- Name += AsmPrinter.MAI->getGlobalPrefix();
- Name += MO.getSymbolName();
- } else {
- const GlobalValue *GV = MO.getGlobal();
- bool isImplicitlyPrivate = false;
- if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
- MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
- MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
- isImplicitlyPrivate = true;
-
- Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
- }
-
- // If the target flags on the operand changes the name of the symbol, do that
- // before we return the symbol.
- switch (MO.getTargetFlags()) {
- default: break;
- case X86II::MO_DLLIMPORT: {
- // Handle dllimport linkage.
- const char *Prefix = "__imp_";
- Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
- break;
- }
- case X86II::MO_DARWIN_NONLAZY:
- case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
- Name += "$non_lazy_ptr";
- MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
-
- MachineModuleInfoImpl::StubValueTy &StubSym =
- getMachOMMI().getGVStubEntry(Sym);
- if (StubSym.getPointer() == 0) {
- assert(MO.isGlobal() && "Extern symbol not handled yet");
- StubSym =
- MachineModuleInfoImpl::
- StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
- !MO.getGlobal()->hasInternalLinkage());
- }
- return Sym;
- }
- case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
- Name += "$non_lazy_ptr";
- MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
- MachineModuleInfoImpl::StubValueTy &StubSym =
- getMachOMMI().getHiddenGVStubEntry(Sym);
- if (StubSym.getPointer() == 0) {
- assert(MO.isGlobal() && "Extern symbol not handled yet");
- StubSym =
- MachineModuleInfoImpl::
- StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
- !MO.getGlobal()->hasInternalLinkage());
- }
- return Sym;
- }
- case X86II::MO_DARWIN_STUB: {
- Name += "$stub";
- MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
- MachineModuleInfoImpl::StubValueTy &StubSym =
- getMachOMMI().getFnStubEntry(Sym);
- if (StubSym.getPointer())
- return Sym;
-
- if (MO.isGlobal()) {
- StubSym =
- MachineModuleInfoImpl::
- StubValueTy(AsmPrinter.Mang->getSymbol(MO.getGlobal()),
- !MO.getGlobal()->hasInternalLinkage());
- } else {
- Name.erase(Name.end()-5, Name.end());
- StubSym =
- MachineModuleInfoImpl::
- StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
- }
- return Sym;
- }
- }
-
- return Ctx.GetOrCreateSymbol(Name.str());
-}
-
-MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
- MCSymbol *Sym) const {
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- const MCExpr *Expr = 0;
- MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
-
- switch (MO.getTargetFlags()) {
- default: llvm_unreachable("Unknown target flag on GV operand");
- case X86II::MO_NO_FLAG: // No flag.
- // These affect the name of the symbol, not any suffix.
- case X86II::MO_DARWIN_NONLAZY:
- case X86II::MO_DLLIMPORT:
- case X86II::MO_DARWIN_STUB:
- break;
-
- case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
- case X86II::MO_TLVP_PIC_BASE:
- Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
- // Subtract the pic base.
- Expr = MCBinaryExpr::CreateSub(Expr,
- MCSymbolRefExpr::Create(GetPICBaseSymbol(),
- Ctx),
- Ctx);
- break;
- case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
- case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
- case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
- case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
- case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
- case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
- case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
- case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
- case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
- case X86II::MO_PIC_BASE_OFFSET:
- case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
- case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
- Expr = MCSymbolRefExpr::Create(Sym, Ctx);
- // Subtract the pic base.
- Expr = MCBinaryExpr::CreateSub(Expr,
- MCSymbolRefExpr::Create(GetPICBaseSymbol(), Ctx),
- Ctx);
- if (MO.isJTI() && AsmPrinter.MAI->hasSetDirective()) {
- // If .set directive is supported, use it to reduce the number of
- // relocations the assembler will generate for differences between
- // local labels. This is only safe when the symbols are in the same
- // section so we are restricting it to jumptable references.
- MCSymbol *Label = Ctx.CreateTempSymbol();
- AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
- Expr = MCSymbolRefExpr::Create(Label, Ctx);
- }
- break;
- }
-
- if (Expr == 0)
- Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
-
- if (!MO.isJTI() && MO.getOffset())
- Expr = MCBinaryExpr::CreateAdd(Expr,
- MCConstantExpr::Create(MO.getOffset(), Ctx),
- Ctx);
- return MCOperand::CreateExpr(Expr);
-}
-
-
-
-static void lower_subreg32(MCInst *MI, unsigned OpNo) {
- // Convert registers in the addr mode according to subreg32.
- unsigned Reg = MI->getOperand(OpNo).getReg();
- if (Reg != 0)
- MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
-}
-
-static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
- // Convert registers in the addr mode according to subreg64.
- for (unsigned i = 0; i != 4; ++i) {
- if (!MI->getOperand(OpNo+i).isReg()) continue;
-
- unsigned Reg = MI->getOperand(OpNo+i).getReg();
- if (Reg == 0) continue;
-
- MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
- }
-}
-
-/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
-static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
- OutMI.setOpcode(NewOpc);
- lower_subreg32(&OutMI, 0);
-}
-/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
-static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
- OutMI.setOpcode(NewOpc);
- OutMI.addOperand(OutMI.getOperand(0));
- OutMI.addOperand(OutMI.getOperand(0));
-}
-
-/// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
-/// a short fixed-register form.
-static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
- unsigned ImmOp = Inst.getNumOperands() - 1;
- assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() &&
- ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
- Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
- Inst.getNumOperands() == 2) && "Unexpected instruction!");
-
- // Check whether the destination register can be fixed.
- unsigned Reg = Inst.getOperand(0).getReg();
- if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
- return;
-
- // If so, rewrite the instruction.
- MCOperand Saved = Inst.getOperand(ImmOp);
- Inst = MCInst();
- Inst.setOpcode(Opcode);
- Inst.addOperand(Saved);
-}
-
-/// \brief Simplify things like MOV32rm to MOV32o32a.
-static void SimplifyShortMoveForm(MCInst &Inst, unsigned Opcode) {
- bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
- unsigned AddrBase = IsStore;
- unsigned RegOp = IsStore ? 0 : 5;
- unsigned AddrOp = AddrBase + 3;
- assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
- Inst.getOperand(AddrBase + 0).isReg() && // base
- Inst.getOperand(AddrBase + 1).isImm() && // scale
- Inst.getOperand(AddrBase + 2).isReg() && // index register
- (Inst.getOperand(AddrOp).isExpr() || // address
- Inst.getOperand(AddrOp).isImm())&&
- Inst.getOperand(AddrBase + 4).isReg() && // segment
- "Unexpected instruction!");
-
- // Check whether the destination register can be fixed.
- unsigned Reg = Inst.getOperand(RegOp).getReg();
- if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
- return;
-
- // Check whether this is an absolute address.
- // FIXME: We know TLVP symbol refs aren't, but there should be a better way
- // to do this here.
- bool Absolute = true;
- if (Inst.getOperand(AddrOp).isExpr()) {
- const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
- if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
- if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
- Absolute = false;
- }
-
- if (Absolute &&
- (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
- Inst.getOperand(AddrBase + 2).getReg() != 0 ||
- Inst.getOperand(AddrBase + 4).getReg() != 0 ||
- Inst.getOperand(AddrBase + 1).getImm() != 1))
- return;
-
- // If so, rewrite the instruction.
- MCOperand Saved = Inst.getOperand(AddrOp);
- Inst = MCInst();
- Inst.setOpcode(Opcode);
- Inst.addOperand(Saved);
-}
-
-void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
- OutMI.setOpcode(MI->getOpcode());
-
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
-
- MCOperand MCOp;
- switch (MO.getType()) {
- default:
- MI->dump();
- llvm_unreachable("unknown operand type");
- case MachineOperand::MO_Register:
- // Ignore all implicit register operands.
- if (MO.isImplicit()) continue;
- MCOp = MCOperand::CreateReg(MO.getReg());
- break;
- case MachineOperand::MO_Immediate:
- MCOp = MCOperand::CreateImm(MO.getImm());
- break;
- case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
- MO.getMBB()->getSymbol(), Ctx));
- break;
- case MachineOperand::MO_GlobalAddress:
- MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
- break;
- case MachineOperand::MO_ExternalSymbol:
- MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
- break;
- case MachineOperand::MO_JumpTableIndex:
- MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
- break;
- case MachineOperand::MO_BlockAddress:
- MCOp = LowerSymbolOperand(MO,
- AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
- break;
- }
-
- OutMI.addOperand(MCOp);
- }
-
- // Handle a few special cases to eliminate operand modifiers.
- switch (OutMI.getOpcode()) {
- case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
- lower_lea64_32mem(&OutMI, 1);
- // FALL THROUGH.
- case X86::LEA64r:
- case X86::LEA16r:
- case X86::LEA32r:
- // LEA should have a segment register, but it must be empty.
- assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
- "Unexpected # of LEA operands");
- assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
- "LEA has segment specified!");
- break;
- case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
- case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
- case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
- case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
- case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
- case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
- case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
- case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
- case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
- case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
- case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
- case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
- case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
- case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
- case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
- case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
- case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
- case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
- case X86::MMX_V_SETALLONES:
- LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
- case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
- case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
- case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
- case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
- case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
- case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
-
- case X86::MOV16r0:
- LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
- LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
- break;
- case X86::MOV64r0:
- LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
- LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
- break;
-
- // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have
- // register inputs modeled as normal uses instead of implicit uses. As such,
- // truncate off all but the first operand (the callee). FIXME: Change isel.
- case X86::TAILJMPr64:
- case X86::CALL64r:
- case X86::CALL64pcrel32: {
- unsigned Opcode = OutMI.getOpcode();
- MCOperand Saved = OutMI.getOperand(0);
- OutMI = MCInst();
- OutMI.setOpcode(Opcode);
- OutMI.addOperand(Saved);
- break;
- }
-
- // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
- case X86::TAILJMPr:
- case X86::TAILJMPd:
- case X86::TAILJMPd64: {
- unsigned Opcode;
- switch (OutMI.getOpcode()) {
- default: assert(0 && "Invalid opcode");
- case X86::TAILJMPr: Opcode = X86::JMP32r; break;
- case X86::TAILJMPd:
- case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
- }
-
- MCOperand Saved = OutMI.getOperand(0);
- OutMI = MCInst();
- OutMI.setOpcode(Opcode);
- OutMI.addOperand(Saved);
- break;
- }
-
- // The assembler backend wants to see branches in their small form and relax
- // them to their large form. The JIT can only handle the large form because
- // it does not do relaxation. For now, translate the large form to the
- // small one here.
- case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
- case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
- case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
- case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
- case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
- case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
- case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
- case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
- case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
- case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
- case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
- case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
- case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
- case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
- case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
- case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
- case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
-
- // We don't currently select the correct instruction form for instructions
- // which have a short %eax, etc. form. Handle this by custom lowering, for
- // now.
- //
- // Note, we are currently not handling the following instructions:
- // MOV64ao8, MOV64o8a
- // XCHG16ar, XCHG32ar, XCHG64ar
- case X86::MOV8mr_NOREX:
- case X86::MOV8mr: SimplifyShortMoveForm(OutMI, X86::MOV8ao8); break;
- case X86::MOV8rm_NOREX:
- case X86::MOV8rm: SimplifyShortMoveForm(OutMI, X86::MOV8o8a); break;
- case X86::MOV16mr: SimplifyShortMoveForm(OutMI, X86::MOV16ao16); break;
- case X86::MOV16rm: SimplifyShortMoveForm(OutMI, X86::MOV16o16a); break;
- case X86::MOV32mr: SimplifyShortMoveForm(OutMI, X86::MOV32ao32); break;
- case X86::MOV32rm: SimplifyShortMoveForm(OutMI, X86::MOV32o32a); break;
- case X86::MOV64mr: SimplifyShortMoveForm(OutMI, X86::MOV64ao64); break;
- case X86::MOV64rm: SimplifyShortMoveForm(OutMI, X86::MOV64o64a); break;
-
- case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
- case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
- case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
- case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
- case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
- case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
- case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
- case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
- case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
- case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
- case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
- case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
- case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
- case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
- case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
- case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
- case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
- case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
- case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
- case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
- case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
- case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
- case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
- case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
- case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
- case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
- case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
- case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
- case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
- case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
- case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
- case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
- case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
- case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
- case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
- case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
- }
-}
-
-void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
- raw_ostream &O) {
- // Only the target-dependent form of DBG_VALUE should get here.
- // Referencing the offset and metadata as NOps-2 and NOps-1 is
- // probably portable to other targets; frame pointer location is not.
- unsigned NOps = MI->getNumOperands();
- assert(NOps==7);
- O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
- // cast away const; DIetc do not take const operands for some reason.
- DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
- if (V.getContext().isSubprogram())
- O << DISubprogram(V.getContext()).getDisplayName() << ":";
- O << V.getName();
- O << " <- ";
- // Frame address. Currently handles register +- offset only.
- O << '[';
- if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg())
- printOperand(MI, 0, O);
- else
- O << "undef";
- O << '+'; printOperand(MI, 3, O);
- O << ']';
- O << "+";
- printOperand(MI, NOps-2, O);
-}
-
-MachineLocation
-X86AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
- MachineLocation Location;
- assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!");
- // Frame address. Currently handles register +- offset only.
-
- if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm())
- Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm());
- return Location;
-}
-
-
-void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
- X86MCInstLower MCInstLowering(OutContext, Mang, *this);
- switch (MI->getOpcode()) {
- case TargetOpcode::DBG_VALUE:
- if (isVerbose() && OutStreamer.hasRawTextSupport()) {
- std::string TmpStr;
- raw_string_ostream OS(TmpStr);
- PrintDebugValueComment(MI, OS);
- OutStreamer.EmitRawText(StringRef(OS.str()));
- }
- return;
-
- case X86::TAILJMPr:
- case X86::TAILJMPd:
- case X86::TAILJMPd64:
- // Lower these as normal, but add some comments.
- OutStreamer.AddComment("TAILCALL");
- break;
-
- case X86::MOVPC32r: {
- MCInst TmpInst;
- // This is a pseudo op for a two instruction sequence with a label, which
- // looks like:
- // call "L1$pb"
- // "L1$pb":
- // popl %esi
-
- // Emit the call.
- MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
- TmpInst.setOpcode(X86::CALLpcrel32);
- // FIXME: We would like an efficient form for this, so we don't have to do a
- // lot of extra uniquing.
- TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
- OutContext)));
- OutStreamer.EmitInstruction(TmpInst);
-
- // Emit the label.
- OutStreamer.EmitLabel(PICBase);
-
- // popl $reg
- TmpInst.setOpcode(X86::POP32r);
- TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
-
- case X86::ADD32ri: {
- // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
- if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
- break;
-
- // Okay, we have something like:
- // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
-
- // For this, we want to print something like:
- // MYGLOBAL + (. - PICBASE)
- // However, we can't generate a ".", so just emit a new label here and refer
- // to it.
- MCSymbol *DotSym = OutContext.CreateTempSymbol();
- OutStreamer.EmitLabel(DotSym);
-
- // Now that we have emitted the label, lower the complex operand expression.
- MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
-
- const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
- const MCExpr *PICBase =
- MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
- DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
-
- DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
- DotExpr, OutContext);
-
- MCInst TmpInst;
- TmpInst.setOpcode(X86::ADD32ri);
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
- TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
- TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
- OutStreamer.EmitInstruction(TmpInst);
- return;
- }
- }
-
- MCInst TmpInst;
- MCInstLowering.Lower(MI, TmpInst);
- OutStreamer.EmitInstruction(TmpInst);
-}
-
Removed: llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/AsmPrinter/X86MCInstLower.h (removed)
@@ -1,51 +0,0 @@
-//===-- X86MCInstLower.h - Lower MachineInstr to MCInst -------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef X86_MCINSTLOWER_H
-#define X86_MCINSTLOWER_H
-
-#include "llvm/Support/Compiler.h"
-
-namespace llvm {
- class MCContext;
- class MCInst;
- class MCOperand;
- class MCSymbol;
- class MachineInstr;
- class MachineModuleInfoMachO;
- class MachineOperand;
- class Mangler;
- class X86AsmPrinter;
- class X86Subtarget;
-
-/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
-class LLVM_LIBRARY_VISIBILITY X86MCInstLower {
- MCContext &Ctx;
- Mangler *Mang;
- X86AsmPrinter &AsmPrinter;
-
- const X86Subtarget &getSubtarget() const;
-public:
- X86MCInstLower(MCContext &ctx, Mangler *mang, X86AsmPrinter &asmprinter)
- : Ctx(ctx), Mang(mang), AsmPrinter(asmprinter) {}
-
- void Lower(const MachineInstr *MI, MCInst &OutMI) const;
-
- MCSymbol *GetPICBaseSymbol() const;
-
- MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
- MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
-
-private:
- MachineModuleInfoMachO &getMachOMMI() const;
-};
-
-}
-
-#endif
Modified: llvm/branches/wendling/eh/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -18,23 +18,24 @@
set(sources
SSEDomainFix.cpp
X86AsmBackend.cpp
- X86CodeEmitter.cpp
+ X86AsmPrinter.cpp
X86COFFMachineModuleInfo.cpp
+ X86CodeEmitter.cpp
X86ELFWriterInfo.cpp
+ X86FastISel.cpp
X86FloatingPoint.cpp
- X86FloatingPointRegKill.cpp
X86ISelDAGToDAG.cpp
X86ISelLowering.cpp
X86InstrInfo.cpp
X86JITInfo.cpp
X86MCAsmInfo.cpp
X86MCCodeEmitter.cpp
+ X86MCInstLower.cpp
X86RegisterInfo.cpp
+ X86SelectionDAGInfo.cpp
X86Subtarget.cpp
X86TargetMachine.cpp
X86TargetObjectFile.cpp
- X86FastISel.cpp
- X86SelectionDAGInfo.cpp
)
if( CMAKE_CL_64 )
@@ -49,4 +50,4 @@
add_llvm_target(X86CodeGen ${sources})
-target_link_libraries (LLVMX86CodeGen LLVMSelectionDAG)
+target_link_libraries (LLVMX86CodeGen LLVMX86AsmPrinter LLVMSelectionDAG)
Modified: llvm/branches/wendling/eh/lib/Target/X86/README-FPStack.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/README-FPStack.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/README-FPStack.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/README-FPStack.txt Sat Jul 31 19:59:02 2010
@@ -27,8 +27,8 @@
//===---------------------------------------------------------------------===//
-The FP stackifier needs to be global. Also, it should handle simple permutates
-to reduce number of shuffle instructions, e.g. turning:
+The FP stackifier should handle simple permutates to reduce number of shuffle
+instructions, e.g. turning:
fld P -> fld Q
fld Q fld P
Modified: llvm/branches/wendling/eh/lib/Target/X86/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/README.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/README.txt (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/README.txt Sat Jul 31 19:59:02 2010
@@ -1135,13 +1135,6 @@
//===---------------------------------------------------------------------===//
-handling llvm.memory.barrier on pre SSE2 cpus
-
-should generate:
-lock ; mov %esp, %esp
-
-//===---------------------------------------------------------------------===//
-
The generated code on x86 for checking for signed overflow on a multiply the
obvious way is much longer than it needs to be.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86.h Sat Jul 31 19:59:02 2010
@@ -49,11 +49,6 @@
/// crossings.
FunctionPass *createSSEDomainFixPass();
-/// createX87FPRegKillInserterPass - This function returns a pass which
-/// inserts FP_REG_KILL instructions where needed.
-///
-FunctionPass *createX87FPRegKillInserterPass();
-
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86.td Sat Jul 31 19:59:02 2010
@@ -67,6 +67,8 @@
def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
"Enable AVX instructions">;
+def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",
+ "Enable carry-less multiplication instructions">;
def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
"Enable three-operand fused multiple-add">;
def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
@@ -180,7 +182,6 @@
// Currently the X86 assembly parser only supports ATT syntax.
def ATTAsmParser : AsmParser {
string AsmParserClassName = "ATTAsmParser";
- string AsmParserInstCleanup = "InstructionCleanup";
string MatchInstructionName = "MatchInstructionImpl";
int Variant = 0;
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86AsmBackend.cpp Sat Jul 31 19:59:02 2010
@@ -14,6 +14,7 @@
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSectionCOFF.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MachObjectWriter.h"
@@ -212,6 +213,23 @@
: ELFX86AsmBackend(T) {}
};
+class WindowsX86AsmBackend : public X86AsmBackend {
+public:
+ WindowsX86AsmBackend(const Target &T)
+ : X86AsmBackend(T) {
+ HasScatteredSymbols = true;
+ }
+
+ MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+ return createWinCOFFObjectWriter (OS);
+ }
+
+ bool isVirtualSection(const MCSection &Section) const {
+ const MCSectionCOFF &SE = static_cast<const MCSectionCOFF&>(Section);
+ return SE.getCharacteristics() & COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA;
+ }
+};
+
class DarwinX86AsmBackend : public X86AsmBackend {
public:
DarwinX86AsmBackend(const Target &T)
@@ -290,6 +308,8 @@
switch (Triple(TT).getOS()) {
case Triple::Darwin:
return new DarwinX86_32AsmBackend(T);
+ case Triple::Win32:
+ return new WindowsX86AsmBackend(T);
default:
return new ELFX86_32AsmBackend(T);
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86CodeEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86CodeEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -146,6 +146,103 @@
return false;
}
+/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
+/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
+/// size, and 3) use of X86-64 extended registers.
+static unsigned determineREX(const MachineInstr &MI) {
+ unsigned REX = 0;
+ const TargetInstrDesc &Desc = MI.getDesc();
+
+ // Pseudo instructions do not need REX prefix byte.
+ if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
+ return 0;
+ if (Desc.TSFlags & X86II::REX_W)
+ REX |= 1 << 3;
+
+ unsigned NumOps = Desc.getNumOperands();
+ if (NumOps) {
+ bool isTwoAddr = NumOps > 1 &&
+ Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
+
+ // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
+ unsigned i = isTwoAddr ? 1 : 0;
+ for (unsigned e = NumOps; i != e; ++i) {
+ const MachineOperand& MO = MI.getOperand(i);
+ if (MO.isReg()) {
+ unsigned Reg = MO.getReg();
+ if (X86InstrInfo::isX86_64NonExtLowByteReg(Reg))
+ REX |= 0x40;
+ }
+ }
+
+ switch (Desc.TSFlags & X86II::FormMask) {
+ case X86II::MRMInitReg:
+ if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
+ REX |= (1 << 0) | (1 << 2);
+ break;
+ case X86II::MRMSrcReg: {
+ if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
+ REX |= 1 << 2;
+ i = isTwoAddr ? 2 : 1;
+ for (unsigned e = NumOps; i != e; ++i) {
+ const MachineOperand& MO = MI.getOperand(i);
+ if (X86InstrInfo::isX86_64ExtendedReg(MO))
+ REX |= 1 << 0;
+ }
+ break;
+ }
+ case X86II::MRMSrcMem: {
+ if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
+ REX |= 1 << 2;
+ unsigned Bit = 0;
+ i = isTwoAddr ? 2 : 1;
+ for (; i != NumOps; ++i) {
+ const MachineOperand& MO = MI.getOperand(i);
+ if (MO.isReg()) {
+ if (X86InstrInfo::isX86_64ExtendedReg(MO))
+ REX |= 1 << Bit;
+ Bit++;
+ }
+ }
+ break;
+ }
+ case X86II::MRM0m: case X86II::MRM1m:
+ case X86II::MRM2m: case X86II::MRM3m:
+ case X86II::MRM4m: case X86II::MRM5m:
+ case X86II::MRM6m: case X86II::MRM7m:
+ case X86II::MRMDestMem: {
+ unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
+ i = isTwoAddr ? 1 : 0;
+ if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
+ REX |= 1 << 2;
+ unsigned Bit = 0;
+ for (; i != e; ++i) {
+ const MachineOperand& MO = MI.getOperand(i);
+ if (MO.isReg()) {
+ if (X86InstrInfo::isX86_64ExtendedReg(MO))
+ REX |= 1 << Bit;
+ Bit++;
+ }
+ }
+ break;
+ }
+ default: {
+ if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
+ REX |= 1 << 0;
+ i = isTwoAddr ? 2 : 1;
+ for (unsigned e = NumOps; i != e; ++i) {
+ const MachineOperand& MO = MI.getOperand(i);
+ if (X86InstrInfo::isX86_64ExtendedReg(MO))
+ REX |= 1 << 2;
+ }
+ break;
+ }
+ }
+ }
+ return REX;
+}
+
+
/// emitPCRelativeBlockAddress - This method keeps track of the information
/// necessary to resolve the address of this block later and emits a dummy
/// value.
@@ -569,7 +666,7 @@
// Handle REX prefix.
if (Is64BitMode) {
- if (unsigned REX = X86InstrInfo::determineREX(MI))
+ if (unsigned REX = determineREX(MI))
MCE.emitByte(0x40 | REX);
}
@@ -614,7 +711,7 @@
if (MI.getOperand(0).getSymbolName()[0])
report_fatal_error("JIT does not support inline asm!");
break;
- case TargetOpcode::DBG_LABEL:
+ case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::GC_LABEL:
case TargetOpcode::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getMCSymbol());
@@ -622,7 +719,6 @@
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
- case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {
// This emits the "call" portion of this pseudo instruction.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86FastISel.cpp Sat Jul 31 19:59:02 2010
@@ -1058,10 +1058,8 @@
const MachineInstr &MI = *RI;
if (MI.definesRegister(Reg)) {
- unsigned Src, Dst, SrcSR, DstSR;
-
- if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
- Reg = Src;
+ if (MI.isCopy()) {
+ Reg = MI.getOperand(1).getReg();
continue;
}
@@ -1648,15 +1646,26 @@
MachineInstrBuilder MIB;
if (CalleeOp) {
// Register-indirect call.
- unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
+ unsigned CallOpc;
+ if (Subtarget->isTargetWin64())
+ CallOpc = X86::WINCALL64r;
+ else if (Subtarget->is64Bit())
+ CallOpc = X86::CALL64r;
+ else
+ CallOpc = X86::CALL32r;
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
.addReg(CalleeOp);
} else {
// Direct call.
assert(GV && "Not a direct call");
- unsigned CallOpc =
- Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
+ unsigned CallOpc;
+ if (Subtarget->isTargetWin64())
+ CallOpc = X86::WINCALL64pcrel32;
+ else if (Subtarget->is64Bit())
+ CallOpc = X86::CALL64pcrel32;
+ else
+ CallOpc = X86::CALLpcrel32;
// See if we need any target-specific flags on the GV operand.
unsigned char OpFlags = 0;
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPoint.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPoint.cpp Sat Jul 31 19:59:02 2010
@@ -8,23 +8,18 @@
//===----------------------------------------------------------------------===//
//
// This file defines the pass which converts floating point instructions from
-// virtual registers into register stack instructions. This pass uses live
+// pseudo registers into register stack instructions. This pass uses live
// variable information to indicate where the FPn registers are used and their
// lifetimes.
//
-// This pass is hampered by the lack of decent CFG manipulation routines for
-// machine code. In particular, this wants to be able to split critical edges
-// as necessary, traverse the machine basic block CFG in depth-first order, and
-// allow there to be multiple machine basic blocks for each LLVM basicblock
-// (needed for critical edge splitting).
+// The x87 hardware tracks liveness of the stack registers, so it is necessary
+// to implement exact liveness tracking between basic blocks. The CFG edges are
+// partitioned into bundles where the same FP registers must be live in
+// identical stack positions. Instructions are inserted at the end of each basic
+// block to rearrange the live registers to match the outgoing bundle.
//
-// In particular, this pass currently barfs on critical edges. Because of this,
-// it requires the instruction selector to insert FP_REG_KILL instructions on
-// the exits of any basic block that has critical edges going from it, or which
-// branch to a critical basic block.
-//
-// FIXME: this is not implemented yet. The stackifier pass only works on local
-// basic blocks.
+// This approach avoids splitting critical edges at the potential cost of more
+// live register shuffling instructions when critical edges are present.
//
//===----------------------------------------------------------------------===//
@@ -32,6 +27,7 @@
#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/ADT/DepthFirstIterator.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
@@ -54,7 +50,12 @@
namespace {
struct FPS : public MachineFunctionPass {
static char ID;
- FPS() : MachineFunctionPass(&ID) {}
+ FPS() : MachineFunctionPass(&ID) {
+ // This is really only to keep valgrind quiet.
+ // The logic in isLive() is too much for it.
+ memset(Stack, 0, sizeof(Stack));
+ memset(RegMap, 0, sizeof(RegMap));
+ }
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@@ -69,11 +70,71 @@
private:
const TargetInstrInfo *TII; // Machine instruction info.
+
+ // Two CFG edges are related if they leave the same block, or enter the same
+ // block. The transitive closure of an edge under this relation is a
+ // LiveBundle. It represents a set of CFG edges where the live FP stack
+ // registers must be allocated identically in the x87 stack.
+ //
+ // A LiveBundle is usually all the edges leaving a block, or all the edges
+ // entering a block, but it can contain more edges if critical edges are
+ // present.
+ //
+ // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
+ // but the exact mapping of FP registers to stack slots is fixed later.
+ struct LiveBundle {
+ // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
+ unsigned Mask;
+
+ // Number of pre-assigned live registers in FixStack. This is 0 when the
+ // stack order has not yet been fixed.
+ unsigned FixCount;
+
+ // Assigned stack order for live-in registers.
+ // FixStack[i] == getStackEntry(i) for all i < FixCount.
+ unsigned char FixStack[8];
+
+ LiveBundle(unsigned m = 0) : Mask(m), FixCount(0) {}
+
+ // Have the live registers been assigned a stack order yet?
+ bool isFixed() const { return !Mask || FixCount; }
+ };
+
+ // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
+ // with no live FP registers.
+ SmallVector<LiveBundle, 8> LiveBundles;
+
+ // Map each MBB in the current function to an (ingoing, outgoing) index into
+ // LiveBundles. Blocks with no FP registers live in or out map to (0, 0)
+ // and are not actually stored in the map.
+ DenseMap<MachineBasicBlock*, std::pair<unsigned, unsigned> > BlockBundle;
+
+ // Return a bitmask of FP registers in block's live-in list.
+ unsigned calcLiveInMask(MachineBasicBlock *MBB) {
+ unsigned Mask = 0;
+ for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
+ E = MBB->livein_end(); I != E; ++I) {
+ unsigned Reg = *I - X86::FP0;
+ if (Reg < 8)
+ Mask |= 1 << Reg;
+ }
+ return Mask;
+ }
+
+ // Partition all the CFG edges into LiveBundles.
+ void bundleCFG(MachineFunction &MF);
+
MachineBasicBlock *MBB; // Current basic block
unsigned Stack[8]; // FP<n> Registers in each stack slot...
unsigned RegMap[8]; // Track which stack slot contains each register
unsigned StackTop; // The current top of the FP stack.
+ // Set up our stack model to match the incoming registers to MBB.
+ void setupBlockStack();
+
+ // Shuffle live registers to match the expectations of successor blocks.
+ void finishBlockStack();
+
void dumpStack() const {
dbgs() << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
@@ -82,27 +143,41 @@
}
dbgs() << "\n";
}
- private:
+
/// isStackEmpty - Return true if the FP stack is empty.
bool isStackEmpty() const {
return StackTop == 0;
}
-
- // getSlot - Return the stack slot number a particular register number is
- // in.
+
+ /// getSlot - Return the stack slot number a particular register number is
+ /// in.
unsigned getSlot(unsigned RegNo) const {
assert(RegNo < 8 && "Regno out of range!");
return RegMap[RegNo];
}
- // getStackEntry - Return the X86::FP<n> register in register ST(i).
+ /// isLive - Is RegNo currently live in the stack?
+ bool isLive(unsigned RegNo) const {
+ unsigned Slot = getSlot(RegNo);
+ return Slot < StackTop && Stack[Slot] == RegNo;
+ }
+
+ /// getScratchReg - Return an FP register that is not currently in use.
+ unsigned getScratchReg() {
+ for (int i = 7; i >= 0; --i)
+ if (!isLive(i))
+ return i;
+ llvm_unreachable("Ran out of scratch FP registers");
+ }
+
+ /// getStackEntry - Return the X86::FP<n> register in register ST(i).
unsigned getStackEntry(unsigned STi) const {
assert(STi < StackTop && "Access past stack top!");
return Stack[StackTop-1-STi];
}
- // getSTReg - Return the X86::ST(i) register which contains the specified
- // FP<RegNo> register.
+ /// getSTReg - Return the X86::ST(i) register which contains the specified
+ /// FP<RegNo> register.
unsigned getSTReg(unsigned RegNo) const {
return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
}
@@ -117,10 +192,9 @@
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
- MachineInstr *MI = I;
- DebugLoc dl = MI->getDebugLoc();
+ DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
if (isAtTop(RegNo)) return;
-
+
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
@@ -137,24 +211,37 @@
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
- DebugLoc dl = I->getDebugLoc();
+ DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
}
- // popStackAfter - Pop the current value off of the top of the FP stack
- // after the specified instruction.
+ /// popStackAfter - Pop the current value off of the top of the FP stack
+ /// after the specified instruction.
void popStackAfter(MachineBasicBlock::iterator &I);
- // freeStackSlotAfter - Free the specified register from the register stack,
- // so that it is no longer in a register. If the register is currently at
- // the top of the stack, we just pop the current instruction, otherwise we
- // store the current top-of-stack into the specified slot, then pop the top
- // of stack.
+ /// freeStackSlotAfter - Free the specified register from the register
+ /// stack, so that it is no longer in a register. If the register is
+ /// currently at the top of the stack, we just pop the current instruction,
+ /// otherwise we store the current top-of-stack into the specified slot,
+ /// then pop the top of stack.
void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
+ /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
+ /// instruction.
+ MachineBasicBlock::iterator
+ freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
+
+ /// Adjust the live registers to be the set in Mask.
+ void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
+
+ /// Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is
+ /// st(0), FP reg FixStack[1] is st(1) etc.
+ void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
+ MachineBasicBlock::iterator I);
+
bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
void handleZeroArgFP(MachineBasicBlock::iterator &I);
@@ -181,7 +268,6 @@
return Reg - X86::FP0;
}
-
/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
/// register references into FP stack references.
///
@@ -201,6 +287,10 @@
if (!FPIsUsed) return false;
TII = MF.getTarget().getInstrInfo();
+
+ // Prepare cross-MBB liveness.
+ bundleCFG(MF);
+
StackTop = 0;
// Process the function in depth first order so that we process at least one
@@ -215,16 +305,111 @@
Changed |= processBasicBlock(MF, **I);
// Process any unreachable blocks in arbitrary order now.
- if (MF.size() == Processed.size())
- return Changed;
+ if (MF.size() != Processed.size())
+ for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
+ if (Processed.insert(BB))
+ Changed |= processBasicBlock(MF, *BB);
+
+ BlockBundle.clear();
+ LiveBundles.clear();
- for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
- if (Processed.insert(BB))
- Changed |= processBasicBlock(MF, *BB);
-
return Changed;
}
+/// bundleCFG - Scan all the basic blocks to determine consistent live-in and
+/// live-out sets for the FP registers. Consistent means that the set of
+/// registers live-out from a block is identical to the live-in set of all
+/// successors. This is not enforced by the normal live-in lists since
+/// registers may be implicitly defined, or not used by all successors.
+void FPS::bundleCFG(MachineFunction &MF) {
+ assert(LiveBundles.empty() && "Stale data in LiveBundles");
+ assert(BlockBundle.empty() && "Stale data in BlockBundle");
+ SmallPtrSet<MachineBasicBlock*, 8> PropDown, PropUp;
+
+ // LiveBundle[0] is the empty live-in set.
+ LiveBundles.resize(1);
+
+ // First gather the actual live-in masks for all MBBs.
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
+ MachineBasicBlock *MBB = I;
+ const unsigned Mask = calcLiveInMask(MBB);
+ if (!Mask)
+ continue;
+ // Ingoing bundle index.
+ unsigned &Idx = BlockBundle[MBB].first;
+ // Already assigned an ingoing bundle?
+ if (Idx)
+ continue;
+ // Allocate a new LiveBundle struct for this block's live-ins.
+ const unsigned BundleIdx = Idx = LiveBundles.size();
+ DEBUG(dbgs() << "Creating LB#" << BundleIdx << ": in:BB#"
+ << MBB->getNumber());
+ LiveBundles.push_back(Mask);
+ LiveBundle &Bundle = LiveBundles.back();
+
+ // Make sure all predecessors have the same live-out set.
+ PropUp.insert(MBB);
+
+ // Keep pushing liveness up and down the CFG until convergence.
+ // Only critical edges cause iteration here, but when they do, multiple
+ // blocks can be assigned to the same LiveBundle index.
+ do {
+ // Assign BundleIdx as liveout from predecessors in PropUp.
+ for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropUp.begin(),
+ E = PropUp.end(); I != E; ++I) {
+ MachineBasicBlock *MBB = *I;
+ for (MachineBasicBlock::const_pred_iterator LinkI = MBB->pred_begin(),
+ LinkE = MBB->pred_end(); LinkI != LinkE; ++LinkI) {
+ MachineBasicBlock *PredMBB = *LinkI;
+ // PredMBB's liveout bundle should be set to LIIdx.
+ unsigned &Idx = BlockBundle[PredMBB].second;
+ if (Idx) {
+ assert(Idx == BundleIdx && "Inconsistent CFG");
+ continue;
+ }
+ Idx = BundleIdx;
+ DEBUG(dbgs() << " out:BB#" << PredMBB->getNumber());
+ // Propagate to siblings.
+ if (PredMBB->succ_size() > 1)
+ PropDown.insert(PredMBB);
+ }
+ }
+ PropUp.clear();
+
+ // Assign BundleIdx as livein to successors in PropDown.
+ for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropDown.begin(),
+ E = PropDown.end(); I != E; ++I) {
+ MachineBasicBlock *MBB = *I;
+ for (MachineBasicBlock::const_succ_iterator LinkI = MBB->succ_begin(),
+ LinkE = MBB->succ_end(); LinkI != LinkE; ++LinkI) {
+ MachineBasicBlock *SuccMBB = *LinkI;
+ // LinkMBB's livein bundle should be set to BundleIdx.
+ unsigned &Idx = BlockBundle[SuccMBB].first;
+ if (Idx) {
+ assert(Idx == BundleIdx && "Inconsistent CFG");
+ continue;
+ }
+ Idx = BundleIdx;
+ DEBUG(dbgs() << " in:BB#" << SuccMBB->getNumber());
+ // Propagate to siblings.
+ if (SuccMBB->pred_size() > 1)
+ PropUp.insert(SuccMBB);
+ // Also accumulate the bundle liveness mask from the liveins here.
+ Bundle.Mask |= calcLiveInMask(SuccMBB);
+ }
+ }
+ PropDown.clear();
+ } while (!PropUp.empty());
+ DEBUG({
+ dbgs() << " live:";
+ for (unsigned i = 0; i < 8; ++i)
+ if (Bundle.Mask & (1<<i))
+ dbgs() << " %FP" << i;
+ dbgs() << '\n';
+ });
+ }
+}
+
/// processBasicBlock - Loop over all of the instructions in the basic block,
/// transforming FP instructions into their stack form.
///
@@ -232,10 +417,12 @@
bool Changed = false;
MBB = &BB;
+ setupBlockStack();
+
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
uint64_t Flags = MI->getDesc().TSFlags;
-
+
unsigned FPInstClass = Flags & X86II::FPTypeMask;
if (MI->isInlineAsm())
FPInstClass = X86II::SpecialFP;
@@ -302,10 +489,82 @@
Changed = true;
}
- assert(isStackEmpty() && "Stack not empty at end of basic block?");
+ finishBlockStack();
+
return Changed;
}
+/// setupBlockStack - Use the BlockBundle map to set up our model of the stack
+/// to match predecessors' live out stack.
+void FPS::setupBlockStack() {
+ DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
+ << " derived from " << MBB->getName() << ".\n");
+ StackTop = 0;
+ const LiveBundle &Bundle = LiveBundles[BlockBundle.lookup(MBB).first];
+
+ if (!Bundle.Mask) {
+ DEBUG(dbgs() << "Block has no FP live-ins.\n");
+ return;
+ }
+
+ // Depth-first iteration should ensure that we always have an assigned stack.
+ assert(Bundle.isFixed() && "Reached block before any predecessors");
+
+ // Push the fixed live-in registers.
+ for (unsigned i = Bundle.FixCount; i > 0; --i) {
+ MBB->addLiveIn(X86::ST0+i-1);
+ DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
+ << unsigned(Bundle.FixStack[i-1]) << '\n');
+ pushReg(Bundle.FixStack[i-1]);
+ }
+
+ // Kill off unwanted live-ins. This can happen with a critical edge.
+ // FIXME: We could keep these live registers around as zombies. They may need
+ // to be revived at the end of a short block. It might save a few instrs.
+ adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
+ DEBUG(MBB->dump());
+}
+
+/// finishBlockStack - Revive live-outs that are implicitly defined out of
+/// MBB. Shuffle live registers to match the expected fixed stack of any
+/// predecessors, and ensure that all predecessors are expecting the same
+/// stack.
+void FPS::finishBlockStack() {
+ // The RET handling below takes care of return blocks for us.
+ if (MBB->succ_empty())
+ return;
+
+ DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
+ << " derived from " << MBB->getName() << ".\n");
+
+ unsigned BundleIdx = BlockBundle.lookup(MBB).second;
+ LiveBundle &Bundle = LiveBundles[BundleIdx];
+
+ // We may need to kill and define some registers to match successors.
+ // FIXME: This can probably be combined with the shuffle below.
+ MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
+ adjustLiveRegs(Bundle.Mask, Term);
+
+ if (!Bundle.Mask) {
+ DEBUG(dbgs() << "No live-outs.\n");
+ return;
+ }
+
+ // Has the stack order been fixed yet?
+ DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
+ if (Bundle.isFixed()) {
+ DEBUG(dbgs() << "Shuffling stack to match.\n");
+ shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
+ } else {
+ // Not fixed yet, we get to choose.
+ DEBUG(dbgs() << "Fixing stack order now.\n");
+ Bundle.FixCount = StackTop;
+ for (unsigned i = 0; i < StackTop; ++i)
+ Bundle.FixStack[i] = getStackEntry(i);
+ }
+}
+
+
//===----------------------------------------------------------------------===//
// Efficient Lookup Table Support
//===----------------------------------------------------------------------===//
@@ -597,6 +856,13 @@
// Otherwise, store the top of stack into the dead slot, killing the operand
// without having to add in an explicit xchg then pop.
//
+ I = freeStackSlotBefore(++I, FPRegNo);
+}
+
+/// freeStackSlotBefore - Free the specified register without trying any
+/// folding.
+MachineBasicBlock::iterator
+FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
unsigned STReg = getSTReg(FPRegNo);
unsigned OldSlot = getSlot(FPRegNo);
unsigned TopReg = Stack[StackTop-1];
@@ -604,9 +870,90 @@
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
- MachineInstr *MI = I;
- DebugLoc dl = MI->getDebugLoc();
- I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
+ return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg);
+}
+
+/// adjustLiveRegs - Kill and revive registers such that exactly the FP
+/// registers with a bit in Mask are live.
+void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
+ unsigned Defs = Mask;
+ unsigned Kills = 0;
+ for (unsigned i = 0; i < StackTop; ++i) {
+ unsigned RegNo = Stack[i];
+ if (!(Defs & (1 << RegNo)))
+ // This register is live, but we don't want it.
+ Kills |= (1 << RegNo);
+ else
+ // We don't need to imp-def this live register.
+ Defs &= ~(1 << RegNo);
+ }
+ assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
+
+ // Produce implicit-defs for free by using killed registers.
+ while (Kills && Defs) {
+ unsigned KReg = CountTrailingZeros_32(Kills);
+ unsigned DReg = CountTrailingZeros_32(Defs);
+ DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
+ std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
+ std::swap(RegMap[KReg], RegMap[DReg]);
+ Kills &= ~(1 << KReg);
+ Defs &= ~(1 << DReg);
+ }
+
+ // Kill registers by popping.
+ if (Kills && I != MBB->begin()) {
+ MachineBasicBlock::iterator I2 = llvm::prior(I);
+ for (;;) {
+ unsigned KReg = getStackEntry(0);
+ if (!(Kills & (1 << KReg)))
+ break;
+ DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
+ popStackAfter(I2);
+ Kills &= ~(1 << KReg);
+ }
+ }
+
+ // Manually kill the rest.
+ while (Kills) {
+ unsigned KReg = CountTrailingZeros_32(Kills);
+ DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
+ freeStackSlotBefore(I, KReg);
+ Kills &= ~(1 << KReg);
+ }
+
+ // Load zeros for all the imp-defs.
+ while(Defs) {
+ unsigned DReg = CountTrailingZeros_32(Defs);
+ DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
+ BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
+ pushReg(DReg);
+ Defs &= ~(1 << DReg);
+ }
+
+ // Now we should have the correct registers live.
+ DEBUG(dumpStack());
+ assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch");
+}
+
+/// shuffleStackTop - emit fxch instructions before I to shuffle the top
+/// FixCount entries into the order given by FixStack.
+/// FIXME: Is there a better algorithm than insertion sort?
+void FPS::shuffleStackTop(const unsigned char *FixStack,
+ unsigned FixCount,
+ MachineBasicBlock::iterator I) {
+ // Move items into place, starting from the desired stack bottom.
+ while (FixCount--) {
+ // Old register at position FixCount.
+ unsigned OldReg = getStackEntry(FixCount);
+ // Desired register at position FixCount.
+ unsigned Reg = FixStack[FixCount];
+ if (Reg == OldReg)
+ continue;
+ // (Reg st0) (OldReg st0) = (Reg OldReg st0)
+ moveToTop(Reg, I);
+ moveToTop(OldReg, I);
+ }
+ DEBUG(dumpStack());
}
@@ -660,7 +1007,7 @@
MI->getOpcode() == X86::ISTT_Fp32m80 ||
MI->getOpcode() == X86::ISTT_Fp64m80 ||
MI->getOpcode() == X86::ST_FpP80m)) {
- duplicateToTop(Reg, 7 /*temp register*/, I);
+ duplicateToTop(Reg, getScratchReg(), I);
} else {
moveToTop(Reg, I); // Move to the top of the stack...
}
@@ -1013,8 +1360,7 @@
if (!MI->killsRegister(X86::FP0 + Op0)) {
// Duplicate Op0 into a temporary on the stack top.
- // This actually assumes that FP7 is dead.
- duplicateToTop(Op0, 7, I);
+ duplicateToTop(Op0, getScratchReg(), I);
} else {
// Op0 is killed, so just swap it into position.
moveToTop(Op0, I);
@@ -1034,8 +1380,7 @@
++StackTop;
unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0).
if (!MI->killsRegister(X86::FP0 + Op0)) {
- // Assume FP6 is not live, use it as a scratch register.
- duplicateToTop(Op0, 6, I);
+ duplicateToTop(Op0, getScratchReg(), I);
moveToTop(RegOnTop, I);
} else if (getSTReg(Op0) != X86::ST1) {
// We have the wrong value at st(1). Shuffle! Untested!
@@ -1119,11 +1464,11 @@
case X86::RETI:
// If RET has an FP register use operand, pass the first one in ST(0) and
// the second one in ST(1).
- if (isStackEmpty()) return; // Quick check to see if any are possible.
-
+
// Find the register operands.
unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
-
+ unsigned LiveMask = 0;
+
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
@@ -1142,12 +1487,18 @@
assert(SecondFPRegOp == ~0U && "More than two fp operands!");
SecondFPRegOp = getFPReg(Op);
}
+ LiveMask |= (1 << getFPReg(Op));
// Remove the operand so that later passes don't see it.
MI->RemoveOperand(i);
--i, --e;
}
-
+
+ // We may have been carrying spurious live-ins, so make sure only the returned
+ // registers are left live.
+ adjustLiveRegs(LiveMask, MI);
+ if (!LiveMask) return; // Quick check to see if any are possible.
+
// There are only four possibilities here:
// 1) we are returning a single FP value. In this case, it has to be in
// ST(0) already, so just declare success by removing the value from the
@@ -1173,7 +1524,7 @@
// Duplicate the TOS so that we return it twice. Just pick some other FPx
// register to hold it.
- unsigned NewReg = (FirstFPRegOp+1)%7;
+ unsigned NewReg = getScratchReg();
duplicateToTop(FirstFPRegOp, NewReg, MI);
FirstFPRegOp = NewReg;
}
@@ -1197,7 +1548,14 @@
}
I = MBB->erase(I); // Remove the pseudo instruction
- --I;
+
+ // We want to leave I pointing to the previous instruction, but what if we
+ // just erased the first instruction?
+ if (I == MBB->begin()) {
+ DEBUG(dbgs() << "Inserting dummy KILL\n");
+ I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL));
+ } else
+ --I;
}
// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.
Removed: llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPointRegKill.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPointRegKill.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPointRegKill.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86FloatingPointRegKill.cpp (removed)
@@ -1,153 +0,0 @@
-//===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the pass which inserts FP_REG_KILL instructions.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "x86-codegen"
-#include "X86.h"
-#include "X86InstrInfo.h"
-#include "llvm/Instructions.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/CFG.h"
-#include "llvm/ADT/Statistic.h"
-using namespace llvm;
-
-STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added");
-
-namespace {
- struct FPRegKiller : public MachineFunctionPass {
- static char ID;
- FPRegKiller() : MachineFunctionPass(&ID) {}
-
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.setPreservesCFG();
- AU.addPreservedID(MachineLoopInfoID);
- AU.addPreservedID(MachineDominatorsID);
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
- virtual const char *getPassName() const {
- return "X86 FP_REG_KILL inserter";
- }
- };
- char FPRegKiller::ID = 0;
-}
-
-FunctionPass *llvm::createX87FPRegKillInserterPass() {
- return new FPRegKiller();
-}
-
-/// isFPStackVReg - Return true if the specified vreg is from a fp stack
-/// register class.
-static bool isFPStackVReg(unsigned RegNo, const MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(RegNo))
- return false;
-
- switch (MRI.getRegClass(RegNo)->getID()) {
- default: return false;
- case X86::RFP32RegClassID:
- case X86::RFP64RegClassID:
- case X86::RFP80RegClassID:
- return true;
- }
-}
-
-
-/// ContainsFPStackCode - Return true if the specific MBB has floating point
-/// stack code, and thus needs an FP_REG_KILL.
-static bool ContainsFPStackCode(MachineBasicBlock *MBB,
- const MachineRegisterInfo &MRI) {
- // Scan the block, looking for instructions that define or use fp stack vregs.
- for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
- I != E; ++I) {
- for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
- if (!I->getOperand(op).isReg())
- continue;
- if (unsigned Reg = I->getOperand(op).getReg())
- if (isFPStackVReg(Reg, MRI))
- return true;
- }
- }
-
- // Check PHI nodes in successor blocks. These PHI's will be lowered to have
- // a copy of the input value in this block, which is a definition of the
- // value.
- for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
- E = MBB->succ_end(); SI != E; ++ SI) {
- MachineBasicBlock *SuccBB = *SI;
- for (MachineBasicBlock::iterator I = SuccBB->begin(), E = SuccBB->end();
- I != E; ++I) {
- // All PHI nodes are at the top of the block.
- if (!I->isPHI()) break;
-
- if (isFPStackVReg(I->getOperand(0).getReg(), MRI))
- return true;
- }
- }
-
- return false;
-}
-
-bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) {
- // If we are emitting FP stack code, scan the basic block to determine if this
- // block defines or uses any FP values. If so, put an FP_REG_KILL instruction
- // before the terminator of the block.
-
- // Note that FP stack instructions are used in all modes for long double,
- // so we always need to do this check.
- // Also note that it's possible for an FP stack register to be live across
- // an instruction that produces multiple basic blocks (SSE CMOV) so we
- // must check all the generated basic blocks.
-
- // Scan all of the machine instructions in these MBBs, checking for FP
- // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
-
- // Fast-path: If nothing is using the x87 registers, we don't need to do
- // any scanning.
- const MachineRegisterInfo &MRI = MF.getRegInfo();
- if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() &&
- MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() &&
- MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty())
- return false;
-
- bool Changed = false;
- MachineFunction::iterator MBBI = MF.begin();
- MachineFunction::iterator EndMBB = MF.end();
- for (; MBBI != EndMBB; ++MBBI) {
- MachineBasicBlock *MBB = MBBI;
-
- // If this block returns, ignore it. We don't want to insert an FP_REG_KILL
- // before the return.
- if (!MBB->empty()) {
- MachineBasicBlock::iterator EndI = MBB->end();
- --EndI;
- if (EndI->getDesc().isReturn())
- continue;
- }
-
- // If we find any FP stack code, emit the FP_REG_KILL instruction.
- if (ContainsFPStackCode(MBB, MRI)) {
- BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(),
- MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL));
- ++NumFPKill;
- Changed = true;
- }
- }
-
- return Changed;
-}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.cpp Sat Jul 31 19:59:02 2010
@@ -343,8 +343,9 @@
if (Subtarget->hasSSE1())
setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
- if (!Subtarget->hasSSE2())
- setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
+ // We may not have a libcall for MEMBARRIER so we should lower this.
+ setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
+
// On X86 and X86-64, atomic operations are lowered to locked instructions.
// Locked instructions, in turn, have implicit fence semantics (all memory
// operations are flushed before issuing the locked instruction, and they
@@ -837,6 +838,10 @@
// FIXME: Do we need to handle scalar-to-vector here?
setOperationAction(ISD::MUL, MVT::v4i32, Legal);
+ // Can turn SHL into an integer multiply.
+ setOperationAction(ISD::SHL, MVT::v4i32, Custom);
+ setOperationAction(ISD::SHL, MVT::v16i8, Custom);
+
// i8 and i16 vectors are custom , because the source register and source
// source memory operand types are not the same width. f32 vectors are
// custom since the immediate controlling the insert encodes additional
@@ -1189,6 +1194,50 @@
return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
}
+std::pair<const TargetRegisterClass*, uint8_t>
+X86TargetLowering::findRepresentativeClass(EVT VT) const{
+ const TargetRegisterClass *RRC = 0;
+ uint8_t Cost = 1;
+ switch (VT.getSimpleVT().SimpleTy) {
+ default:
+ return TargetLowering::findRepresentativeClass(VT);
+ case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
+ RRC = (Subtarget->is64Bit()
+ ? X86::GR64RegisterClass : X86::GR32RegisterClass);
+ break;
+ case MVT::v8i8: case MVT::v4i16:
+ case MVT::v2i32: case MVT::v1i64:
+ RRC = X86::VR64RegisterClass;
+ break;
+ case MVT::f32: case MVT::f64:
+ case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
+ case MVT::v4f32: case MVT::v2f64:
+ case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
+ case MVT::v4f64:
+ RRC = X86::VR128RegisterClass;
+ break;
+ }
+ return std::make_pair(RRC, Cost);
+}
+
+unsigned
+X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
+ switch (RC->getID()) {
+ default:
+ return 0;
+ case X86::GR32RegClassID:
+ return 4 - FPDiff;
+ case X86::GR64RegClassID:
+ return 8 - FPDiff;
+ case X86::VR128RegClassID:
+ return Subtarget->is64Bit() ? 10 : 4;
+ case X86::VR64RegClassID:
+ return 4;
+ }
+}
+
bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
unsigned &Offset) const {
if (!Subtarget->isTargetLinux())
@@ -1259,6 +1308,20 @@
CCValAssign &VA = RVLocs[i];
assert(VA.isRegLoc() && "Can only return in registers!");
SDValue ValToCopy = OutVals[i];
+ EVT ValVT = ValToCopy.getValueType();
+
+ // If this is x86-64, and we disabled SSE, we can't return FP values
+ if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
+ (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
+ report_fatal_error("SSE register return with SSE disabled");
+ }
+ // Likewise we can't return F64 values with SSE1 only. gcc does so, but
+ // llvm-gcc has never done it right and no one has noticed, so this
+ // should be OK for now.
+ if (ValVT == MVT::f64 &&
+ (Subtarget->is64Bit() && !Subtarget->hasSSE2())) {
+ report_fatal_error("SSE2 register return with SSE2 disabled");
+ }
// Returns in ST0/ST1 are handled specially: these are pushed as operands to
// the RET instruction and handled by the FP Stackifier.
@@ -1276,11 +1339,11 @@
// 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
// which is returned in RAX / RDX.
if (Subtarget->is64Bit()) {
- EVT ValVT = ValToCopy.getValueType();
if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
- ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
+ ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
+ ValToCopy);
}
}
@@ -1990,7 +2053,7 @@
}
}
- if (Is64Bit && isVarArg) {
+ if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
// From AMD64 ABI document:
// For calls that may call functions that use varargs or stdargs
// (prototype-less calls or calls to functions containing ellipsis (...) in
@@ -1999,7 +2062,6 @@
// the number of registers, but must be an ubound on the number of SSE
// registers used and is in the range 0 - 8 inclusive.
- // FIXME: Verify this on Win64
// Count the number of XMM registers allocated.
static const unsigned XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
@@ -2356,8 +2418,8 @@
if (RegInfo->needsStackRealignment(MF))
return false;
- // Do not sibcall optimize vararg calls unless the call site is not passing any
- // arguments.
+ // Do not sibcall optimize vararg calls unless the call site is not passing
+ // any arguments.
if (isVarArg && !Outs.empty())
return false;
@@ -7218,7 +7280,8 @@
InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
if (InRegCount > 2) {
- report_fatal_error("Nest register in use - reduce number of inreg parameters!");
+ report_fatal_error("Nest register in use - reduce number of inreg"
+ " parameters!");
}
}
break;
@@ -7439,6 +7502,86 @@
return Res;
}
+SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
+ EVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue R = Op.getOperand(0);
+
+ LLVMContext *Context = DAG.getContext();
+
+ assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
+
+ if (VT == MVT::v4i32) {
+ Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
+ Op.getOperand(1), DAG.getConstant(23, MVT::i32));
+
+ ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
+
+ std::vector<Constant*> CV(4, CI);
+ Constant *C = ConstantVector::get(CV);
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0,
+ false, false, 16);
+
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
+ Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
+ return DAG.getNode(ISD::MUL, dl, VT, Op, R);
+ }
+ if (VT == MVT::v16i8) {
+ // a = a << 5;
+ Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
+ Op.getOperand(1), DAG.getConstant(5, MVT::i32));
+
+ ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
+ ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
+
+ std::vector<Constant*> CVM1(16, CM1);
+ std::vector<Constant*> CVM2(16, CM2);
+ Constant *C = ConstantVector::get(CVM1);
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0,
+ false, false, 16);
+
+ // r = pblendv(r, psllw(r & (char16)15, 4), a);
+ M = DAG.getNode(ISD::AND, dl, VT, R, M);
+ M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
+ DAG.getConstant(4, MVT::i32));
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, M, Op);
+ // a += a
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
+
+ C = ConstantVector::get(CVM2);
+ CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0, false, false, 16);
+
+ // r = pblendv(r, psllw(r & (char16)63, 2), a);
+ M = DAG.getNode(ISD::AND, dl, VT, R, M);
+ M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
+ DAG.getConstant(2, MVT::i32));
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, M, Op);
+ // a += a
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
+
+ // return pblendv(r, r+r, a);
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
+ return R;
+ }
+ return SDValue();
+}
SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
// Lower the "add/sub/mul with overflow" instruction into a regular ins plus
@@ -7508,6 +7651,36 @@
return Sum;
}
+SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
+ DebugLoc dl = Op.getDebugLoc();
+
+ if (!Subtarget->hasSSE2())
+ return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
+ DAG.getConstant(0, MVT::i32));
+
+ unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
+ if(!isDev)
+ return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
+ else {
+ unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+ unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+ unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
+ unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+
+ // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
+ if (!Op1 && !Op2 && !Op3 && Op4)
+ return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
+
+ // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
+ if (Op1 && !Op2 && !Op3 && !Op4)
+ return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
+
+ // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
+ // (MFENCE)>;
+ return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
+ }
+}
+
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
EVT T = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
@@ -7597,6 +7770,7 @@
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default: llvm_unreachable("Should not custom lower this!");
+ case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
@@ -7640,6 +7814,7 @@
case ISD::CTLZ: return LowerCTLZ(Op, DAG);
case ISD::CTTZ: return LowerCTTZ(Op, DAG);
case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
+ case ISD::SHL: return LowerSHL(Op, DAG);
case ISD::SADDO:
case ISD::UADDO:
case ISD::SSUBO:
@@ -8368,19 +8543,31 @@
}
// FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
-// all of this code can be replaced with that in the .td file.
+// or XMM0_V32I8 in AVX all of this code can be replaced with that
+// in the .td file.
MachineBasicBlock *
X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
unsigned numArgs, bool memArg) const {
+ assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
+ "Target must have SSE4.2 or AVX features enabled");
+
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned Opc;
- if (memArg)
- Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
- else
- Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
+
+ if (!Subtarget->hasAVX()) {
+ if (memArg)
+ Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
+ else
+ Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
+ } else {
+ if (memArg)
+ Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
+ else
+ Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
+ }
MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
@@ -8727,12 +8914,16 @@
}
// String/text processing lowering.
case X86::PCMPISTRM128REG:
+ case X86::VPCMPISTRM128REG:
return EmitPCMP(MI, BB, 3, false /* in-mem */);
case X86::PCMPISTRM128MEM:
+ case X86::VPCMPISTRM128MEM:
return EmitPCMP(MI, BB, 3, true /* in-mem */);
case X86::PCMPESTRM128REG:
+ case X86::VPCMPESTRM128REG:
return EmitPCMP(MI, BB, 5, false /* in mem */);
case X86::PCMPESTRM128MEM:
+ case X86::VPCMPESTRM128MEM:
return EmitPCMP(MI, BB, 5, true /* in mem */);
// Atomic Lowering.
@@ -9030,8 +9221,8 @@
// Store the value to a temporary stack slot.
SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
- SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL, 0,
- false, false, 0);
+ SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
+ 0, false, false, 0);
// Replace each use (extract) with a load of the appropriate element.
for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
@@ -9045,11 +9236,12 @@
uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
- SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), OffsetVal, StackPtr);
+ SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
+ OffsetVal, StackPtr);
// Load the scalar.
- SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, ScalarAddr,
- NULL, 0, false, false, 0);
+ SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
+ ScalarAddr, NULL, 0, false, false, 0);
// Replace the exact with the load.
DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
@@ -9087,8 +9279,7 @@
// Converting this to a min would handle NaNs incorrectly, and swapping
// the operands would cause it to handle comparisons between positive
// and negative zero incorrectly.
- if (!FiniteOnlyFPMath() &&
- (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
+ if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
if (!UnsafeFPMath &&
!(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
break;
@@ -9126,8 +9317,7 @@
// Converting this to a max would handle NaNs incorrectly, and swapping
// the operands would cause it to handle comparisons between positive
// and negative zero incorrectly.
- if (!FiniteOnlyFPMath() &&
- (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
+ if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
if (!UnsafeFPMath &&
!(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
break;
@@ -9156,8 +9346,7 @@
// cause it to handle NaNs incorrectly.
if (!UnsafeFPMath &&
!(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
- if (!FiniteOnlyFPMath() &&
- (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
+ if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
break;
std::swap(LHS, RHS);
}
@@ -9182,8 +9371,7 @@
case ISD::SETULT:
// Converting this to a max would handle NaNs incorrectly.
- if (!FiniteOnlyFPMath() &&
- (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
+ if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
break;
Opcode = X86ISD::FMAX;
break;
@@ -9193,8 +9381,7 @@
// cause it to handle NaNs incorrectly.
if (!UnsafeFPMath &&
!DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
- if (!FiniteOnlyFPMath() &&
- (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
+ if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
break;
std::swap(LHS, RHS);
}
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86ISelLowering.h Sat Jul 31 19:59:02 2010
@@ -265,7 +265,13 @@
ATOMXOR64_DAG,
ATOMAND64_DAG,
ATOMNAND64_DAG,
- ATOMSWAP64_DAG
+ ATOMSWAP64_DAG,
+
+ // Memory barrier
+ MEMBARRIER,
+ MFENCE,
+ SFENCE,
+ LFENCE
// WARNING: Do not add anything in the end unless you want the node to
// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
@@ -584,12 +590,19 @@
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
+ unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
+
/// getStackCookieLocation - Return true if the target stores stack
/// protector cookies at a fixed offset in some non-standard address
/// space, and populates the address space and offset as
/// appropriate.
virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
+ protected:
+ std::pair<const TargetRegisterClass*, uint8_t>
+ findRepresentativeClass(EVT VT) const;
+
private:
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
@@ -710,11 +723,13 @@
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue
LowerFormalArguments(SDValue Chain,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86Instr64bit.td Sat Jul 31 19:59:02 2010
@@ -158,7 +158,7 @@
// FIXME: We need to teach codegen about single list of call-clobbered
// registers.
-let isCall = 1 in
+let isCall = 1, isCodeGenOnly = 1 in
// All calls clobber the non-callee saved registers. RSP is marked as
// a use to prevent stack-pointer assignments that appear immediately
// before calls from potentially appearing dead. Uses for argument
@@ -182,7 +182,8 @@
}
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+ isCodeGenOnly = 1 in
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
@@ -216,9 +217,9 @@
def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
"jmp{q}\t$dst", []>;
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
- [(brind GR64:$dst)]>;
+ [(brind GR64:$dst)]>, Requires<[In64BitMode]>;
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
- [(brind (loadi64 addr:$dst))]>;
+ [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
"ljmp{q}\t{*}$dst", []>;
}
@@ -246,7 +247,7 @@
let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
def LEAVE64 : I<0xC9, RawFrm,
- (outs), (ins), "leave", []>;
+ (outs), (ins), "leave", []>, Requires<[In64BitMode]>;
let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
let mayLoad = 1 in {
def POP64r : I<0x58, AddRegFrm,
@@ -330,7 +331,7 @@
// Fast system-call instructions
def SYSEXIT64 : RI<0x35, RawFrm,
- (outs), (ins), "sysexit", []>, TB;
+ (outs), (ins), "sysexit", []>, TB, Requires<[In64BitMode]>;
//===----------------------------------------------------------------------===//
// Move Instructions...
@@ -374,6 +375,7 @@
[(store i64immSExt32:$src, addr:$dst)]>;
/// Versions of MOV64rr, MOV64rm, and MOV64mr for i64mem_TC and GR64_TC.
+let isCodeGenOnly = 1 in {
let neverHasSideEffects = 1 in
def MOV64rr_TC : RI<0x89, MRMDestReg, (outs GR64_TC:$dst), (ins GR64_TC:$src),
"mov{q}\t{$src, $dst|$dst, $src}", []>;
@@ -388,6 +390,7 @@
def MOV64mr_TC : RI<0x89, MRMDestMem, (outs), (ins i64mem_TC:$dst, GR64_TC:$src),
"mov{q}\t{$src, $dst|$dst, $src}",
[]>;
+}
def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
"mov{q}\t{$src, %rax|%rax, $src}", []>;
@@ -1537,116 +1540,6 @@
(SETB_C64r)>;
//===----------------------------------------------------------------------===//
-// Conversion Instructions...
-//
-
-// f64 -> signed i64
-def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
- "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
-def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
- "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
-def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
- "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
-def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
- (ins f128mem:$src),
- "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
- (load addr:$src)))]>;
-def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
- "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
-def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
- "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
-def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
- "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
-def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
- (ins f128mem:$src),
- "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse2_cvttsd2si64
- (load addr:$src)))]>;
-
-// Signed i64 -> f64
-def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
- "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
- [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
-def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
- "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
- [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
-
-let Constraints = "$src1 = $dst" in {
-def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
- "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
- [(set VR128:$dst,
- (int_x86_sse2_cvtsi642sd VR128:$src1,
- GR64:$src2))]>;
-def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
- "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
- [(set VR128:$dst,
- (int_x86_sse2_cvtsi642sd VR128:$src1,
- (loadi64 addr:$src2)))]>;
-} // Constraints = "$src1 = $dst"
-
-// Signed i64 -> f32
-def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
- "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
- [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
-def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
- "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
- [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
-
-let Constraints = "$src1 = $dst" in {
- def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
- "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
- [(set VR128:$dst,
- (int_x86_sse_cvtsi642ss VR128:$src1,
- GR64:$src2))]>;
- def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
- (outs VR128:$dst),
- (ins VR128:$src1, i64mem:$src2),
- "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
- [(set VR128:$dst,
- (int_x86_sse_cvtsi642ss VR128:$src1,
- (loadi64 addr:$src2)))]>;
-} // Constraints = "$src1 = $dst"
-
-// f32 -> signed i64
-def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
- "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
-def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
- "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
-def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
- "cvtss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse_cvtss2si64 VR128:$src))]>;
-def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
- "cvtss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (int_x86_sse_cvtss2si64
- (load addr:$src)))]>;
-def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
- "cvttss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
-def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
- "cvttss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
-def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
- "cvttss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse_cvttss2si64 VR128:$src))]>;
-def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
- (ins f32mem:$src),
- "cvttss2si{q}\t{$src, $dst|$dst, $src}",
- [(set GR64:$dst,
- (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
-
// Descriptor-table support instructions
// LLDT is not interpreted specially in 64-bit mode because there is no sign
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrFPStack.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrFPStack.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrFPStack.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrFPStack.td Sat Jul 31 19:59:02 2010
@@ -108,10 +108,6 @@
[(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
}
-let isTerminator = 1 in
- let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
- def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>;
-
// All FP Stack operations are represented with four instructions here. The
// first three instructions, generated by the instruction selector, use "RFP32"
// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrFormats.td Sat Jul 31 19:59:02 2010
@@ -411,6 +411,20 @@
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
Requires<[HasSSE42]>;
+// AVX Instruction Templates:
+// Instructions introduced in AVX (no SSE equivalent forms)
+//
+// AVX8I - AVX instructions with T8 and OpSize prefix.
+// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
+class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag> pattern>
+ : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
+ Requires<[HasAVX]>;
+class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag> pattern>
+ : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
+ Requires<[HasAVX]>;
+
// AES Instruction Templates:
//
// AES8I
@@ -425,6 +439,18 @@
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
Requires<[HasAES]>;
+// CLMUL Instruction Templates
+class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag>pattern>
+ : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
+ OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
+
+// FMA3 Instruction Templates
+class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
+ list<dag>pattern>
+ : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
+ OpSize, VEX_4V, Requires<[HasFMA3]>;
+
// X86-64 Instruction templates...
//
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrFragmentsSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrFragmentsSIMD.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrFragmentsSIMD.td Sat Jul 31 19:59:02 2010
@@ -213,6 +213,7 @@
def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
// FIXME: move this to a more appropriate place after all AVX is done.
+def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
@@ -261,6 +262,9 @@
def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
+// FIXME: move this to a more appropriate place after all AVX is done.
+def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
+
def vzmovl_v2i64 : PatFrag<(ops node:$src),
(bitconvert (v2i64 (X86vzmovl
(v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -667,46 +667,6 @@
assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
}
-bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
- switch (MI.getOpcode()) {
- default:
- return false;
- case X86::MOV8rr:
- case X86::MOV8rr_NOREX:
- case X86::MOV16rr:
- case X86::MOV32rr:
- case X86::MOV64rr:
- case X86::MOV32rr_TC:
- case X86::MOV64rr_TC:
-
- // FP Stack register class copies
- case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
- case X86::MOV_Fp3264: case X86::MOV_Fp3280:
- case X86::MOV_Fp6432: case X86::MOV_Fp8032:
-
- // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
- // copies are done with FsMOVAPSrr and FsMOVAPDrr.
-
- case X86::FsMOVAPSrr:
- case X86::FsMOVAPDrr:
- case X86::MOVAPSrr:
- case X86::MOVAPDrr:
- case X86::MOVDQArr:
- case X86::MMX_MOVQ64rr:
- assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- "invalid register-register move instruction");
- SrcReg = MI.getOperand(1).getReg();
- DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
- return true;
- }
-}
-
bool
X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
@@ -827,7 +787,7 @@
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (isFrameLoadOpcode(MI->getOpcode()))
- if (isFrameOperand(MI, 1, FrameIndex))
+ if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
return MI->getOperand(0).getReg();
return 0;
}
@@ -866,7 +826,8 @@
unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
if (isFrameStoreOpcode(MI->getOpcode()))
- if (isFrameOperand(MI, 0, FrameIndex))
+ if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
+ isFrameOperand(MI, 0, FrameIndex))
return MI->getOperand(X86::AddrNumOperands).getReg();
return 0;
}
@@ -1664,14 +1625,6 @@
return !isPredicated(MI);
}
-// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
-static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
- const X86InstrInfo &TII) {
- if (MI->getOpcode() == X86::FP_REG_KILL)
- return false;
- return TII.isUnpredicatedTerminator(MI);
-}
-
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
@@ -1688,7 +1641,7 @@
// Working from the bottom, when we see a non-terminator instruction, we're
// done.
- if (!isBrAnalysisUnpredicatedTerminator(I, *this))
+ if (!isUnpredicatedTerminator(I))
break;
// A terminator that isn't a branch can't easily be handled by this
@@ -2046,6 +1999,8 @@
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
const MachineFunction &MF = *MBB.getParent();
+ assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
+ "Stack slot too small for store");
bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL = MBB.findDebugLoc(MI);
@@ -2130,8 +2085,9 @@
CalleeFrameSize += SlotSize;
BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
} else {
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
- &X86::VR128RegClass, &RI);
+ RC, &RI);
}
}
@@ -2161,8 +2117,9 @@
if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
BuildMI(MBB, MI, DL, get(Opc), Reg);
} else {
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
- &X86::VR128RegClass, &RI);
+ RC, &RI);
}
}
return true;
@@ -2991,561 +2948,6 @@
return false;
}
-
-/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
-/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
-/// size, and 3) use of X86-64 extended registers.
-unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
- unsigned REX = 0;
- const TargetInstrDesc &Desc = MI.getDesc();
-
- // Pseudo instructions do not need REX prefix byte.
- if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
- return 0;
- if (Desc.TSFlags & X86II::REX_W)
- REX |= 1 << 3;
-
- unsigned NumOps = Desc.getNumOperands();
- if (NumOps) {
- bool isTwoAddr = NumOps > 1 &&
- Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
-
- // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
- unsigned i = isTwoAddr ? 1 : 0;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isReg()) {
- unsigned Reg = MO.getReg();
- if (isX86_64NonExtLowByteReg(Reg))
- REX |= 0x40;
- }
- }
-
- switch (Desc.TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg:
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= (1 << 0) | (1 << 2);
- break;
- case X86II::MRMSrcReg: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 2;
- i = isTwoAddr ? 2 : 1;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << 0;
- }
- break;
- }
- case X86II::MRMSrcMem: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 2;
- unsigned Bit = 0;
- i = isTwoAddr ? 2 : 1;
- for (; i != NumOps; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isReg()) {
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << Bit;
- Bit++;
- }
- }
- break;
- }
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- case X86II::MRMDestMem: {
- unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
- i = isTwoAddr ? 1 : 0;
- if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
- REX |= 1 << 2;
- unsigned Bit = 0;
- for (; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isReg()) {
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << Bit;
- Bit++;
- }
- }
- break;
- }
- default: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 0;
- i = isTwoAddr ? 2 : 1;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << 2;
- }
- break;
- }
- }
- }
- return REX;
-}
-
-/// sizePCRelativeBlockAddress - This method returns the size of a PC
-/// relative block address instruction
-///
-static unsigned sizePCRelativeBlockAddress() {
- return 4;
-}
-
-/// sizeGlobalAddress - Give the size of the emission of this global address
-///
-static unsigned sizeGlobalAddress(bool dword) {
- return dword ? 8 : 4;
-}
-
-/// sizeConstPoolAddress - Give the size of the emission of this constant
-/// pool address
-///
-static unsigned sizeConstPoolAddress(bool dword) {
- return dword ? 8 : 4;
-}
-
-/// sizeExternalSymbolAddress - Give the size of the emission of this external
-/// symbol
-///
-static unsigned sizeExternalSymbolAddress(bool dword) {
- return dword ? 8 : 4;
-}
-
-/// sizeJumpTableAddress - Give the size of the emission of this jump
-/// table address
-///
-static unsigned sizeJumpTableAddress(bool dword) {
- return dword ? 8 : 4;
-}
-
-static unsigned sizeConstant(unsigned Size) {
- return Size;
-}
-
-static unsigned sizeRegModRMByte(){
- return 1;
-}
-
-static unsigned sizeSIBByte(){
- return 1;
-}
-
-static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
- unsigned FinalSize = 0;
- // If this is a simple integer displacement that doesn't require a relocation.
- if (!RelocOp) {
- FinalSize += sizeConstant(4);
- return FinalSize;
- }
-
- // Otherwise, this is something that requires a relocation.
- if (RelocOp->isGlobal()) {
- FinalSize += sizeGlobalAddress(false);
- } else if (RelocOp->isCPI()) {
- FinalSize += sizeConstPoolAddress(false);
- } else if (RelocOp->isJTI()) {
- FinalSize += sizeJumpTableAddress(false);
- } else {
- llvm_unreachable("Unknown value to relocate!");
- }
- return FinalSize;
-}
-
-static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
- bool IsPIC, bool Is64BitMode) {
- const MachineOperand &Op3 = MI.getOperand(Op+3);
- int DispVal = 0;
- const MachineOperand *DispForReloc = 0;
- unsigned FinalSize = 0;
-
- // Figure out what sort of displacement we have to handle here.
- if (Op3.isGlobal()) {
- DispForReloc = &Op3;
- } else if (Op3.isCPI()) {
- if (Is64BitMode || IsPIC) {
- DispForReloc = &Op3;
- } else {
- DispVal = 1;
- }
- } else if (Op3.isJTI()) {
- if (Is64BitMode || IsPIC) {
- DispForReloc = &Op3;
- } else {
- DispVal = 1;
- }
- } else {
- DispVal = 1;
- }
-
- const MachineOperand &Base = MI.getOperand(Op);
- const MachineOperand &IndexReg = MI.getOperand(Op+2);
-
- unsigned BaseReg = Base.getReg();
-
- // Is a SIB byte needed?
- if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
- IndexReg.getReg() == 0 &&
- (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
- if (BaseReg == 0) { // Just a displacement?
- // Emit special case [disp32] encoding
- ++FinalSize;
- FinalSize += getDisplacementFieldSize(DispForReloc);
- } else {
- unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
- if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
- // Emit simple indirect register encoding... [EAX] f.e.
- ++FinalSize;
- // Be pessimistic and assume it's a disp32, not a disp8
- } else {
- // Emit the most general non-SIB encoding: [REG+disp32]
- ++FinalSize;
- FinalSize += getDisplacementFieldSize(DispForReloc);
- }
- }
-
- } else { // We need a SIB byte, so start by outputting the ModR/M byte first
- assert(IndexReg.getReg() != X86::ESP &&
- IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
-
- bool ForceDisp32 = false;
- if (BaseReg == 0 || DispForReloc) {
- // Emit the normal disp32 encoding.
- ++FinalSize;
- ForceDisp32 = true;
- } else {
- ++FinalSize;
- }
-
- FinalSize += sizeSIBByte();
-
- // Do we need to output a displacement?
- if (DispVal != 0 || ForceDisp32) {
- FinalSize += getDisplacementFieldSize(DispForReloc);
- }
- }
- return FinalSize;
-}
-
-
-static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
- const TargetInstrDesc *Desc,
- bool IsPIC, bool Is64BitMode) {
-
- unsigned Opcode = Desc->Opcode;
- unsigned FinalSize = 0;
-
- // Emit the lock opcode prefix as needed.
- if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
-
- // Emit segment override opcode prefix as needed.
- switch (Desc->TSFlags & X86II::SegOvrMask) {
- case X86II::FS:
- case X86II::GS:
- ++FinalSize;
- break;
- default: llvm_unreachable("Invalid segment!");
- case 0: break; // No segment override!
- }
-
- // Emit the repeat opcode prefix as needed.
- if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
-
- // Emit the operand size opcode prefix as needed.
- if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
-
- // Emit the address size opcode prefix as needed.
- if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
-
- bool Need0FPrefix = false;
- switch (Desc->TSFlags & X86II::Op0Mask) {
- case X86II::TB: // Two-byte opcode prefix
- case X86II::T8: // 0F 38
- case X86II::TA: // 0F 3A
- Need0FPrefix = true;
- break;
- case X86II::TF: // F2 0F 38
- ++FinalSize;
- Need0FPrefix = true;
- break;
- case X86II::REP: break; // already handled.
- case X86II::XS: // F3 0F
- ++FinalSize;
- Need0FPrefix = true;
- break;
- case X86II::XD: // F2 0F
- ++FinalSize;
- Need0FPrefix = true;
- break;
- case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
- case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
- ++FinalSize;
- break; // Two-byte opcode prefix
- default: llvm_unreachable("Invalid prefix!");
- case 0: break; // No prefix!
- }
-
- if (Is64BitMode) {
- // REX prefix
- unsigned REX = X86InstrInfo::determineREX(MI);
- if (REX)
- ++FinalSize;
- }
-
- // 0x0F escape code must be emitted just before the opcode.
- if (Need0FPrefix)
- ++FinalSize;
-
- switch (Desc->TSFlags & X86II::Op0Mask) {
- case X86II::T8: // 0F 38
- ++FinalSize;
- break;
- case X86II::TA: // 0F 3A
- ++FinalSize;
- break;
- case X86II::TF: // F2 0F 38
- ++FinalSize;
- break;
- }
-
- // If this is a two-address instruction, skip one of the register operands.
- unsigned NumOps = Desc->getNumOperands();
- unsigned CurOp = 0;
- if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
- CurOp++;
- else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
- // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
- --NumOps;
-
- switch (Desc->TSFlags & X86II::FormMask) {
- default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
- case X86II::Pseudo:
- // Remember the current PC offset, this is the PIC relocation
- // base address.
- switch (Opcode) {
- default:
- break;
- case TargetOpcode::INLINEASM: {
- const MachineFunction *MF = MI.getParent()->getParent();
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
- FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
- *MF->getTarget().getMCAsmInfo());
- break;
- }
- case TargetOpcode::DBG_LABEL:
- case TargetOpcode::EH_LABEL:
- case TargetOpcode::DBG_VALUE:
- break;
- case TargetOpcode::IMPLICIT_DEF:
- case TargetOpcode::KILL:
- case X86::FP_REG_KILL:
- break;
- case X86::MOVPC32r: {
- // This emits the "call" portion of this pseudo instruction.
- ++FinalSize;
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- break;
- }
- }
- CurOp = NumOps;
- break;
- case X86II::RawFrm:
- ++FinalSize;
-
- if (CurOp != NumOps) {
- const MachineOperand &MO = MI.getOperand(CurOp++);
- if (MO.isMBB()) {
- FinalSize += sizePCRelativeBlockAddress();
- } else if (MO.isGlobal()) {
- FinalSize += sizeGlobalAddress(false);
- } else if (MO.isSymbol()) {
- FinalSize += sizeExternalSymbolAddress(false);
- } else if (MO.isImm()) {
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- } else {
- llvm_unreachable("Unknown RawFrm operand!");
- }
- }
- break;
-
- case X86II::AddRegFrm:
- ++FinalSize;
- ++CurOp;
-
- if (CurOp != NumOps) {
- const MachineOperand &MO1 = MI.getOperand(CurOp++);
- unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
- if (MO1.isImm())
- FinalSize += sizeConstant(Size);
- else {
- bool dword = false;
- if (Opcode == X86::MOV64ri)
- dword = true;
- if (MO1.isGlobal()) {
- FinalSize += sizeGlobalAddress(dword);
- } else if (MO1.isSymbol())
- FinalSize += sizeExternalSymbolAddress(dword);
- else if (MO1.isCPI())
- FinalSize += sizeConstPoolAddress(dword);
- else if (MO1.isJTI())
- FinalSize += sizeJumpTableAddress(dword);
- }
- }
- break;
-
- case X86II::MRMDestReg: {
- ++FinalSize;
- FinalSize += sizeRegModRMByte();
- CurOp += 2;
- if (CurOp != NumOps) {
- ++CurOp;
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- }
- break;
- }
- case X86II::MRMDestMem: {
- ++FinalSize;
- FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
- CurOp += X86::AddrNumOperands + 1;
- if (CurOp != NumOps) {
- ++CurOp;
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- }
- break;
- }
-
- case X86II::MRMSrcReg:
- ++FinalSize;
- FinalSize += sizeRegModRMByte();
- CurOp += 2;
- if (CurOp != NumOps) {
- ++CurOp;
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- }
- break;
-
- case X86II::MRMSrcMem: {
- ++FinalSize;
- FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
- CurOp += X86::AddrNumOperands + 1;
- if (CurOp != NumOps) {
- ++CurOp;
- FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
- }
- break;
- }
-
- case X86II::MRM0r: case X86II::MRM1r:
- case X86II::MRM2r: case X86II::MRM3r:
- case X86II::MRM4r: case X86II::MRM5r:
- case X86II::MRM6r: case X86II::MRM7r:
- ++FinalSize;
- if (Desc->getOpcode() == X86::LFENCE ||
- Desc->getOpcode() == X86::MFENCE) {
- // Special handling of lfence and mfence;
- FinalSize += sizeRegModRMByte();
- } else if (Desc->getOpcode() == X86::MONITOR ||
- Desc->getOpcode() == X86::MWAIT) {
- // Special handling of monitor and mwait.
- FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
- } else {
- ++CurOp;
- FinalSize += sizeRegModRMByte();
- }
-
- if (CurOp != NumOps) {
- const MachineOperand &MO1 = MI.getOperand(CurOp++);
- unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
- if (MO1.isImm())
- FinalSize += sizeConstant(Size);
- else {
- bool dword = false;
- if (Opcode == X86::MOV64ri32)
- dword = true;
- if (MO1.isGlobal()) {
- FinalSize += sizeGlobalAddress(dword);
- } else if (MO1.isSymbol())
- FinalSize += sizeExternalSymbolAddress(dword);
- else if (MO1.isCPI())
- FinalSize += sizeConstPoolAddress(dword);
- else if (MO1.isJTI())
- FinalSize += sizeJumpTableAddress(dword);
- }
- }
- break;
-
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m: {
-
- ++FinalSize;
- FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
- CurOp += X86::AddrNumOperands;
-
- if (CurOp != NumOps) {
- const MachineOperand &MO = MI.getOperand(CurOp++);
- unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
- if (MO.isImm())
- FinalSize += sizeConstant(Size);
- else {
- bool dword = false;
- if (Opcode == X86::MOV64mi32)
- dword = true;
- if (MO.isGlobal()) {
- FinalSize += sizeGlobalAddress(dword);
- } else if (MO.isSymbol())
- FinalSize += sizeExternalSymbolAddress(dword);
- else if (MO.isCPI())
- FinalSize += sizeConstPoolAddress(dword);
- else if (MO.isJTI())
- FinalSize += sizeJumpTableAddress(dword);
- }
- }
- break;
-
- case X86II::MRM_C1:
- case X86II::MRM_C8:
- case X86II::MRM_C9:
- case X86II::MRM_E8:
- case X86II::MRM_F0:
- FinalSize += 2;
- break;
- }
-
- case X86II::MRMInitReg:
- ++FinalSize;
- // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
- FinalSize += sizeRegModRMByte();
- ++CurOp;
- break;
- }
-
- if (!Desc->isVariadic() && CurOp != NumOps) {
- std::string msg;
- raw_string_ostream Msg(msg);
- Msg << "Cannot determine size: " << MI;
- report_fatal_error(Msg.str());
- }
-
-
- return FinalSize;
-}
-
-
-unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
- const TargetInstrDesc &Desc = MI->getDesc();
- bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
- bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
- unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
- if (Desc.getOpcode() == X86::MOVPC32r)
- Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
- return Size;
-}
-
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.h Sat Jul 31 19:59:02 2010
@@ -610,12 +610,6 @@
///
virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
/// extension instruction. That is, it's like a copy where it's legal for the
/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
@@ -826,16 +820,11 @@
if (!MO.isReg()) return false;
return isX86_64ExtendedReg(MO.getReg());
}
- static unsigned determineREX(const MachineInstr &MI);
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
/// higher) register? e.g. r8, xmm8, xmm13, etc.
static bool isX86_64ExtendedReg(unsigned RegNo);
- /// GetInstSize - Returns the size of the specified MachineInstr.
- ///
- virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
-
/// getGlobalBaseReg - Return a virtual register initialized with the
/// the global base register value. Output instructions required to
/// initialize the register in the function entry block, if necessary.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrInfo.td Sat Jul 31 19:59:02 2010
@@ -80,6 +80,21 @@
def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
+def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
+def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+
+def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
+ [SDNPHasChain]>;
+def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
+ [SDNPHasChain]>;
+def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
+ [SDNPHasChain]>;
+def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
+ [SDNPHasChain]>;
+def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
+ [SDNPHasChain]>;
+
+
def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
@@ -222,7 +237,7 @@
def i32mem : X86MemOperand<"printi32mem">;
def i64mem : X86MemOperand<"printi64mem">;
def i128mem : X86MemOperand<"printi128mem">;
-//def i256mem : X86MemOperand<"printi256mem">;
+def i256mem : X86MemOperand<"printi256mem">;
def f32mem : X86MemOperand<"printf32mem">;
def f64mem : X86MemOperand<"printf64mem">;
def f80mem : X86MemOperand<"printf80mem">;
@@ -333,15 +348,21 @@
// X86 Instruction Predicate Definitions.
def HasCMov : Predicate<"Subtarget->hasCMov()">;
def NoCMov : Predicate<"!Subtarget->hasCMov()">;
-def HasMMX : Predicate<"Subtarget->hasMMX()">;
-def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
-def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
-def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
-def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
-def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
-def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
-def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
+
+// FIXME: temporary hack to let codegen assert or generate poor code in case
+// no AVX version of the desired intructions is present, this is better for
+// incremental dev (without fallbacks it's easier to spot what's missing)
+def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
+def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
+def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
+def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
+def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
+def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
+def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
+def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
+
def HasAVX : Predicate<"Subtarget->hasAVX()">;
+def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
@@ -650,9 +671,9 @@
// Indirect branches
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
- [(brind GR32:$dst)]>;
+ [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
- [(brind (loadi32 addr:$dst))]>;
+ [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
(ins i16imm:$seg, i16imm:$off),
@@ -721,7 +742,8 @@
// Tail call stuff.
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+ isCodeGenOnly = 1 in
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
@@ -756,7 +778,7 @@
//
let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
def LEAVE : I<0xC9, RawFrm,
- (outs), (ins), "leave", []>;
+ (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
"popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
@@ -934,7 +956,7 @@
def SYSENTER : I<0x34, RawFrm,
(outs), (ins), "sysenter", []>, TB;
def SYSEXIT : I<0x35, RawFrm,
- (outs), (ins), "sysexit", []>, TB;
+ (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
@@ -1025,17 +1047,23 @@
/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
/// 32-bit offset from the PC. These are only valid in x86-32 mode.
def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
- "mov{b}\t{$src, %al|%al, $src}", []>;
+ "mov{b}\t{$src, %al|%al, $src}", []>,
+ Requires<[In32BitMode]>;
def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
- "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
+ "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
+ Requires<[In32BitMode]>;
def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
- "mov{l}\t{$src, %eax|%eax, $src}", []>;
+ "mov{l}\t{$src, %eax|%eax, $src}", []>,
+ Requires<[In32BitMode]>;
def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
- "mov{b}\t{%al, $dst|$dst, %al}", []>;
+ "mov{b}\t{%al, $dst|$dst, %al}", []>,
+ Requires<[In32BitMode]>;
def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
- "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
+ "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
+ Requires<[In32BitMode]>;
def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
- "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
+ "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
+ Requires<[In32BitMode]>;
// Moves to and from segment registers
def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
@@ -1087,6 +1115,7 @@
[(store GR32:$src, addr:$dst)]>;
/// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
+let isCodeGenOnly = 1 in {
let neverHasSideEffects = 1 in
def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
"mov{l}\t{$src, $dst|$dst, $src}", []>;
@@ -1101,10 +1130,12 @@
def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[]>;
+}
// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
// that they can be used for copying and storing h registers, which can't be
// encoded when a REX prefix is present.
+let isCodeGenOnly = 1 in {
let neverHasSideEffects = 1 in
def MOV8rr_NOREX : I<0x88, MRMDestReg,
(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
@@ -1118,6 +1149,7 @@
def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
(outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
+}
// Moves to and from debug registers
def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
@@ -3895,6 +3927,20 @@
// Atomic support
//
+// Memory barriers
+let hasSideEffects = 1 in {
+def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
+ "#MEMBARRIER",
+ [(X86MemBarrier)]>, Requires<[HasSSE2]>;
+
+// TODO: Get this to fold the constant into the instruction.
+let Uses = [ESP] in
+def Int_MemBarrierNoSSE : I<0x0B, Pseudo, (outs), (ins GR32:$zero),
+ "lock\n\t"
+ "or{l}\t{$zero, (%esp)|(%esp), $zero}",
+ [(X86MemBarrierNoSSE GR32:$zero)]>, LOCK;
+}
+
// Atomic swap. These are just normal xchg instructions. But since a memory
// operand is referenced, the atomicity is ensured.
let Constraints = "$val = $dst" in {
@@ -4928,6 +4974,12 @@
include "X86InstrFragmentsSIMD.td"
//===----------------------------------------------------------------------===//
+// FMA - Fused Multiply-Add support (requires FMA)
+//===----------------------------------------------------------------------===//
+
+include "X86InstrFMA.td"
+
+//===----------------------------------------------------------------------===//
// XMM Floating point support (requires SSE / SSE2)
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrMMX.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrMMX.td Sat Jul 31 19:59:02 2010
@@ -164,7 +164,7 @@
def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src),
"movq2dq\t{$src, $dst|$dst, $src}", []>;
-def MMX_MOVFR642Qrr: SSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
+def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src),
"movdq2q\t{$src, $dst|$dst, $src}", []>;
def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86InstrSSE.td Sat Jul 31 19:59:02 2010
@@ -256,10 +256,10 @@
let isAsmParserOnly = 1 in {
def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
"movss\t{$src, $dst|$dst, $src}",
- [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
+ [(store FR32:$src, addr:$dst)]>, XS, VEX;
def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
"movsd\t{$src, $dst|$dst, $src}",
- [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
+ [(store FR64:$src, addr:$dst)]>, XD, VEX;
}
// Extract and store.
@@ -516,6 +516,14 @@
[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
}
+multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
+ X86MemOperand x86memop, string asm> {
+ def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
+ []>;
+ def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
+ []>;
+}
+
multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
string asm, Domain d> {
@@ -526,35 +534,58 @@
}
multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
- SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
- string asm> {
+ X86MemOperand x86memop, string asm> {
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
- asm, []>;
+ !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
- (ins DstRC:$src1, x86memop:$src), asm, []>;
+ (ins DstRC:$src1, x86memop:$src),
+ !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
}
let isAsmParserOnly = 1 in {
-defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
- "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
-defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
- "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
-defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
- "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
- VEX_4V;
-defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
- "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
- VEX_4V;
+defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
+ "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
+defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
+ "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
+ VEX_W;
+defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
+ "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
+defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
+ "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
+ VEX, VEX_W;
+
+// The assembler can recognize rr 64-bit instructions by seeing a rxx
+// register, but the same isn't true when only using memory operands,
+// provide other assembly "l" and "q" forms to address this explicitly
+// where appropriate to do so.
+defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
+ VEX_4V;
+defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
+ VEX_4V, VEX_W;
+defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
+ VEX_4V;
+defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
+ VEX_4V;
+defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
+ VEX_4V, VEX_W;
}
defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
"cvttss2si\t{$src, $dst|$dst, $src}">, XS;
+defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
+ "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
"cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
+defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
+ "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
"cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
+defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
+ "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
"cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
+defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
+ "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
// Conversion Instructions Intrinsics - Match intrinsics which expect MM
// and/or XMM operand(s).
@@ -570,10 +601,12 @@
multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
string asm> {
- def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
- [(set DstRC:$dst, (Int SrcRC:$src))]>;
- def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
- [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
+ def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
+ !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
+ [(set DstRC:$dst, (Int SrcRC:$src))]>;
+ def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
+ !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
+ [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
}
multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
@@ -588,35 +621,79 @@
multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
- PatFrag ld_frag, string asm> {
+ PatFrag ld_frag, string asm, bit Is2Addr = 1> {
def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
- asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+ [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
- (ins DstRC:$src1, x86memop:$src2), asm,
+ (ins DstRC:$src1, x86memop:$src2),
+ !if(Is2Addr,
+ !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
}
let isAsmParserOnly = 1 in {
defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
- f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
- VEX;
+ f32mem, load, "cvtss2si">, XS, VEX;
+ defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
+ int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
+ XS, VEX, VEX_W;
defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
- f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
- VEX;
+ f128mem, load, "cvtsd2si">, XD, VEX;
+ defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
+ int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
+ XD, VEX, VEX_W;
+
+ // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
+ // Get rid of this hack or rename the intrinsics, there are several
+ // intructions that only match with the intrinsic form, why create duplicates
+ // to let them be recognized by the assembler?
+ defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
+ "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
+ defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
+ "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
}
defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
- f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
+ f32mem, load, "cvtss2si">, XS;
+defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
+ f32mem, load, "cvtss2si{q}">, XS, REX_W;
defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
- f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
+ f128mem, load, "cvtsd2si">, XD;
+defm Int_CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
+ f128mem, load, "cvtsd2si">, XD, REX_W;
+defm CVTSD2SI64 : sse12_cvt_s_np<0x2D, VR128, GR64, f64mem, "cvtsd2si{q}">, XD,
+ REX_W;
+
+let isAsmParserOnly = 1 in {
+ defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
+ int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
+ defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
+ int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
+ VEX_W;
+ defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
+ int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
+ defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
+ int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
+ VEX_4V, VEX_W;
+}
let Constraints = "$src1 = $dst" in {
defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
int_x86_sse_cvtsi2ss, i32mem, loadi32,
- "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
+ "cvtsi2ss">, XS;
+ defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
+ int_x86_sse_cvtsi642ss, i64mem, loadi64,
+ "cvtsi2ss{q}">, XS, REX_W;
defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
int_x86_sse2_cvtsi2sd, i32mem, loadi32,
- "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
+ "cvtsi2sd">, XD;
+ defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
+ int_x86_sse2_cvtsi642sd, i64mem, loadi64,
+ "cvtsi2sd">, XD, REX_W;
}
// Instructions below don't have an AVX form.
@@ -645,34 +722,47 @@
/// SSE 1 Only
// Aliases for intrinsics
-let isAsmParserOnly = 1, Pattern = []<dag> in {
-defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
- int_x86_sse_cvttss2si, f32mem, load,
- "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
-defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
- int_x86_sse2_cvttsd2si, f128mem, load,
- "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
+let isAsmParserOnly = 1 in {
+defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
+ f32mem, load, "cvttss2si">, XS, VEX;
+defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
+ int_x86_sse_cvttss2si64, f32mem, load,
+ "cvttss2si">, XS, VEX, VEX_W;
+defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
+ f128mem, load, "cvttss2si">, XD, VEX;
+defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
+ int_x86_sse2_cvttsd2si64, f128mem, load,
+ "cvttss2si">, XD, VEX, VEX_W;
}
defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
- f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
- XS;
+ f32mem, load, "cvttss2si">, XS;
+defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
+ int_x86_sse_cvttss2si64, f32mem, load,
+ "cvttss2si{q}">, XS, REX_W;
defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
- f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
- XD;
+ f128mem, load, "cvttss2si">, XD;
+defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
+ int_x86_sse2_cvttsd2si64, f128mem, load,
+ "cvttss2si{q}">, XD, REX_W;
let isAsmParserOnly = 1, Pattern = []<dag> in {
-defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
- "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
-defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
- "cvtdq2ps\t{$src, $dst|$dst, $src}",
- SSEPackedSingle>, TB, VEX;
-defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load,
- "cvtdq2ps\t{$src, $dst|$dst, $src}",
- SSEPackedSingle>, TB, VEX;
+defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
+ "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
+defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
+ "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
+ VEX_W;
+defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
+ "cvtdq2ps\t{$src, $dst|$dst, $src}",
+ SSEPackedSingle>, TB, VEX;
+defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load,
+ "cvtdq2ps\t{$src, $dst|$dst, $src}",
+ SSEPackedSingle>, TB, VEX;
}
let Pattern = []<dag> in {
defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
"cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
+defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
+ "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
"cvtdq2ps\t{$src, $dst|$dst, $src}",
SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
@@ -701,13 +791,11 @@
let isAsmParserOnly = 1 in
defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
- int_x86_sse2_cvtsd2ss, f64mem, load,
- "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
- XS, VEX_4V;
+ int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
+ XS, VEX_4V;
let Constraints = "$src1 = $dst" in
defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
- int_x86_sse2_cvtsd2ss, f64mem, load,
- "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
+ int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
// Convert scalar single to scalar double
let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
@@ -964,11 +1052,11 @@
let isAsmParserOnly = 1 in {
def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- "cvtps2pd\t{$src, $dst|$dst, $src}",
+ "vcvtps2pd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
VEX, Requires<[HasAVX]>;
def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
- "cvtps2pd\t{$src, $dst|$dst, $src}",
+ "vcvtps2pd\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse2_cvtps2pd
(load addr:$src)))]>,
VEX, Requires<[HasAVX]>;
@@ -1232,24 +1320,30 @@
multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
ValueType vt, string asm, PatFrag mem_frag,
Domain d, bit IsConvertibleToThreeAddress = 0> {
- def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
- [(set VR128:$dst, (vt (shufp:$src3
- VR128:$src1, (mem_frag addr:$src2))))], d>;
+ def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
+ [(set RC:$dst, (vt (shufp:$src3
+ RC:$src1, (mem_frag addr:$src2))))], d>;
let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
- def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
- [(set VR128:$dst,
- (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
+ def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
+ [(set RC:$dst,
+ (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
}
let isAsmParserOnly = 1 in {
- defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
- "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
- memopv4f32, SSEPackedSingle>, VEX_4V;
- defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
- "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
- memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
+ defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
+ "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ memopv4f32, SSEPackedSingle>, VEX_4V;
+ defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
+ "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ memopv8f32, SSEPackedSingle>, VEX_4V;
+ defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
+ "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
+ memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
+ defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
+ "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
+ memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
}
let Constraints = "$src1 = $dst" in {
@@ -1351,12 +1445,25 @@
defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
"movmskpd", SSEPackedDouble>, OpSize,
VEX;
+
// FIXME: merge with multiclass above when the intrinsics come.
+ def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
+ "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
+ def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
+ "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
+ VEX;
+
def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
- VEX;
+ VEX;
+
+ def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
+ "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
+ def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
+ "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
+ VEX;
}
//===----------------------------------------------------------------------===//
@@ -1565,7 +1672,7 @@
}
multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
- bit Is2Addr = 1> {
+ bit Is2Addr = 1> {
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
!strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
@@ -1573,7 +1680,7 @@
}
multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
- bit Is2Addr = 1> {
+ bit Is2Addr = 1> {
defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
!strconcat(OpcodeStr, "ps"), "", "_ps", f128mem, memopv4f32,
SSEPackedSingle, Is2Addr>, TB;
@@ -1586,24 +1693,32 @@
// Binary Arithmetic instructions
let isAsmParserOnly = 1 in {
defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
+ basic_sse12_fp_binop_s_int<0x58, "add", 0>,
basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
+ basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
let isCommutable = 0 in {
defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
+ basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
+ basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
+ basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
+ basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>, VEX_4V;
defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
+ basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
+ basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
}
}
@@ -1668,20 +1783,20 @@
multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
SDNode OpNode, Intrinsic F32Int> {
def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
- !strconcat(!strconcat("v", OpcodeStr),
+ !strconcat(OpcodeStr,
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
- !strconcat(!strconcat("v", OpcodeStr),
+ !strconcat(OpcodeStr,
"ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, XS, Requires<[HasAVX, OptForSize]>;
- def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(!strconcat("v", OpcodeStr),
- "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
- def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, ssmem:$src2),
- !strconcat(!strconcat("v", OpcodeStr),
- "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+ def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ !strconcat(OpcodeStr,
+ "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
+ [(set VR128:$dst, (F32Int VR128:$src))]>;
+ def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
+ !strconcat(OpcodeStr,
+ "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
+ [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
}
/// sse1_fp_unop_p - SSE1 unops in packed form.
@@ -1738,21 +1853,19 @@
/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
SDNode OpNode, Intrinsic F64Int> {
- def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
- !strconcat(OpcodeStr,
- "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
- def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
- (ins FR64:$src1, f64mem:$src2),
- !strconcat(OpcodeStr,
- "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
- def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2),
- !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
- def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, sdmem:$src2),
- !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- []>;
+ def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
+ !strconcat(OpcodeStr,
+ "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+ def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
+ (ins FR64:$src1, f64mem:$src2),
+ !strconcat(OpcodeStr,
+ "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+ def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
+ [(set VR128:$dst, (F64Int VR128:$src))]>;
+ def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
+ !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
+ [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
}
/// sse2_fp_unop_p - SSE2 unops in vector forms.
@@ -1789,27 +1902,31 @@
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
// Square root.
- defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
- sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
+ defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
+ sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
VEX_4V;
defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
+ sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
+ sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
VEX;
// Reciprocal approximations. Note that these typically require refinement
// in order to obtain suitable precision.
- defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
+ defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
int_x86_sse_rsqrt_ss>, VEX_4V;
defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
- sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>, VEX;
+ sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
+ sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
- defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
+ defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
VEX_4V;
defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
- sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>, VEX;
+ sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
+ sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
}
// Square root.
@@ -1961,6 +2078,7 @@
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
TB, Requires<[HasSSE1]>;
+def : Pat<(X86SFence), (SFENCE)>;
// Alias instructions that map zero vector to pxor / xorp* for sse.
// We set canFoldAsLoad because this can be converted to a constant-pool
@@ -2003,35 +2121,47 @@
//===---------------------------------------------------------------------===//
// SSE2 - Move Aligned/Unaligned Packed Integer Instructions
//===---------------------------------------------------------------------===//
+
let ExeDomain = SSEPackedInt in { // SSE integer instructions
let isAsmParserOnly = 1 in {
- let neverHasSideEffects = 1 in
- def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
- def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
- "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
+ let neverHasSideEffects = 1 in {
+ def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ }
+ def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+ "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
+ def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
+ "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
let canFoldAsLoad = 1, mayLoad = 1 in {
- def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
- "movdqa\t{$src, $dst|$dst, $src}",
- [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
- VEX;
- def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
- "vmovdqu\t{$src, $dst|$dst, $src}",
- [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
- XS, VEX, Requires<[HasAVX]>;
+ def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ let Predicates = [HasAVX] in {
+ def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+ "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
+ def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
+ "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
+ }
}
let mayStore = 1 in {
- def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
- (ins i128mem:$dst, VR128:$src),
- "movdqa\t{$src, $dst|$dst, $src}",
- [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
- def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
- "vmovdqu\t{$src, $dst|$dst, $src}",
- [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
- XS, VEX, Requires<[HasAVX]>;
+ def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
+ (ins i128mem:$dst, VR128:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
+ (ins i256mem:$dst, VR256:$src),
+ "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+ let Predicates = [HasAVX] in {
+ def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
+ "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
+ def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
+ "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
+ }
}
}
@@ -2376,6 +2506,25 @@
}
} // Constraints = "$src1 = $dst"
+let Predicates = [HasAVX] in {
+ def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
+ (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+ def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
+ (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+ def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
+ (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
+ def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
+ (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
+ def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
+ (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
+
+ // Shift up / down and insert zero's.
+ def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
+ (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+ def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
+ (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
+}
+
let Predicates = [HasSSE2] in {
def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
(v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
@@ -2662,11 +2811,16 @@
imm:$src2))]>;
// Insert
-let isAsmParserOnly = 1, Predicates = [HasAVX] in
- defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
+let isAsmParserOnly = 1, Predicates = [HasAVX] in {
+ defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
+ def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
+ "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, OpSize, VEX_4V;
+}
let Constraints = "$src1 = $dst" in
- defm VPINSRW : sse2_pinsrw, TB, OpSize;
+ defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
} // ExeDomain = SSEPackedInt
@@ -2676,10 +2830,13 @@
let ExeDomain = SSEPackedInt in {
-let isAsmParserOnly = 1 in
-def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
+let isAsmParserOnly = 1 in {
+def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
+def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
+ "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
+}
def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
"pmovmskb\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
@@ -2939,18 +3096,20 @@
// Instructions to match in the assembler
let isAsmParserOnly = 1 in {
-// This instructions is in fact an alias to movd with 64 bit dst
def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
"movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
"movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
+// Recognize "movd" with GR64 destination, but encode as a "movq"
+def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
+ "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
}
// Instructions for the disassembler
// xr = XMM register
// xm = mem64
-let isAsmParserOnly = 1 in
+let isAsmParserOnly = 1, Predicates = [HasAVX] in
def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@@ -2970,19 +3129,14 @@
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
+def : Pat<(X86LFence), (LFENCE)>;
+def : Pat<(X86MFence), (MFENCE)>;
+
// Pause. This "instruction" is encoded as "rep; nop", so even though it
// was introduced with SSE2, it's backward compatible.
def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
-//TODO: custom lower this so as to never even generate the noop
-def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
- (i8 0)), (NOOP)>;
-def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
-def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
-def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
- (i8 1)), (MFENCE)>;
-
// Alias instructions that map zero vector to pxor / xorp* for sse.
// We set canFoldAsLoad because this can be converted to a constant-pool
// load of an all-ones value if folding it would be beneficial.
@@ -3057,9 +3211,20 @@
(memopv4f32 addr:$src), (undef)))]>;
}
+multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
+ string OpcodeStr> {
+def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
+def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
+}
+
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
-defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
-defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
+ // FIXME: Merge above classes when we have patterns for the ymm version
+ defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
+ defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
+ defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
+ defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
}
defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
@@ -3076,15 +3241,30 @@
(undef))))]>;
}
-let isAsmParserOnly = 1, Predicates = [HasAVX] in
- defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
+multiclass sse3_replicate_dfp_y<string OpcodeStr> {
+def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ []>;
+def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ []>;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX] in {
+ // FIXME: Merge above classes when we have patterns for the ymm version
+ defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
+ defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
+}
defm MOVDDUP : sse3_replicate_dfp<"movddup">;
// Move Unaligned Integer
-let isAsmParserOnly = 1 in
+let isAsmParserOnly = 1, Predicates = [HasAVX] in {
def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"vlddqu\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
+ def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
+ "vlddqu\t{$src, $dst|$dst, $src}", []>, VEX;
+}
def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"lddqu\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
@@ -3125,35 +3305,41 @@
// SSE3 - Arithmetic
//===---------------------------------------------------------------------===//
-multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, bit Is2Addr = 1> {
+multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
+ X86MemOperand x86memop, bit Is2Addr = 1> {
def rr : I<0xD0, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+ (outs RC:$dst), (ins RC:$src1, RC:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (Int VR128:$src1,
- VR128:$src2))]>;
+ [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
def rm : I<0xD0, MRMSrcMem,
- (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
+ (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (Int VR128:$src1,
- (memop addr:$src2)))]>;
-
+ [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
}
let isAsmParserOnly = 1, Predicates = [HasAVX],
ExeDomain = SSEPackedDouble in {
- defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", 0>, XD,
- VEX_4V;
- defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", 0>, OpSize,
- VEX_4V;
+ defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
+ f128mem, 0>, XD, VEX_4V;
+ defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
+ f128mem, 0>, OpSize, VEX_4V;
+ let Pattern = []<dag> in {
+ defm VADDSUBPSY : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR256,
+ f256mem, 0>, XD, VEX_4V;
+ defm VADDSUBPDY : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR256,
+ f256mem, 0>, OpSize, VEX_4V;
+ }
}
let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
ExeDomain = SSEPackedDouble in {
- defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps">, XD;
- defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd">, TB, OpSize;
+ defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
+ f128mem>, XD;
+ defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
+ f128mem>, TB, OpSize;
}
//===---------------------------------------------------------------------===//
@@ -3161,51 +3347,65 @@
//===---------------------------------------------------------------------===//
// Horizontal ops
-class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
- : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
+ X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
+ def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
-class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
- : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
+ [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
+
+ def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
-class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
- : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+ [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
+}
+multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
+ X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
+ def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
-class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
- : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
+ [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
+
+ def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
!if(Is2Addr,
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
- [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
+ [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
+}
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
- def VHADDPSrr : S3D_Intrr<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
- def VHADDPSrm : S3D_Intrm<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
- def VHADDPDrr : S3_Intrr <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
- def VHADDPDrm : S3_Intrm <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
- def VHSUBPSrr : S3D_Intrr<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
- def VHSUBPSrm : S3D_Intrm<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
- def VHSUBPDrr : S3_Intrr <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
- def VHSUBPDrm : S3_Intrm <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
+ defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
+ int_x86_sse3_hadd_ps, 0>, VEX_4V;
+ defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
+ int_x86_sse3_hadd_pd, 0>, VEX_4V;
+ defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
+ int_x86_sse3_hsub_ps, 0>, VEX_4V;
+ defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
+ int_x86_sse3_hsub_pd, 0>, VEX_4V;
+ let Pattern = []<dag> in {
+ defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
+ int_x86_sse3_hadd_ps, 0>, VEX_4V;
+ defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
+ int_x86_sse3_hadd_pd, 0>, VEX_4V;
+ defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
+ int_x86_sse3_hsub_ps, 0>, VEX_4V;
+ defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
+ int_x86_sse3_hsub_pd, 0>, VEX_4V;
+ }
}
let Constraints = "$src1 = $dst" in {
- def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
- def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
- def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
- def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
- def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
- def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
- def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
- def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
+ defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
+ int_x86_sse3_hadd_ps>;
+ defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
+ int_x86_sse3_hadd_pd>;
+ defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
+ int_x86_sse3_hsub_ps>;
+ defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
+ int_x86_sse3_hsub_pd>;
}
//===---------------------------------------------------------------------===//
@@ -3923,8 +4123,12 @@
// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
}
-let isAsmParserOnly = 1, Predicates = [HasAVX] in
+let isAsmParserOnly = 1, Predicates = [HasAVX] in {
defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
+ def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
+}
defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
@@ -4007,8 +4211,13 @@
addr:$dst)]>, OpSize;
}
-let isAsmParserOnly = 1, Predicates = [HasAVX] in
+let isAsmParserOnly = 1, Predicates = [HasAVX] in {
defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
+ def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
+ (ins VR128:$src1, i32i8imm:$src2),
+ "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ []>, OpSize, VEX;
+}
defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
// Also match an EXTRACTPS store when the store is done as f32 instead of i32.
@@ -4131,7 +4340,11 @@
defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
- (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
+ (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
+ Requires<[HasAVX]>;
+def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
+ (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
+ Requires<[HasSSE41]>;
//===----------------------------------------------------------------------===//
// SSE4.1 - Round Instructions
@@ -4178,33 +4391,33 @@
OpSize;
}
-multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
- string OpcodeStr> {
+multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
+ RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
// Intrinsic operation, reg.
// Vector intrinsic operation, reg
def PSr : SS4AIi8<opcps, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+ (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
// Vector intrinsic operation, mem
def PSm : Ii8<opcps, MRMSrcMem,
- (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+ (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, TA, OpSize, Requires<[HasSSE41]>;
// Vector intrinsic operation, reg
def PDr : SS4AIi8<opcpd, MRMSrcReg,
- (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+ (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
// Vector intrinsic operation, mem
def PDm : SS4AIi8<opcpd, MRMSrcMem,
- (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+ (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr,
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[]>, OpSize;
@@ -4261,8 +4474,8 @@
OpSize;
}
-multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
- string OpcodeStr> {
+multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
+ string OpcodeStr> {
// Intrinsic operation, reg.
def SSr : SS4AIi8<opcss, MRMSrcReg,
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
@@ -4302,8 +4515,11 @@
int_x86_sse41_round_ss, int_x86_sse41_round_sd,
0>, VEX_4V;
// Instructions for the assembler
- defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
- defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
+ defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
+ VEX;
+ defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
+ VEX;
+ defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
}
defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
@@ -4313,6 +4529,57 @@
int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
//===----------------------------------------------------------------------===//
+// SSE4.1 - Packed Bit Test
+//===----------------------------------------------------------------------===//
+
+// ptest instruction we'll lower to this in X86ISelLowering primarily from
+// the intel intrinsic that corresponds to this.
+let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
+def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
+ OpSize, VEX;
+def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
+
+def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
+ OpSize, VEX;
+def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
+ "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
+}
+
+let Defs = [EFLAGS] in {
+def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
+ "ptest \t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
+ OpSize;
+def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
+ "ptest \t{$src2, $src1|$src1, $src2}",
+ [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
+ OpSize;
+}
+
+// The bit test instructions below are AVX only
+multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
+ X86MemOperand x86memop> {
+ def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ []>, OpSize, VEX;
+ def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+ []>, OpSize, VEX;
+}
+
+let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
+ defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem>;
+ defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem>;
+ defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem>;
+ defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem>;
+}
+
+//===----------------------------------------------------------------------===//
// SSE4.1 - Misc Instructions
//===----------------------------------------------------------------------===//
@@ -4431,79 +4698,110 @@
/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
- Intrinsic IntId128, bit Is2Addr = 1> {
+ Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
+ X86MemOperand x86memop, bit Is2Addr = 1> {
let isCommutable = 1 in
- def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+ def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2, i32i8imm:$src3),
!if(Is2Addr,
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
- [(set VR128:$dst,
- (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
+ [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
OpSize;
- def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
+ def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
!if(Is2Addr,
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
- [(set VR128:$dst,
- (IntId128 VR128:$src1,
- (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
+ [(set RC:$dst,
+ (IntId RC:$src1,
+ (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
OpSize;
}
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
let isCommutable = 0 in {
defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
+ let Pattern = []<dag> in {
+ defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
+ VR256, memopv32i8, i256mem, 0>, VEX_4V;
+ defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
+ VR256, memopv32i8, i256mem, 0>, VEX_4V;
+ }
defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
}
defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
- 0>, VEX_4V;
+ VR128, memopv16i8, i128mem, 0>, VEX_4V;
+ let Pattern = []<dag> in
+ defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
+ VR256, memopv32i8, i256mem, 0>, VEX_4V;
}
let Constraints = "$src1 = $dst" in {
let isCommutable = 0 in {
- defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
- defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
- defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
- defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
+ defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
+ VR128, memopv16i8, i128mem>;
+ defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
+ VR128, memopv16i8, i128mem>;
+ defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
+ VR128, memopv16i8, i128mem>;
+ defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
+ VR128, memopv16i8, i128mem>;
}
- defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
- defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
+ defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
+ VR128, memopv16i8, i128mem>;
+ defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
+ VR128, memopv16i8, i128mem>;
}
/// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
- multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr> {
- def rr : I<opc, MRMSrcReg, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, VR128:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
- [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
-
- def rm : I<opc, MRMSrcMem, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, VR128:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
- [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
- }
+multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
+ RegisterClass RC, X86MemOperand x86memop,
+ PatFrag mem_frag, Intrinsic IntId> {
+ def rr : I<opc, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2, RC:$src3),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
+ SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
+
+ def rm : I<opc, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, x86memop:$src2, RC:$src3),
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+ [(set RC:$dst,
+ (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
+ RC:$src3))],
+ SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
+}
}
-defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd">;
-defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps">;
-defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb">;
+defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
+ memopv16i8, int_x86_sse41_blendvpd>;
+defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
+ memopv16i8, int_x86_sse41_blendvps>;
+defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
+ memopv16i8, int_x86_sse41_pblendvb>;
+
+let Pattern = []<dag> in { // FIXME: implement 256 intrinsics here.
+defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
+ memopv32i8, int_x86_sse41_blendvpd>;
+defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
+ memopv32i8, int_x86_sse41_blendvps>;
+}
/// SS41I_ternary_int - SSE 4.1 ternary operator
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
@@ -4529,30 +4827,6 @@
defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
-// ptest instruction we'll lower to this in X86ISelLowering primarily from
-// the intel intrinsic that corresponds to this.
-let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
-def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
- "vptest\t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
- OpSize, VEX;
-def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
- "vptest\t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
- OpSize, VEX;
-}
-
-let Defs = [EFLAGS] in {
-def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
- "ptest \t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
- OpSize;
-def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
- "ptest \t{$src2, $src1|$src1, $src2}",
- [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
- OpSize;
-}
-
let isAsmParserOnly = 1, Predicates = [HasAVX] in
def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"vmovntdqa\t{$src, $dst|$dst, $src}",
@@ -4603,17 +4877,20 @@
//===----------------------------------------------------------------------===//
// Packed Compare Implicit Length Strings, Return Mask
-let Defs = [EFLAGS], usesCustomInserter = 1 in {
- def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src2, i8imm:$src3),
- "#PCMPISTRM128rr PSEUDO!",
+multiclass pseudo_pcmpistrm<string asm> {
+ def REG : Ii8<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3), !strconcat(asm, "rr PSEUDO"),
[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
- imm:$src3))]>, OpSize;
- def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
- "#PCMPISTRM128rm PSEUDO!",
+ imm:$src3))]>;
+ def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3), !strconcat(asm, "rm PSEUDO"),
[(set VR128:$dst, (int_x86_sse42_pcmpistrm128
- VR128:$src1, (load addr:$src2), imm:$src3))]>, OpSize;
+ VR128:$src1, (load addr:$src2), imm:$src3))]>;
+}
+
+let Defs = [EFLAGS], usesCustomInserter = 1 in {
+ defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
+ defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
}
let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
@@ -4636,20 +4913,20 @@
}
// Packed Compare Explicit Length Strings, Return Mask
-let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
- def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, VR128:$src3, i8imm:$src5),
- "#PCMPESTRM128rr PSEUDO!",
- [(set VR128:$dst,
- (int_x86_sse42_pcmpestrm128
- VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
-
- def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
- (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
- "#PCMPESTRM128rm PSEUDO!",
+multiclass pseudo_pcmpestrm<string asm> {
+ def REG : Ii8<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src3, i8imm:$src5), !strconcat(asm, "rr PSEUDO"),
+ [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
+ VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
+ def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src3, i8imm:$src5), !strconcat(asm, "rm PSEUDO"),
[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
- VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
- OpSize;
+ VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
+}
+
+let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
+ defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
+ defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
}
let isAsmParserOnly = 1, Predicates = [HasAVX],
@@ -4941,3 +5218,143 @@
(int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
imm:$src2))]>,
OpSize;
+
+//===----------------------------------------------------------------------===//
+// CLMUL Instructions
+//===----------------------------------------------------------------------===//
+
+// Only the AVX version of CLMUL instructions are described here.
+
+// Carry-less Multiplication instructions
+let isAsmParserOnly = 1 in {
+def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
+ (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+ "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>;
+
+def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+ "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>;
+
+// Assembler Only
+multiclass avx_vpclmul<string asm> {
+ def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>;
+
+ def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+ !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>;
+}
+defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
+defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
+defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
+defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
+
+} // isAsmParserOnly
+
+//===----------------------------------------------------------------------===//
+// AVX Instructions
+//===----------------------------------------------------------------------===//
+
+let isAsmParserOnly = 1 in {
+
+// Load from memory and broadcast to all elements of the destination operand
+class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
+ X86MemOperand x86memop> :
+ AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, VEX;
+
+def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem>;
+def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem>;
+def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>;
+def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>;
+
+// Insert packed floating-point values
+def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
+ (ins VR256:$src1, VR128:$src2, i8imm:$src3),
+ "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
+ (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
+ "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+
+// Extract packed floating-point values
+def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
+ (ins VR256:$src1, i8imm:$src2),
+ "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ []>, VEX;
+def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
+ (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
+ "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ []>, VEX;
+
+// Conditional SIMD Packed Loads and Stores
+multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr> {
+ def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
+ (ins VR128:$src1, f128mem:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+ def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
+ (ins VR256:$src1, f256mem:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+ def mr : AVX8I<opc_mr, MRMDestMem, (outs),
+ (ins f128mem:$dst, VR128:$src1, VR128:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+ def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
+ (ins f256mem:$dst, VR256:$src1, VR256:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+}
+
+defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps">;
+defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd">;
+
+// Permute Floating-Point Values
+multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
+ RegisterClass RC, X86MemOperand x86memop> {
+ def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, RC:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+ def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
+ (ins RC:$src1, x86memop:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX_4V;
+ def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
+ (ins RC:$src1, i8imm:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX;
+ def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
+ (ins x86memop:$src1, i8imm:$src2),
+ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+ []>, VEX;
+}
+
+defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem>;
+defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem>;
+defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem>;
+defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem>;
+
+def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
+ (ins VR256:$src1, VR256:$src2, i8imm:$src3),
+ "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
+ (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
+ "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
+ []>, VEX_4V;
+
+// Zero All YMM registers
+def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L,
+ Requires<[HasAVX]>;
+
+// Zero Upper bits of YMM registers
+def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX,
+ Requires<[HasAVX]>;
+
+} // isAsmParserOnly
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86MCCodeEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -469,30 +469,36 @@
unsigned NumOps = MI.getNumOperands();
unsigned CurOp = 0;
+ bool IsDestMem = false;
switch (TSFlags & X86II::FormMask) {
case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
+ case X86II::MRMDestMem:
+ IsDestMem = true;
+ // The important info for the VEX prefix is never beyond the address
+ // registers. Don't check beyond that.
+ NumOps = CurOp = X86::AddrNumOperands;
case X86II::MRM0m: case X86II::MRM1m:
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m:
- case X86II::MRMDestMem:
- NumOps = CurOp = X86::AddrNumOperands;
case X86II::MRMSrcMem:
case X86II::MRMSrcReg:
if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_R = 0x0;
-
- // CurOp and NumOps are equal when VEX_R represents a register used
- // to index a memory destination (which is the last operand)
- CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
+ CurOp++;
if (HasVEX_4V) {
- VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+ VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
CurOp++;
}
+ // To only check operands before the memory address ones, start
+ // the search from the begining
+ if (IsDestMem)
+ CurOp = 0;
+
// If the last register should be encoded in the immediate field
// do not use any bit from VEX prefix to this register, ignore it
if (TSFlags & X86II::VEX_I8IMM)
@@ -508,7 +514,10 @@
VEX_X = 0x0;
}
break;
- default: // MRMDestReg, MRM0r-MRM7r
+ default: // MRMDestReg, MRM0r-MRM7r, RawFrm
+ if (!MI.getNumOperands())
+ break;
+
if (MI.getOperand(CurOp).isReg() &&
X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_B = 0;
@@ -524,7 +533,6 @@
VEX_R = 0x0;
}
break;
- assert(0 && "Not implemented!");
}
// Emit segment override opcode prefix as needed.
@@ -833,10 +841,15 @@
case X86II::MRMDestMem:
EmitByte(BaseOpcode, CurByte, OS);
+ SrcRegNum = CurOp + X86::AddrNumOperands;
+
+ if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
+ SrcRegNum++;
+
EmitMemModRMByte(MI, CurOp,
- GetX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)),
+ GetX86RegNum(MI.getOperand(SrcRegNum)),
TSFlags, CurByte, OS, Fixups);
- CurOp += X86::AddrNumOperands + 1;
+ CurOp = SrcRegNum + 1;
break;
case X86II::MRMSrcReg:
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -193,6 +193,12 @@
case X86::DR7:
return 7;
+ // Pseudo index registers are equivalent to a "none"
+ // scaled index (See Intel Manual 2A, table 2-3)
+ case X86::EIZ:
+ case X86::RIZ:
+ return 4;
+
default:
assert(isVirtualRegister(RegNo) && "Unknown physical register!");
llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
@@ -456,26 +462,25 @@
bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
- bool requiresRealignment =
- RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
- F->hasFnAttr(Attribute::StackAlignment));
+ bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
+ F->hasFnAttr(Attribute::StackAlignment));
// FIXME: Currently we don't support stack realignment for functions with
// variable-sized allocas.
- // FIXME: Temporary disable the error - it seems to be too conservative.
+ // FIXME: It's more complicated than this...
if (0 && requiresRealignment && MFI->hasVarSizedObjects())
report_fatal_error(
"Stack realignment in presense of dynamic allocas is not supported");
- return (requiresRealignment && !MFI->hasVarSizedObjects());
+ return requiresRealignment && canRealignStack(MF);
}
-bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
+bool X86RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo()->hasVarSizedObjects();
}
-bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
- int &FrameIdx) const {
+bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
+ unsigned Reg, int &FrameIdx) const {
if (Reg == FramePtr && hasFP(MF)) {
FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
return true;
@@ -979,7 +984,7 @@
if (needsFrameMoves) {
// Mark the place where EBP/RBP was saved.
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
// Define the current CFA rule to use the provided offset.
if (StackSize) {
@@ -1007,7 +1012,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
// Define the current CFA to use the EBP/RBP register.
MachineLocation FPDst(FramePtr);
@@ -1047,7 +1052,7 @@
if (!HasFP && needsFrameMoves) {
// Mark callee-saved push instruction.
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
// Define the current CFA rule to use the provided offset.
unsigned Ptr = StackSize ?
@@ -1119,7 +1124,7 @@
if ((NumBytes || PushedRegs) && needsFrameMoves) {
// Mark end of stack pointer adjustment.
MCSymbol *Label = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
if (!HasFP && NumBytes) {
// Define the current CFA rule to use the provided offset.
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.h Sat Jul 31 19:59:02 2010
@@ -117,9 +117,9 @@
bool needsStackRealignment(const MachineFunction &MF) const;
- bool hasReservedCallFrame(MachineFunction &MF) const;
+ bool hasReservedCallFrame(const MachineFunction &MF) const;
- bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
+ bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
int &FrameIdx) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.td?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86RegisterInfo.td Sat Jul 31 19:59:02 2010
@@ -241,6 +241,10 @@
def CR6 : Register<"cr6">;
def CR7 : Register<"cr7">;
def CR8 : Register<"cr8">;
+
+ // Pseudo index registers
+ def EIZ : Register<"eiz">;
+ def RIZ : Register<"riz">;
}
@@ -804,7 +808,7 @@
}];
}
-def VR256 : RegisterClass<"X86", [v8i32, v4i64, v8f32, v4f64], 256,
+def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
YMM8, YMM9, YMM10, YMM11,
YMM12, YMM13, YMM14, YMM15]> {
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.cpp Sat Jul 31 19:59:02 2010
@@ -260,9 +260,10 @@
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
- HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
- HasAVX = ((ECX >> 28) & 0x1);
- HasAES = IsIntel && ((ECX >> 25) & 0x1);
+ HasCLMUL = IsIntel && ((ECX >> 1) & 0x1);
+ HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
+ HasAVX = ((ECX >> 28) & 0x1);
+ HasAES = IsIntel && ((ECX >> 25) & 0x1);
if (IsIntel || IsAMD) {
// Determine if bit test memory instructions are slow.
@@ -291,6 +292,7 @@
, HasSSE4A(false)
, HasAVX(false)
, HasAES(false)
+ , HasCLMUL(false)
, HasFMA3(false)
, HasFMA4(false)
, IsBTMemSlow(false)
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86Subtarget.h Sat Jul 31 19:59:02 2010
@@ -74,6 +74,9 @@
/// HasAES - Target has AES instructions
bool HasAES;
+ /// HasCLMUL - Target has carry-less multiplication
+ bool HasCLMUL;
+
/// HasFMA3 - Target has 3-operand fused multiply-add
bool HasFMA3;
@@ -149,6 +152,7 @@
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
bool hasAVX() const { return HasAVX; }
bool hasAES() const { return HasAES; }
+ bool hasCLMUL() const { return HasCLMUL; }
bool hasFMA3() const { return HasFMA3; }
bool hasFMA4() const { return HasFMA4; }
bool isBTMemSlow() const { return IsBTMemSlow; }
Modified: llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/X86/X86TargetMachine.cpp Sat Jul 31 19:59:02 2010
@@ -46,6 +46,8 @@
bool RelaxAll) {
Triple TheTriple(TT);
switch (TheTriple.getOS()) {
+ case Triple::Win32:
+ return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll);
default:
return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
}
@@ -182,9 +184,6 @@
bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
- // Install a pass to insert x87 FP_REG_KILL instructions, as needed.
- PM.add(createX87FPRegKillInserterPass());
-
PM.add(createX86MaxStackAlignmentHeuristicPass());
return false; // -print-machineinstr shouldn't print after this.
}
Modified: llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Sat Jul 31 19:59:02 2010
@@ -264,15 +264,13 @@
void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) {
SmallString<128> Str;
raw_svector_ostream O(Str);
-
+
// Check for mov mnemonic
- unsigned src, dst, srcSR, dstSR;
- if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) {
- O << "\tmov " << getRegisterName(dst) << ", ";
- O << getRegisterName(src);
- } else {
+ if (MI->getOpcode() == XCore::ADD_2rus && !MI->getOperand(2).getImm())
+ O << "\tmov " << getRegisterName(MI->getOperand(0).getReg()) << ", "
+ << getRegisterName(MI->getOperand(1).getReg());
+ else
printInstruction(MI, O);
- }
OutStreamer.EmitRawText(O.str());
}
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.cpp Sat Jul 31 19:59:02 2010
@@ -46,33 +46,6 @@
return op.isImm() && op.getImm() == 0;
}
-/// Return true if the instruction is a register to register move and
-/// leave the source and dest operands in the passed parameters.
-///
-bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSR, unsigned &DstSR) const {
- SrcSR = DstSR = 0; // No sub-registers.
-
- // We look for 4 kinds of patterns here:
- // add dst, src, 0
- // sub dst, src, 0
- // or dst, src, src
- // and dst, src, src
- if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus)
- && isZeroImm(MI.getOperand(2))) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r)
- && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- DstReg = MI.getOperand(0).getReg();
- SrcReg = MI.getOperand(1).getReg();
- return true;
- }
- return false;
-}
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
@@ -437,7 +410,7 @@
it->getFrameIdx(), RC, &RI);
if (emitFrameMoves) {
MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
- BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel);
+ BuildMI(MBB, MI, DL, get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
}
}
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.h (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreInstrInfo.h Sat Jul 31 19:59:02 2010
@@ -30,12 +30,6 @@
///
virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
- virtual bool isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
-
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
Modified: llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/branches/wendling/eh/lib/Target/XCore/XCoreRegisterInfo.cpp Sat Jul 31 19:59:02 2010
@@ -420,7 +420,7 @@
// Show update of SP.
MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
MachineLocation SPDst(MachineLocation::VirtualFP);
MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
@@ -439,7 +439,7 @@
if (emitFrameMoves) {
MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveLRLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
MachineLocation CSSrc(XCore::LR);
MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc));
@@ -455,7 +455,7 @@
MBB.addLiveIn(XCore::R10);
if (emitFrameMoves) {
MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveR10Label);
+ BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
MachineLocation CSSrc(XCore::R10);
MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc));
@@ -467,7 +467,7 @@
if (emitFrameMoves) {
// Show FP is now valid.
MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel);
+ BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
MachineLocation SPDst(FramePtr);
MachineLocation SPSrc(MachineLocation::VirtualFP);
MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc));
Modified: llvm/branches/wendling/eh/lib/Transforms/Hello/Hello.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Hello/Hello.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Hello/Hello.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Hello/Hello.cpp Sat Jul 31 19:59:02 2010
@@ -37,7 +37,7 @@
}
char Hello::ID = 0;
-static RegisterPass<Hello> X("hello", "Hello World Pass");
+INITIALIZE_PASS(Hello, "hello", "Hello World Pass", false, false);
namespace {
// Hello2 - The second implementation with getAnalysisUsage implemented.
@@ -60,5 +60,6 @@
}
char Hello2::ID = 0;
-static RegisterPass<Hello2>
-Y("hello2", "Hello World Pass (with getAnalysisUsage implemented)");
+INITIALIZE_PASS(Hello2, "hello2",
+ "Hello World Pass (with getAnalysisUsage implemented)",
+ false, false);
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/ArgumentPromotion.cpp Sat Jul 31 19:59:02 2010
@@ -84,8 +84,8 @@
}
char ArgPromotion::ID = 0;
-static RegisterPass<ArgPromotion>
-X("argpromotion", "Promote 'by reference' arguments to scalars");
+INITIALIZE_PASS(ArgPromotion, "argpromotion",
+ "Promote 'by reference' arguments to scalars", false, false);
Pass *llvm::createArgumentPromotionPass(unsigned maxElements) {
return new ArgPromotion(maxElements);
@@ -208,8 +208,8 @@
// have direct callees.
for (Value::use_iterator UI = Callee->use_begin(), E = Callee->use_end();
UI != E; ++UI) {
- CallSite CS = CallSite::get(*UI);
- assert(CS.getInstruction() && "Should only have direct calls!");
+ CallSite CS(*UI);
+ assert(CS && "Should only have direct calls!");
if (!IsAlwaysValidPointer(CS.getArgument(ArgNo)))
return false;
@@ -619,14 +619,13 @@
// Get a new callgraph node for NF.
CallGraphNode *NF_CGN = CG.getOrInsertFunction(NF);
-
// Loop over all of the callers of the function, transforming the call sites
// to pass in the loaded pointers.
//
SmallVector<Value*, 16> Args;
while (!F->use_empty()) {
- CallSite CS = CallSite::get(F->use_back());
+ CallSite CS(F->use_back());
assert(CS.getCalledFunction() == F);
Instruction *Call = CS.getInstruction();
const AttrListPtr &CallPAL = CS.getAttributes();
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/ConstantMerge.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/ConstantMerge.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/ConstantMerge.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/ConstantMerge.cpp Sat Jul 31 19:59:02 2010
@@ -41,8 +41,8 @@
}
char ConstantMerge::ID = 0;
-static RegisterPass<ConstantMerge>
-X("constmerge", "Merge Duplicate Global Constants");
+INITIALIZE_PASS(ConstantMerge, "constmerge",
+ "Merge Duplicate Global Constants", false, false);
ModulePass *llvm::createConstantMergePass() { return new ConstantMerge(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/DeadArgumentElimination.cpp Sat Jul 31 19:59:02 2010
@@ -151,8 +151,7 @@
char DAE::ID = 0;
-static RegisterPass<DAE>
-X("deadargelim", "Dead Argument Elimination");
+INITIALIZE_PASS(DAE, "deadargelim", "Dead Argument Elimination", false, false);
namespace {
/// DAH - DeadArgumentHacking pass - Same as dead argument elimination, but
@@ -167,8 +166,9 @@
}
char DAH::ID = 0;
-static RegisterPass<DAH>
-Y("deadarghaX0r", "Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE)");
+INITIALIZE_PASS(DAH, "deadarghaX0r",
+ "Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE)",
+ false, false);
/// createDeadArgEliminationPass - This pass removes arguments from functions
/// which are not used by the body of the function.
@@ -220,11 +220,11 @@
//
std::vector<Value*> Args;
while (!Fn.use_empty()) {
- CallSite CS = CallSite::get(Fn.use_back());
+ CallSite CS(Fn.use_back());
Instruction *Call = CS.getInstruction();
// Pass all the same arguments.
- Args.assign(CS.arg_begin(), CS.arg_begin()+NumArgs);
+ Args.assign(CS.arg_begin(), CS.arg_begin() + NumArgs);
// Drop any attributes that were on the vararg arguments.
AttrListPtr PAL = CS.getAttributes();
@@ -253,8 +253,7 @@
if (cast<CallInst>(Call)->isTailCall())
cast<CallInst>(New)->setTailCall();
}
- if (MDNode *N = Call->getDbgMetadata())
- New->setDbgMetadata(N);
+ New->setDebugLoc(Call->getDebugLoc());
Args.clear();
@@ -728,7 +727,7 @@
//
std::vector<Value*> Args;
while (!F->use_empty()) {
- CallSite CS = CallSite::get(F->use_back());
+ CallSite CS(F->use_back());
Instruction *Call = CS.getInstruction();
AttributesVec.clear();
@@ -786,8 +785,7 @@
if (cast<CallInst>(Call)->isTailCall())
cast<CallInst>(New)->setTailCall();
}
- if (MDNode *N = Call->getDbgMetadata())
- New->setDbgMetadata(N);
+ New->setDebugLoc(Call->getDebugLoc());
Args.clear();
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/DeadTypeElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/DeadTypeElimination.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/DeadTypeElimination.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/DeadTypeElimination.cpp Sat Jul 31 19:59:02 2010
@@ -45,7 +45,7 @@
}
char DTE::ID = 0;
-static RegisterPass<DTE> X("deadtypeelim", "Dead Type Elimination");
+INITIALIZE_PASS(DTE, "deadtypeelim", "Dead Type Elimination", false, false);
ModulePass *llvm::createDeadTypeEliminationPass() {
return new DTE();
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/FunctionAttrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/FunctionAttrs.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/FunctionAttrs.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/FunctionAttrs.cpp Sat Jul 31 19:59:02 2010
@@ -69,8 +69,8 @@
}
char FunctionAttrs::ID = 0;
-static RegisterPass<FunctionAttrs>
-X("functionattrs", "Deduce function attributes");
+INITIALIZE_PASS(FunctionAttrs, "functionattrs",
+ "Deduce function attributes", false, false);
Pass *llvm::createFunctionAttrsPass() { return new FunctionAttrs(); }
@@ -162,8 +162,8 @@
// Some instructions can be ignored even if they read or write memory.
// Detect these now, skipping to the next instruction if one is found.
- CallSite CS = CallSite::get(I);
- if (CS.getInstruction() && CS.getCalledFunction()) {
+ CallSite CS(cast<Value>(I));
+ if (CS && CS.getCalledFunction()) {
// Ignore calls to functions in the same SCC.
if (SCCNodes.count(CS.getCalledFunction()))
continue;
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalDCE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalDCE.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalDCE.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalDCE.cpp Sat Jul 31 19:59:02 2010
@@ -51,7 +51,8 @@
}
char GlobalDCE::ID = 0;
-static RegisterPass<GlobalDCE> X("globaldce", "Dead Global Elimination");
+INITIALIZE_PASS(GlobalDCE, "globaldce",
+ "Dead Global Elimination", false, false);
ModulePass *llvm::createGlobalDCEPass() { return new GlobalDCE(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalOpt.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/GlobalOpt.cpp Sat Jul 31 19:59:02 2010
@@ -74,7 +74,8 @@
}
char GlobalOpt::ID = 0;
-static RegisterPass<GlobalOpt> X("globalopt", "Global Variable Optimizer");
+INITIALIZE_PASS(GlobalOpt, "globalopt",
+ "Global Variable Optimizer", false, false);
ModulePass *llvm::createGlobalOptimizerPass() { return new GlobalOpt(); }
@@ -1467,7 +1468,7 @@
TargetData *TD) {
if (!TD)
return false;
-
+
// If this is a malloc of an abstract type, don't touch it.
if (!AllocTy->isSized())
return false;
@@ -2302,7 +2303,8 @@
if (isa<InlineAsm>(CI->getCalledValue())) return false;
// Resolve function pointers.
- Function *Callee = dyn_cast<Function>(getVal(Values, CI->getCalledValue()));
+ Function *Callee = dyn_cast<Function>(getVal(Values,
+ CI->getCalledValue()));
if (!Callee) return false; // Cannot resolve.
SmallVector<Constant*, 8> Formals;
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/IPConstantPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/IPConstantPropagation.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/IPConstantPropagation.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/IPConstantPropagation.cpp Sat Jul 31 19:59:02 2010
@@ -45,8 +45,8 @@
}
char IPCP::ID = 0;
-static RegisterPass<IPCP>
-X("ipconstprop", "Interprocedural constant propagation");
+INITIALIZE_PASS(IPCP, "ipconstprop",
+ "Interprocedural constant propagation", false, false);
ModulePass *llvm::createIPConstantPropagationPass() { return new IPCP(); }
@@ -94,7 +94,7 @@
if (!isa<CallInst>(U) && !isa<InvokeInst>(U))
return false;
- CallSite CS = CallSite::get(cast<Instruction>(U));
+ CallSite CS(cast<Instruction>(U));
if (!CS.isCallee(UI))
return false;
@@ -219,7 +219,7 @@
// constant.
bool MadeChange = false;
for (Value::use_iterator UI = F.use_begin(), E = F.use_end(); UI != E; ++UI) {
- CallSite CS = CallSite::get(*UI);
+ CallSite CS(*UI);
Instruction* Call = CS.getInstruction();
// Not a call instruction or a call instruction that's not calling F
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/InlineAlways.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/InlineAlways.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/InlineAlways.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/InlineAlways.cpp Sat Jul 31 19:59:02 2010
@@ -61,8 +61,8 @@
}
char AlwaysInliner::ID = 0;
-static RegisterPass<AlwaysInliner>
-X("always-inline", "Inliner for always_inline functions");
+INITIALIZE_PASS(AlwaysInliner, "always-inline",
+ "Inliner for always_inline functions", false, false);
Pass *llvm::createAlwaysInlinerPass() { return new AlwaysInliner(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/InlineSimple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/InlineSimple.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/InlineSimple.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/InlineSimple.cpp Sat Jul 31 19:59:02 2010
@@ -56,8 +56,8 @@
}
char SimpleInliner::ID = 0;
-static RegisterPass<SimpleInliner>
-X("inline", "Function Integration/Inlining");
+INITIALIZE_PASS(SimpleInliner, "inline",
+ "Function Integration/Inlining", false, false);
Pass *llvm::createFunctionInliningPass() { return new SimpleInliner(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/Inliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/Inliner.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/Inliner.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/Inliner.cpp Sat Jul 31 19:59:02 2010
@@ -238,11 +238,11 @@
bool someOuterCallWouldNotBeInlined = false;
for (Value::use_iterator I = Caller->use_begin(), E =Caller->use_end();
I != E; ++I) {
- CallSite CS2 = CallSite::get(*I);
+ CallSite CS2(*I);
// If this isn't a call to Caller (it could be some other sort
// of reference) skip it.
- if (CS2.getInstruction() == 0 || CS2.getCalledFunction() != Caller)
+ if (!CS2 || CS2.getCalledFunction() != Caller)
continue;
InlineCost IC2 = getInlineCost(CS2);
@@ -334,10 +334,10 @@
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
- CallSite CS = CallSite::get(I);
+ CallSite CS(cast<Value>(I));
// If this isn't a call, or it is a call to an intrinsic, it can
// never be inlined.
- if (CS.getInstruction() == 0 || isa<IntrinsicInst>(I))
+ if (!CS || isa<IntrinsicInst>(I))
continue;
// If this is a direct call to an external function, we can never inline
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/Internalize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/Internalize.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/Internalize.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/Internalize.cpp Sat Jul 31 19:59:02 2010
@@ -63,8 +63,8 @@
} // end anonymous namespace
char InternalizePass::ID = 0;
-static RegisterPass<InternalizePass>
-X("internalize", "Internalize Global Symbols");
+INITIALIZE_PASS(InternalizePass, "internalize",
+ "Internalize Global Symbols", false, false);
InternalizePass::InternalizePass(bool AllButMain)
: ModulePass(&ID), AllButMain(AllButMain){
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/LoopExtractor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/LoopExtractor.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/LoopExtractor.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/LoopExtractor.cpp Sat Jul 31 19:59:02 2010
@@ -50,8 +50,8 @@
}
char LoopExtractor::ID = 0;
-static RegisterPass<LoopExtractor>
-X("loop-extract", "Extract loops into new functions");
+INITIALIZE_PASS(LoopExtractor, "loop-extract",
+ "Extract loops into new functions", false, false);
namespace {
/// SingleLoopExtractor - For bugpoint.
@@ -62,8 +62,8 @@
} // End anonymous namespace
char SingleLoopExtractor::ID = 0;
-static RegisterPass<SingleLoopExtractor>
-Y("loop-extract-single", "Extract at most one loop into a new function");
+INITIALIZE_PASS(SingleLoopExtractor, "loop-extract-single",
+ "Extract at most one loop into a new function", false, false);
// createLoopExtractorPass - This pass extracts all natural loops from the
// program into a function if it can.
@@ -147,27 +147,26 @@
std::vector<std::pair<std::string, std::string> > BlocksToNotExtractByName;
public:
static char ID; // Pass identification, replacement for typeid
- explicit BlockExtractorPass(const std::vector<BasicBlock*> &B)
- : ModulePass(&ID), BlocksToNotExtract(B) {
+ BlockExtractorPass() : ModulePass(&ID) {
if (!BlockFile.empty())
LoadFile(BlockFile.c_str());
}
- BlockExtractorPass() : ModulePass(&ID) {}
bool runOnModule(Module &M);
};
}
char BlockExtractorPass::ID = 0;
-static RegisterPass<BlockExtractorPass>
-XX("extract-blocks", "Extract Basic Blocks From Module (for bugpoint use)");
+INITIALIZE_PASS(BlockExtractorPass, "extract-blocks",
+ "Extract Basic Blocks From Module (for bugpoint use)",
+ false, false);
// createBlockExtractorPass - This pass extracts all blocks (except those
// specified in the argument list) from the functions in the module.
//
-ModulePass *llvm::createBlockExtractorPass(const std::vector<BasicBlock*> &BTNE)
+ModulePass *llvm::createBlockExtractorPass()
{
- return new BlockExtractorPass(BTNE);
+ return new BlockExtractorPass();
}
void BlockExtractorPass::LoadFile(const char *Filename) {
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/LowerSetJmp.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/LowerSetJmp.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/LowerSetJmp.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/LowerSetJmp.cpp Sat Jul 31 19:59:02 2010
@@ -122,7 +122,7 @@
} // end anonymous namespace
char LowerSetJmp::ID = 0;
-static RegisterPass<LowerSetJmp> X("lowersetjmp", "Lower Set Jump");
+INITIALIZE_PASS(LowerSetJmp, "lowersetjmp", "Lower Set Jump", false, false);
// run - Run the transformation on the program. We grab the function
// prototypes for longjmp and setjmp. If they are used in the program,
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/MergeFunctions.cpp Sat Jul 31 19:59:02 2010
@@ -111,7 +111,7 @@
}
char MergeFunctions::ID = 0;
-static RegisterPass<MergeFunctions> X("mergefunc", "Merge Functions");
+INITIALIZE_PASS(MergeFunctions, "mergefunc", "Merge Functions", false, false);
ModulePass *llvm::createMergeFunctionsPass() {
return new MergeFunctions();
@@ -216,11 +216,17 @@
return true;
}
- case Type::ArrayTyID:
+ case Type::ArrayTyID: {
+ const ArrayType *ATy1 = cast<ArrayType>(Ty1);
+ const ArrayType *ATy2 = cast<ArrayType>(Ty2);
+ return ATy1->getNumElements() == ATy2->getNumElements() &&
+ isEquivalentType(ATy1->getElementType(), ATy2->getElementType());
+ }
case Type::VectorTyID: {
- const SequentialType *STy1 = cast<SequentialType>(Ty1);
- const SequentialType *STy2 = cast<SequentialType>(Ty2);
- return isEquivalentType(STy1->getElementType(), STy2->getElementType());
+ const VectorType *VTy1 = cast<VectorType>(Ty1);
+ const VectorType *VTy2 = cast<VectorType>(Ty2);
+ return VTy1->getNumElements() == VTy2->getNumElements() &&
+ isEquivalentType(VTy1->getElementType(), VTy2->getElementType());
}
}
}
@@ -603,6 +609,10 @@
}
static void AliasGToF(Function *F, Function *G) {
+ // Darwin will trigger llvm_unreachable if asked to codegen an alias.
+ return ThunkGToF(F, G);
+
+#if 0
if (!G->hasExternalLinkage() && !G->hasLocalLinkage() && !G->hasWeakLinkage())
return ThunkGToF(F, G);
@@ -614,6 +624,7 @@
GA->setVisibility(G->getVisibility());
G->replaceAllUsesWith(GA);
G->eraseFromParent();
+#endif
}
static bool fold(std::vector<Function *> &FnVec, unsigned i, unsigned j) {
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/PartialInlining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/PartialInlining.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/PartialInlining.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/PartialInlining.cpp Sat Jul 31 19:59:02 2010
@@ -40,7 +40,8 @@
}
char PartialInliner::ID = 0;
-static RegisterPass<PartialInliner> X("partial-inliner", "Partial Inliner");
+INITIALIZE_PASS(PartialInliner, "partial-inliner",
+ "Partial Inliner", false, false);
ModulePass* llvm::createPartialInliningPass() { return new PartialInliner(); }
@@ -159,7 +160,7 @@
bool recursive = false;
for (Function::use_iterator UI = currFunc->use_begin(),
UE = currFunc->use_end(); UI != UE; ++UI)
- if (Instruction* I = dyn_cast<Instruction>(UI))
+ if (Instruction* I = dyn_cast<Instruction>(*UI))
if (I->getParent()->getParent() == currFunc) {
recursive = true;
break;
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/PartialSpecialization.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/PartialSpecialization.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/PartialSpecialization.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/PartialSpecialization.cpp Sat Jul 31 19:59:02 2010
@@ -56,8 +56,8 @@
}
char PartSpec::ID = 0;
-static RegisterPass<PartSpec>
-X("partialspecialization", "Partial Specialization");
+INITIALIZE_PASS(PartSpec, "partialspecialization",
+ "Partial Specialization", false, false);
// Specialize F by replacing the arguments (keys) in replacements with the
// constants (values). Replace all calls to F with those constants with
@@ -82,10 +82,10 @@
ii != ee; ) {
Value::use_iterator i = ii;
++ii;
- if (isa<CallInst>(i) || isa<InvokeInst>(i)) {
- CallSite CS(cast<Instruction>(i));
+ User *U = *i;
+ CallSite CS(U);
+ if (CS) {
if (CS.getCalledFunction() == F) {
-
SmallVector<Value*, 6> args;
// Assemble the non-specialized arguments for the updated callsite.
// In the process, make sure that the specialized arguments are
@@ -105,13 +105,13 @@
}
}
Value* NCall;
- if (CallInst *CI = dyn_cast<CallInst>(i)) {
+ if (CallInst *CI = dyn_cast<CallInst>(U)) {
NCall = CallInst::Create(NF, args.begin(), args.end(),
CI->getName(), CI);
cast<CallInst>(NCall)->setTailCall(CI->isTailCall());
cast<CallInst>(NCall)->setCallingConv(CI->getCallingConv());
} else {
- InvokeInst *II = cast<InvokeInst>(i);
+ InvokeInst *II = cast<InvokeInst>(U);
NCall = InvokeInst::Create(NF, II->getNormalDest(),
II->getUnwindDest(),
II->getPersonalityFn(),
@@ -128,8 +128,7 @@
++numReplaced;
}
}
- next_use:
- ;
+ next_use:;
}
return NF;
}
@@ -179,14 +178,14 @@
ui != ue; ++ui) {
bool interesting = false;
-
- if (isa<CmpInst>(ui)) interesting = true;
- else if (isa<CallInst>(ui))
+ User *U = *ui;
+ if (isa<CmpInst>(U)) interesting = true;
+ else if (isa<CallInst>(U))
interesting = ui->getOperand(0) == ii;
- else if (isa<InvokeInst>(ui))
+ else if (isa<InvokeInst>(U))
interesting = ui->getOperand(0) == ii;
- else if (isa<SwitchInst>(ui)) interesting = true;
- else if (isa<BranchInst>(ui)) interesting = true;
+ else if (isa<SwitchInst>(U)) interesting = true;
+ else if (isa<BranchInst>(U)) interesting = true;
if (interesting) {
args.push_back(std::distance(F.arg_begin(), ii));
@@ -201,14 +200,16 @@
std::map<Constant*, int>& dist) {
bool hasIndirect = false;
int total = 0;
- for(Value::use_iterator ii = F.use_begin(), ee = F.use_end();
- ii != ee; ++ii)
- if ((isa<CallInst>(ii) || isa<InvokeInst>(ii))
- && ii->getOperand(0) == &F) {
- ++dist[dyn_cast<Constant>(ii->getOperand(arg + 1))];
+ for (Value::use_iterator ii = F.use_begin(), ee = F.use_end();
+ ii != ee; ++ii) {
+ User *U = *ii;
+ CallSite CS(U);
+ if (CS && CS.getCalledFunction() == &F) {
+ ++dist[dyn_cast<Constant>(CS.getArgument(arg))];
++total;
} else
hasIndirect = true;
+ }
// Preserve the original address taken function even if all other uses
// will be specialized.
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/PruneEH.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/PruneEH.cpp Sat Jul 31 19:59:02 2010
@@ -48,8 +48,8 @@
}
char PruneEH::ID = 0;
-static RegisterPass<PruneEH>
-X("prune-eh", "Remove unused exception handling info");
+INITIALIZE_PASS(PruneEH, "prune-eh",
+ "Remove unused exception handling info", false, false);
Pass *llvm::createPruneEHPass() { return new PruneEH(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/StripDeadPrototypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/StripDeadPrototypes.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/StripDeadPrototypes.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/StripDeadPrototypes.cpp Sat Jul 31 19:59:02 2010
@@ -36,8 +36,8 @@
} // end anonymous namespace
char StripDeadPrototypesPass::ID = 0;
-static RegisterPass<StripDeadPrototypesPass>
-X("strip-dead-prototypes", "Strip Unused Function Prototypes");
+INITIALIZE_PASS(StripDeadPrototypesPass, "strip-dead-prototypes",
+ "Strip Unused Function Prototypes", false, false);
bool StripDeadPrototypesPass::runOnModule(Module &M) {
bool MadeChange = false;
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/StripSymbols.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/StripSymbols.cpp Sat Jul 31 19:59:02 2010
@@ -89,32 +89,33 @@
}
char StripSymbols::ID = 0;
-static RegisterPass<StripSymbols>
-X("strip", "Strip all symbols from a module");
+INITIALIZE_PASS(StripSymbols, "strip",
+ "Strip all symbols from a module", false, false);
ModulePass *llvm::createStripSymbolsPass(bool OnlyDebugInfo) {
return new StripSymbols(OnlyDebugInfo);
}
char StripNonDebugSymbols::ID = 0;
-static RegisterPass<StripNonDebugSymbols>
-Y("strip-nondebug", "Strip all symbols, except dbg symbols, from a module");
+INITIALIZE_PASS(StripNonDebugSymbols, "strip-nondebug",
+ "Strip all symbols, except dbg symbols, from a module",
+ false, false);
ModulePass *llvm::createStripNonDebugSymbolsPass() {
return new StripNonDebugSymbols();
}
char StripDebugDeclare::ID = 0;
-static RegisterPass<StripDebugDeclare>
-Z("strip-debug-declare", "Strip all llvm.dbg.declare intrinsics");
+INITIALIZE_PASS(StripDebugDeclare, "strip-debug-declare",
+ "Strip all llvm.dbg.declare intrinsics", false, false);
ModulePass *llvm::createStripDebugDeclarePass() {
return new StripDebugDeclare();
}
char StripDeadDebugInfo::ID = 0;
-static RegisterPass<StripDeadDebugInfo>
-A("strip-dead-debug-info", "Strip debug info for unused symbols");
+INITIALIZE_PASS(StripDeadDebugInfo, "strip-dead-debug-info",
+ "Strip debug info for unused symbols", false, false);
ModulePass *llvm::createStripDeadDebugInfoPass() {
return new StripDeadDebugInfo();
@@ -254,14 +255,15 @@
}
}
- unsigned MDDbgKind = M.getMDKindID("dbg");
for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI)
for (Function::iterator FI = MI->begin(), FE = MI->end(); FI != FE;
++FI)
for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE;
++BI) {
- Changed = true; // FIXME: Only set if there was debug metadata.
- BI->setMetadata(MDDbgKind, 0);
+ if (!BI->getDebugLoc().isUnknown()) {
+ Changed = true;
+ BI->setDebugLoc(DebugLoc());
+ }
}
return Changed;
Modified: llvm/branches/wendling/eh/lib/Transforms/IPO/StructRetPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/IPO/StructRetPromotion.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/IPO/StructRetPromotion.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/IPO/StructRetPromotion.cpp Sat Jul 31 19:59:02 2010
@@ -62,8 +62,8 @@
}
char SRETPromotion::ID = 0;
-static RegisterPass<SRETPromotion>
-X("sretpromotion", "Promote sret arguments to multiple ret values");
+INITIALIZE_PASS(SRETPromotion, "sretpromotion",
+ "Promote sret arguments to multiple ret values", false, false);
Pass *llvm::createStructRetPromotionPass() {
return new SRETPromotion();
@@ -156,7 +156,7 @@
FnUseI != FnUseE; ++FnUseI) {
// The function is passed in as an argument to (possibly) another function,
// we can't change it!
- CallSite CS = CallSite::get(*FnUseI);
+ CallSite CS(*FnUseI);
Instruction *Call = CS.getInstruction();
// The function is used by something else than a call or invoke instruction,
// we can't change it!
@@ -187,7 +187,7 @@
return false;
for (Value::use_iterator GEPI = GEP->use_begin(), GEPE = GEP->use_end();
GEPI != GEPE; ++GEPI)
- if (!isa<LoadInst>(GEPI))
+ if (!isa<LoadInst>(*GEPI))
return false;
}
// Any other FirstArg users make this function unsuitable for sret
@@ -271,7 +271,7 @@
CallGraphNode *NF_CGN = CG.getOrInsertFunction(NF);
while (!F->use_empty()) {
- CallSite CS = CallSite::get(*F->use_begin());
+ CallSite CS(*F->use_begin());
Instruction *Call = CS.getInstruction();
const AttrListPtr &PAL = F->getAttributes();
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCalls.cpp Sat Jul 31 19:59:02 2010
@@ -96,13 +96,23 @@
/// increase the alignment of the ultimate object, making this check succeed.
unsigned InstCombiner::GetOrEnforceKnownAlignment(Value *V,
unsigned PrefAlign) {
- unsigned BitWidth = TD ? TD->getTypeSizeInBits(V->getType()) :
- sizeof(PrefAlign) * CHAR_BIT;
+ assert(V->getType()->isPointerTy() &&
+ "GetOrEnforceKnownAlignment expects a pointer!");
+ unsigned BitWidth = TD ? TD->getPointerSizeInBits() : 64;
APInt Mask = APInt::getAllOnesValue(BitWidth);
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(V, Mask, KnownZero, KnownOne);
unsigned TrailZ = KnownZero.countTrailingOnes();
+
+ // Avoid trouble with rediculously large TrailZ values, such as
+ // those computed from a null pointer.
+ TrailZ = std::min(TrailZ, unsigned(sizeof(unsigned) * CHAR_BIT - 1));
+
unsigned Align = 1u << std::min(BitWidth - 1, TrailZ);
+ unsigned MaxAlign = Value::MaximumAlignment;
+
+ // LLVM doesn't support alignments larger than this currently.
+ Align = std::min(Align, MaxAlign);
if (PrefAlign > Align)
Align = EnforceKnownAlignment(V, Align, PrefAlign);
@@ -630,8 +640,8 @@
cast<VectorType>(II->getArgOperand(0)->getType())->getNumElements();
APInt DemandedElts(VWidth, 1);
APInt UndefElts(VWidth, 0);
- if (Value *V = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
- UndefElts)) {
+ if (Value *V = SimplifyDemandedVectorElts(II->getArgOperand(0),
+ DemandedElts, UndefElts)) {
II->setArgOperand(0, V);
return II;
}
@@ -655,8 +665,10 @@
if (AllEltsOk) {
// Cast the input vectors to byte vectors.
- Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0), Mask->getType());
- Value *Op1 = Builder->CreateBitCast(II->getArgOperand(1), Mask->getType());
+ Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0),
+ Mask->getType());
+ Value *Op1 = Builder->CreateBitCast(II->getArgOperand(1),
+ Mask->getType());
Value *Result = UndefValue::get(Op0->getType());
// Only extract each element once.
@@ -772,13 +784,15 @@
NewInstruction = IC->ReplaceInstUsesWith(*CI, With);
}
bool isFoldable(unsigned SizeCIOp, unsigned SizeArgOp, bool isString) const {
- if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp - CallInst::ArgOffset))) {
+ if (ConstantInt *SizeCI =
+ dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp))) {
if (SizeCI->isAllOnesValue())
return true;
if (isString)
return SizeCI->getZExtValue() >=
- GetStringLength(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset));
- if (ConstantInt *Arg = dyn_cast<ConstantInt>(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset)))
+ GetStringLength(CI->getArgOperand(SizeArgOp));
+ if (ConstantInt *Arg = dyn_cast<ConstantInt>(
+ CI->getArgOperand(SizeArgOp)))
return SizeCI->getZExtValue() >= Arg->getZExtValue();
}
return false;
@@ -1143,7 +1157,7 @@
IntrinsicInst *Tramp =
cast<IntrinsicInst>(cast<BitCastInst>(Callee)->getOperand(0));
- Function *NestF = cast<Function>(Tramp->getArgOperand(1)->stripPointerCasts());
+ Function *NestF =cast<Function>(Tramp->getArgOperand(1)->stripPointerCasts());
const PointerType *NestFPTy = cast<PointerType>(NestF->getType());
const FunctionType *NestFTy = cast<FunctionType>(NestFPTy->getElementType());
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCasts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCasts.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCasts.cpp Sat Jul 31 19:59:02 2010
@@ -1097,6 +1097,33 @@
break;
}
}
+
+ // Fold (fptrunc (sqrt (fpext x))) -> (sqrtf x)
+ // NOTE: This should be disabled by -fno-builtin-sqrt if we ever support it.
+ CallInst *Call = dyn_cast<CallInst>(CI.getOperand(0));
+ if (Call && Call->getCalledFunction() &&
+ Call->getCalledFunction()->getName() == "sqrt" &&
+ Call->getNumArgOperands() == 1) {
+ CastInst *Arg = dyn_cast<CastInst>(Call->getArgOperand(0));
+ if (Arg && Arg->getOpcode() == Instruction::FPExt &&
+ CI.getType()->isFloatTy() &&
+ Call->getType()->isDoubleTy() &&
+ Arg->getType()->isDoubleTy() &&
+ Arg->getOperand(0)->getType()->isFloatTy()) {
+ Function *Callee = Call->getCalledFunction();
+ Module *M = CI.getParent()->getParent()->getParent();
+ Constant* SqrtfFunc = M->getOrInsertFunction("sqrtf",
+ Callee->getAttributes(),
+ Builder->getFloatTy(),
+ Builder->getFloatTy(),
+ NULL);
+ CallInst *ret = CallInst::Create(SqrtfFunc, Arg->getOperand(0),
+ "sqrtfcall");
+ ret->setAttributes(Callee->getAttributes());
+ return ret;
+ }
+ }
+
return 0;
}
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineCompares.cpp Sat Jul 31 19:59:02 2010
@@ -1374,7 +1374,7 @@
case Instruction::Or:
// If bits are being or'd in that are not present in the constant we
// are comparing against, then the comparison could never succeed!
- if (Constant *BOC = dyn_cast<Constant>(BO->getOperand(1))) {
+ if (ConstantInt *BOC = dyn_cast<ConstantInt>(BO->getOperand(1))) {
Constant *NotCI = ConstantExpr::getNot(RHS);
if (!ConstantExpr::getAnd(BOC, NotCI)->isNullValue())
return ReplaceInstUsesWith(ICI,
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Sat Jul 31 19:59:02 2010
@@ -369,7 +369,7 @@
if (DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(U))
return DI;
if (isa<BitCastInst>(U) && U->hasOneUse()) {
- if (DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(U->use_begin()))
+ if (DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(*U->use_begin()))
return DI;
}
}
Modified: llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/InstCombine/InstructionCombining.cpp Sat Jul 31 19:59:02 2010
@@ -60,8 +60,8 @@
char InstCombiner::ID = 0;
-static RegisterPass<InstCombiner>
-X("instcombine", "Combine redundant instructions");
+INITIALIZE_PASS(InstCombiner, "instcombine",
+ "Combine redundant instructions", false, false);
void InstCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreservedID(LCSSAID);
Modified: llvm/branches/wendling/eh/lib/Transforms/Instrumentation/EdgeProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Instrumentation/EdgeProfiling.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Instrumentation/EdgeProfiling.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Instrumentation/EdgeProfiling.cpp Sat Jul 31 19:59:02 2010
@@ -43,8 +43,8 @@
}
char EdgeProfiler::ID = 0;
-static RegisterPass<EdgeProfiler>
-X("insert-edge-profiling", "Insert instrumentation for edge profiling");
+INITIALIZE_PASS(EdgeProfiler, "insert-edge-profiling",
+ "Insert instrumentation for edge profiling", false, false);
ModulePass *llvm::createEdgeProfilerPass() { return new EdgeProfiler(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp Sat Jul 31 19:59:02 2010
@@ -50,9 +50,9 @@
}
char OptimalEdgeProfiler::ID = 0;
-static RegisterPass<OptimalEdgeProfiler>
-X("insert-optimal-edge-profiling",
- "Insert optimal instrumentation for edge profiling");
+INITIALIZE_PASS(OptimalEdgeProfiler, "insert-optimal-edge-profiling",
+ "Insert optimal instrumentation for edge profiling",
+ false, false);
ModulePass *llvm::createOptimalEdgeProfilerPass() {
return new OptimalEdgeProfiler();
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/ABCD.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/ABCD.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/ABCD.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/ABCD.cpp Sat Jul 31 19:59:02 2010
@@ -441,8 +441,9 @@
} // end anonymous namespace.
char ABCD::ID = 0;
-static RegisterPass<ABCD> X("abcd", "ABCD: Eliminating Array Bounds Checks on Demand");
-
+INITIALIZE_PASS(ABCD, "abcd",
+ "ABCD: Eliminating Array Bounds Checks on Demand",
+ false, false);
bool ABCD::runOnFunction(Function &F) {
modified = false;
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/ADCE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/ADCE.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/ADCE.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/ADCE.cpp Sat Jul 31 19:59:02 2010
@@ -45,7 +45,7 @@
}
char ADCE::ID = 0;
-static RegisterPass<ADCE> X("adce", "Aggressive Dead Code Elimination");
+INITIALIZE_PASS(ADCE, "adce", "Aggressive Dead Code Elimination", false, false);
bool ADCE::runOnFunction(Function& F) {
SmallPtrSet<Instruction*, 128> alive;
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/BasicBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/BasicBlockPlacement.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/BasicBlockPlacement.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/BasicBlockPlacement.cpp Sat Jul 31 19:59:02 2010
@@ -74,8 +74,8 @@
}
char BlockPlacement::ID = 0;
-static RegisterPass<BlockPlacement>
-X("block-placement", "Profile Guided Basic Block Placement");
+INITIALIZE_PASS(BlockPlacement, "block-placement",
+ "Profile Guided Basic Block Placement", false, false);
FunctionPass *llvm::createBlockPlacementPass() { return new BlockPlacement(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/CodeGenPrepare.cpp Sat Jul 31 19:59:02 2010
@@ -82,8 +82,8 @@
}
char CodeGenPrepare::ID = 0;
-static RegisterPass<CodeGenPrepare> X("codegenprepare",
- "Optimize for code generation");
+INITIALIZE_PASS(CodeGenPrepare, "codegenprepare",
+ "Optimize for code generation", false, false);
FunctionPass *llvm::createCodeGenPreparePass(const TargetLowering *TLI) {
return new CodeGenPrepare(TLI);
@@ -548,9 +548,9 @@
CI->eraseFromParent();
}
bool isFoldable(unsigned SizeCIOp, unsigned, bool) const {
- if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp
- - CallInst::ArgOffset)))
- return SizeCI->isAllOnesValue();
+ if (ConstantInt *SizeCI =
+ dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp)))
+ return SizeCI->isAllOnesValue();
return false;
}
};
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/ConstantProp.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/ConstantProp.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/ConstantProp.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/ConstantProp.cpp Sat Jul 31 19:59:02 2010
@@ -45,8 +45,8 @@
}
char ConstantPropagation::ID = 0;
-static RegisterPass<ConstantPropagation>
-X("constprop", "Simple constant propagation");
+INITIALIZE_PASS(ConstantPropagation, "constprop",
+ "Simple constant propagation", false, false);
FunctionPass *llvm::createConstantPropagationPass() {
return new ConstantPropagation();
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/DCE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/DCE.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/DCE.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/DCE.cpp Sat Jul 31 19:59:02 2010
@@ -56,8 +56,8 @@
}
char DeadInstElimination::ID = 0;
-static RegisterPass<DeadInstElimination>
-X("die", "Dead Instruction Elimination");
+INITIALIZE_PASS(DeadInstElimination, "die",
+ "Dead Instruction Elimination", false, false);
Pass *llvm::createDeadInstEliminationPass() {
return new DeadInstElimination();
@@ -81,7 +81,7 @@
}
char DCE::ID = 0;
-static RegisterPass<DCE> Y("dce", "Dead Code Elimination");
+INITIALIZE_PASS(DCE, "dce", "Dead Code Elimination", false, false);
bool DCE::runOnFunction(Function &F) {
// Start out with all of the instructions in the worklist...
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/DeadStoreElimination.cpp Sat Jul 31 19:59:02 2010
@@ -82,7 +82,7 @@
}
char DSE::ID = 0;
-static RegisterPass<DSE> X("dse", "Dead Store Elimination");
+INITIALIZE_PASS(DSE, "dse", "Dead Store Elimination", false, false);
FunctionPass *llvm::createDeadStoreEliminationPass() { return new DSE(); }
@@ -401,10 +401,9 @@
}
continue;
- } else if (CallSite::get(BBI).getInstruction() != 0) {
+ } else if (CallSite CS = cast<Value>(BBI)) {
// If this call does not access memory, it can't
// be undeadifying any of our pointers.
- CallSite CS = CallSite::get(BBI);
if (AA.doesNotAccessMemory(CS))
continue;
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/GEPSplitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/GEPSplitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/GEPSplitter.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/GEPSplitter.cpp Sat Jul 31 19:59:02 2010
@@ -32,8 +32,8 @@
}
char GEPSplitter::ID = 0;
-static RegisterPass<GEPSplitter> X("split-geps",
- "split complex GEPs into simple GEPs");
+INITIALIZE_PASS(GEPSplitter, "split-geps",
+ "split complex GEPs into simple GEPs", false, false);
FunctionPass *llvm::createGEPSplitterPass() {
return new GEPSplitter();
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/GVN.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/GVN.cpp Sat Jul 31 19:59:02 2010
@@ -716,8 +716,7 @@
return new GVN(NoLoads);
}
-static RegisterPass<GVN> X("gvn",
- "Global Value Numbering");
+INITIALIZE_PASS(GVN, "gvn", "Global Value Numbering", false, false);
void GVN::dump(DenseMap<uint32_t, Value*>& d) {
errs() << "{\n";
@@ -735,7 +734,7 @@
for (Instruction::use_iterator UI = p->use_begin(), E = p->use_end();
UI != E; ++UI)
- if (PHINode* use_phi = dyn_cast<PHINode>(UI))
+ if (PHINode* use_phi = dyn_cast<PHINode>(*UI))
if (use_phi->getParent() == inst->getParent())
return false;
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/IndVarSimplify.cpp Sat Jul 31 19:59:02 2010
@@ -102,7 +102,7 @@
void RewriteNonIntegerIVs(Loop *L);
ICmpInst *LinearFunctionTestReplace(Loop *L, const SCEV *BackedgeTakenCount,
- Value *IndVar,
+ PHINode *IndVar,
BasicBlock *ExitingBlock,
BranchInst *BI,
SCEVExpander &Rewriter);
@@ -117,8 +117,8 @@
}
char IndVarSimplify::ID = 0;
-static RegisterPass<IndVarSimplify>
-X("indvars", "Canonicalize Induction Variables");
+INITIALIZE_PASS(IndVarSimplify, "indvars",
+ "Canonicalize Induction Variables", false, false);
Pass *llvm::createIndVarSimplifyPass() {
return new IndVarSimplify();
@@ -131,7 +131,7 @@
/// is actually a much broader range than just linear tests.
ICmpInst *IndVarSimplify::LinearFunctionTestReplace(Loop *L,
const SCEV *BackedgeTakenCount,
- Value *IndVar,
+ PHINode *IndVar,
BasicBlock *ExitingBlock,
BranchInst *BI,
SCEVExpander &Rewriter) {
@@ -181,7 +181,7 @@
// The BackedgeTaken expression contains the number of times that the
// backedge branches to the loop header. This is one less than the
// number of times the loop executes, so use the incremented indvar.
- CmpIndVar = L->getCanonicalInductionVariableIncrement();
+ CmpIndVar = IndVar->getIncomingValueForBlock(ExitingBlock);
} else {
// We have to use the preincremented value...
RHS = SE->getTruncateOrZeroExtend(BackedgeTakenCount,
@@ -534,7 +534,7 @@
// Now that we know the largest of the induction variable expressions
// in this loop, insert a canonical induction variable of the largest size.
- Value *IndVar = 0;
+ PHINode *IndVar = 0;
if (NeedCannIV) {
// Check to see if the loop already has any canonical-looking induction
// variables. If any are present and wider than the planned canonical
@@ -862,9 +862,9 @@
// Check Incr uses. One user is PN and the other user is an exit condition
// used by the conditional terminator.
Value::use_iterator IncrUse = Incr->use_begin();
- Instruction *U1 = cast<Instruction>(IncrUse++);
+ Instruction *U1 = cast<Instruction>(*IncrUse++);
if (IncrUse == Incr->use_end()) return;
- Instruction *U2 = cast<Instruction>(IncrUse++);
+ Instruction *U2 = cast<Instruction>(*IncrUse++);
if (IncrUse != Incr->use_end()) return;
// Find exit condition, which is an fcmp. If it doesn't exist, or if it isn't
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/JumpThreading.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/JumpThreading.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/JumpThreading.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/JumpThreading.cpp Sat Jul 31 19:59:02 2010
@@ -111,8 +111,8 @@
}
char JumpThreading::ID = 0;
-static RegisterPass<JumpThreading>
-X("jump-threading", "Jump Threading");
+INITIALIZE_PASS(JumpThreading, "jump-threading",
+ "Jump Threading", false, false);
// Public interface to the Jump Threading pass
FunctionPass *llvm::createJumpThreadingPass() { return new JumpThreading(); }
@@ -1314,6 +1314,9 @@
<< ", across block:\n "
<< *BB << "\n");
+ if (LVI)
+ LVI->threadEdge(PredBB, BB, SuccBB);
+
// We are going to have to map operands from the original BB block to the new
// copy of the block 'NewBB'. If there are PHI nodes in BB, evaluate them to
// account for entry from PredBB.
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LICM.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LICM.cpp Sat Jul 31 19:59:02 2010
@@ -75,10 +75,10 @@
///
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
- AU.addRequiredID(LoopSimplifyID);
- AU.addRequired<LoopInfo>();
AU.addRequired<DominatorTree>();
AU.addRequired<DominanceFrontier>(); // For scalar promotion (mem2reg)
+ AU.addRequired<LoopInfo>();
+ AU.addRequiredID(LoopSimplifyID);
AU.addRequired<AliasAnalysis>();
AU.addPreserved<ScalarEvolution>();
AU.addPreserved<DominanceFrontier>();
@@ -222,7 +222,7 @@
}
char LICM::ID = 0;
-static RegisterPass<LICM> X("licm", "Loop Invariant Code Motion");
+INITIALIZE_PASS(LICM, "licm", "Loop Invariant Code Motion", false, false);
Pass *llvm::createLICMPass() { return new LICM(); }
@@ -457,7 +457,7 @@
/// position, and may either delete it or move it to outside of the loop.
///
void LICM::sink(Instruction &I) {
- DEBUG(dbgs() << "LICM sinking instruction: " << I);
+ DEBUG(dbgs() << "LICM sinking instruction: " << I << "\n");
SmallVector<BasicBlock*, 8> ExitBlocks;
CurLoop->getExitBlocks(ExitBlocks);
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopDeletion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopDeletion.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopDeletion.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopDeletion.cpp Sat Jul 31 19:59:02 2010
@@ -38,9 +38,9 @@
bool &Changed, BasicBlock *Preheader);
virtual void getAnalysisUsage(AnalysisUsage& AU) const {
- AU.addRequired<ScalarEvolution>();
AU.addRequired<DominatorTree>();
AU.addRequired<LoopInfo>();
+ AU.addRequired<ScalarEvolution>();
AU.addRequiredID(LoopSimplifyID);
AU.addRequiredID(LCSSAID);
@@ -55,7 +55,8 @@
}
char LoopDeletion::ID = 0;
-static RegisterPass<LoopDeletion> X("loop-deletion", "Delete dead loops");
+INITIALIZE_PASS(LoopDeletion, "loop-deletion",
+ "Delete dead loops", false, false);
Pass* llvm::createLoopDeletionPass() {
return new LoopDeletion();
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopIndexSplit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopIndexSplit.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopIndexSplit.cpp Sat Jul 31 19:59:02 2010
@@ -197,8 +197,8 @@
}
char LoopIndexSplit::ID = 0;
-static RegisterPass<LoopIndexSplit>
-X("loop-index-split", "Index Split Loops");
+INITIALIZE_PASS(LoopIndexSplit, "loop-index-split",
+ "Index Split Loops", false, false);
Pass *llvm::createLoopIndexSplitPass() {
return new LoopIndexSplit();
@@ -677,7 +677,7 @@
for(pred_iterator PI = pred_begin(FrontierBB), PE = pred_end(FrontierBB);
PI != PE; ++PI) {
BasicBlock *P = *PI;
- if (P == DeadBB || DT->dominates(DeadBB, P))
+ if (DT->dominates(DeadBB, P))
PredBlocks.push_back(P);
}
@@ -799,7 +799,7 @@
// the dominance frontiers.
for (Loop::block_iterator I = LP->block_begin(), E = LP->block_end();
I != E; ++I) {
- if (*I == CondBB || !DT->dominates(CondBB, *I)) continue;
+ if (!DT->properlyDominates(CondBB, *I)) continue;
DominanceFrontier::iterator BBDF = DF->find(*I);
DominanceFrontier::DomSetType::iterator DomSetI = BBDF->second.begin();
DominanceFrontier::DomSetType::iterator DomSetE = BBDF->second.end();
@@ -1183,7 +1183,7 @@
bool usedOutsideBB = false;
for (Value::use_iterator UI = I->use_begin(), UE = I->use_end();
UI != UE; ++UI) {
- Instruction *U = cast<Instruction>(UI);
+ Instruction *U = cast<Instruction>(*UI);
if (U->getParent() != BB)
usedOutsideBB = true;
}
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopRotation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopRotation.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopRotation.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopRotation.cpp Sat Jul 31 19:59:02 2010
@@ -43,15 +43,15 @@
// LCSSA form makes instruction renaming easier.
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addPreserved<DominatorTree>();
+ AU.addPreserved<DominanceFrontier>();
+ AU.addRequired<LoopInfo>();
+ AU.addPreserved<LoopInfo>();
AU.addRequiredID(LoopSimplifyID);
AU.addPreservedID(LoopSimplifyID);
AU.addRequiredID(LCSSAID);
AU.addPreservedID(LCSSAID);
AU.addPreserved<ScalarEvolution>();
- AU.addRequired<LoopInfo>();
- AU.addPreserved<LoopInfo>();
- AU.addPreserved<DominatorTree>();
- AU.addPreserved<DominanceFrontier>();
}
// Helper functions
@@ -79,7 +79,7 @@
}
char LoopRotate::ID = 0;
-static RegisterPass<LoopRotate> X("loop-rotate", "Rotate Loops");
+INITIALIZE_PASS(LoopRotate, "loop-rotate", "Rotate Loops", false, false);
Pass *llvm::createLoopRotatePass() { return new LoopRotate(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopStrengthReduce.cpp Sat Jul 31 19:59:02 2010
@@ -965,6 +965,12 @@
/// may be used.
bool AllFixupsOutsideLoop;
+ /// WidestFixupType - This records the widest use type for any fixup using
+ /// this LSRUse. FindUseWithSimilarFormula can't consider uses with different
+ /// max fixup widths to be equivalent, because the narrower one may be relying
+ /// on the implicit truncation to truncate away bogus bits.
+ const Type *WidestFixupType;
+
/// Formulae - A list of ways to build a value that can satisfy this user.
/// After the list is populated, one of these is selected heuristically and
/// used to formulate a replacement for OperandValToReplace in UserInst.
@@ -976,7 +982,8 @@
LSRUse(KindType K, const Type *T) : Kind(K), AccessTy(T),
MinOffset(INT64_MAX),
MaxOffset(INT64_MIN),
- AllFixupsOutsideLoop(true) {}
+ AllFixupsOutsideLoop(true),
+ WidestFixupType(0) {}
bool HasFormulaWithSameRegs(const Formula &F) const;
bool InsertFormula(const Formula &F);
@@ -1083,6 +1090,9 @@
if (AllFixupsOutsideLoop)
OS << ", all-fixups-outside-loop";
+
+ if (WidestFixupType)
+ OS << ", widest fixup type: " << *WidestFixupType;
}
void LSRUse::dump() const {
@@ -1928,6 +1938,7 @@
if (&LU != &OrigLU &&
LU.Kind != LSRUse::ICmpZero &&
LU.Kind == OrigLU.Kind && OrigLU.AccessTy == LU.AccessTy &&
+ LU.WidestFixupType == OrigLU.WidestFixupType &&
LU.HasFormulaWithSameRegs(OrigF)) {
for (SmallVectorImpl<Formula>::const_iterator I = LU.Formulae.begin(),
E = LU.Formulae.end(); I != E; ++I) {
@@ -2066,6 +2077,10 @@
LF.Offset = P.second;
LSRUse &LU = Uses[LF.LUIdx];
LU.AllFixupsOutsideLoop &= LF.isUseFullyOutsideLoop(L);
+ if (!LU.WidestFixupType ||
+ SE.getTypeSizeInBits(LU.WidestFixupType) <
+ SE.getTypeSizeInBits(LF.OperandValToReplace->getType()))
+ LU.WidestFixupType = LF.OperandValToReplace->getType();
// If this is the first use of this LSRUse, give it a formula.
if (LU.Formulae.empty()) {
@@ -2195,6 +2210,10 @@
LF.Offset = P.second;
LSRUse &LU = Uses[LF.LUIdx];
LU.AllFixupsOutsideLoop &= LF.isUseFullyOutsideLoop(L);
+ if (!LU.WidestFixupType ||
+ SE.getTypeSizeInBits(LU.WidestFixupType) <
+ SE.getTypeSizeInBits(LF.OperandValToReplace->getType()))
+ LU.WidestFixupType = LF.OperandValToReplace->getType();
InsertSupplementalFormula(U, LU, LF.LUIdx);
CountRegisters(LU.Formulae.back(), Uses.size() - 1);
break;
@@ -2362,7 +2381,7 @@
Formula Base) {
// TODO: For now, just add the min and max offset, because it usually isn't
// worthwhile looking at everything inbetween.
- SmallVector<int64_t, 4> Worklist;
+ SmallVector<int64_t, 2> Worklist;
Worklist.push_back(LU.MinOffset);
if (LU.MaxOffset != LU.MinOffset)
Worklist.push_back(LU.MaxOffset);
@@ -2376,7 +2395,14 @@
F.AM.BaseOffs = (uint64_t)Base.AM.BaseOffs - *I;
if (isLegalUse(F.AM, LU.MinOffset - *I, LU.MaxOffset - *I,
LU.Kind, LU.AccessTy, TLI)) {
- F.BaseRegs[i] = SE.getAddExpr(G, SE.getConstant(G->getType(), *I));
+ // Add the offset to the base register.
+ const SCEV *NewG = SE.getAddExpr(G, SE.getConstant(G->getType(), *I));
+ // If it cancelled out, drop the base register, otherwise update it.
+ if (NewG->isZero()) {
+ std::swap(F.BaseRegs[i], F.BaseRegs.back());
+ F.BaseRegs.pop_back();
+ } else
+ F.BaseRegs[i] = NewG;
(void)InsertFormula(LU, LUIdx, F);
}
@@ -2981,7 +3007,7 @@
if (Fixup.LUIdx == LUIdx) {
Fixup.LUIdx = LUThatHas - &Uses.front();
Fixup.Offset += F.AM.BaseOffs;
- DEBUG(errs() << "New fixup has offset "
+ DEBUG(dbgs() << "New fixup has offset "
<< Fixup.Offset << '\n');
}
if (Fixup.LUIdx == NumUses-1)
@@ -3717,8 +3743,8 @@
}
char LoopStrengthReduce::ID = 0;
-static RegisterPass<LoopStrengthReduce>
-X("loop-reduce", "Loop Strength Reduction");
+INITIALIZE_PASS(LoopStrengthReduce, "loop-reduce",
+ "Loop Strength Reduction", false, false);
Pass *llvm::createLoopStrengthReducePass(const TargetLowering *TLI) {
return new LoopStrengthReduce(TLI);
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnrollPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnrollPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnrollPass.cpp Sat Jul 31 19:59:02 2010
@@ -17,6 +17,7 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Analysis/InlineCost.h"
+#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -55,23 +56,25 @@
/// loop preheaders be inserted into the CFG...
///
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<LoopInfo>();
+ AU.addPreserved<LoopInfo>();
AU.addRequiredID(LoopSimplifyID);
+ AU.addPreservedID(LoopSimplifyID);
AU.addRequiredID(LCSSAID);
- AU.addRequired<LoopInfo>();
AU.addPreservedID(LCSSAID);
- AU.addPreserved<LoopInfo>();
// FIXME: Loop unroll requires LCSSA. And LCSSA requires dom info.
// If loop unroll does not preserve dom info then LCSSA pass on next
// loop will receive invalid dom info.
// For now, recreate dom info, if loop is unrolled.
AU.addPreserved<DominatorTree>();
AU.addPreserved<DominanceFrontier>();
+ AU.addPreserved<ScalarEvolution>();
}
};
}
char LoopUnroll::ID = 0;
-static RegisterPass<LoopUnroll> X("loop-unroll", "Unroll loops");
+INITIALIZE_PASS(LoopUnroll, "loop-unroll", "Unroll loops", false, false);
Pass *llvm::createLoopUnrollPass() { return new LoopUnroll(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/LoopUnswitch.cpp Sat Jul 31 19:59:02 2010
@@ -160,7 +160,7 @@
};
}
char LoopUnswitch::ID = 0;
-static RegisterPass<LoopUnswitch> X("loop-unswitch", "Unswitch loops");
+INITIALIZE_PASS(LoopUnswitch, "loop-unswitch", "Unswitch loops", false, false);
Pass *llvm::createLoopUnswitchPass(bool Os) {
return new LoopUnswitch(Os);
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/MemCpyOptimizer.cpp Sat Jul 31 19:59:02 2010
@@ -331,8 +331,7 @@
// createMemCpyOptPass - The public interface to this file...
FunctionPass *llvm::createMemCpyOptPass() { return new MemCpyOpt(); }
-static RegisterPass<MemCpyOpt> X("memcpyopt",
- "MemCpy Optimization");
+INITIALIZE_PASS(MemCpyOpt, "memcpyopt", "MemCpy Optimization", false, false);
@@ -374,7 +373,7 @@
// If the call is readnone, ignore it, otherwise bail out. We don't even
// allow readonly here because we don't want something like:
// A[1] = 2; strlen(A); A[2] = 2; -> memcpy(A, ...); strlen(A).
- if (AA.getModRefBehavior(CallSite::get(BI)) ==
+ if (AA.getModRefBehavior(CallSite(BI)) ==
AliasAnalysis::DoesNotAccessMemory)
continue;
@@ -509,7 +508,7 @@
// because we'll need to do type comparisons based on the underlying type.
Value *cpyDest = cpy->getDest();
Value *cpySrc = cpy->getSource();
- CallSite CS = CallSite::get(C);
+ CallSite CS(C);
// We need to be able to reason about the size of the memcpy, so we require
// that it be a constant.
@@ -637,10 +636,11 @@
return true;
}
-/// processMemCpy - perform simplication of memcpy's. If we have memcpy A which
-/// copies X to Y, and memcpy B which copies Y to Z, then we can rewrite B to be
-/// a memcpy from X to Z (or potentially a memmove, depending on circumstances).
-/// This allows later passes to remove the first memcpy altogether.
+/// processMemCpy - perform simplification of memcpy's. If we have memcpy A
+/// which copies X to Y, and memcpy B which copies Y to Z, then we can rewrite
+/// B to be a memcpy from X to Z (or potentially a memmove, depending on
+/// circumstances). This allows later passes to remove the first memcpy
+/// altogether.
bool MemCpyOpt::processMemCpy(MemCpyInst *M) {
MemoryDependenceAnalysis &MD = getAnalysis<MemoryDependenceAnalysis>();
@@ -744,7 +744,8 @@
const Type *ArgTys[3] = { M->getRawDest()->getType(),
M->getRawSource()->getType(),
M->getLength()->getType() };
- M->setCalledFunction(Intrinsic::getDeclaration(Mod, Intrinsic::memcpy, ArgTys, 3));
+ M->setCalledFunction(Intrinsic::getDeclaration(Mod, Intrinsic::memcpy,
+ ArgTys, 3));
// MemDep may have over conservative information about this instruction, just
// conservatively flush it from the cache.
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/Reassociate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/Reassociate.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/Reassociate.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/Reassociate.cpp Sat Jul 31 19:59:02 2010
@@ -103,7 +103,8 @@
}
char Reassociate::ID = 0;
-static RegisterPass<Reassociate> X("reassociate", "Reassociate expressions");
+INITIALIZE_PASS(Reassociate, "reassociate",
+ "Reassociate expressions", false, false);
// Public interface to the Reassociate pass
FunctionPass *llvm::createReassociatePass() { return new Reassociate(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/SCCP.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/SCCP.cpp Sat Jul 31 19:59:02 2010
@@ -508,10 +508,10 @@
void visitLoadInst (LoadInst &I);
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitCallInst (CallInst &I) {
- visitCallSite(CallSite::get(&I));
+ visitCallSite(&I);
}
void visitInvokeInst (InvokeInst &II) {
- visitCallSite(CallSite::get(&II));
+ visitCallSite(&II);
visitTerminatorInst(II);
}
void visitCallSite (CallSite CS);
@@ -1600,8 +1600,8 @@
} // end anonymous namespace
char SCCP::ID = 0;
-static RegisterPass<SCCP>
-X("sccp", "Sparse Conditional Constant Propagation");
+INITIALIZE_PASS(SCCP, "sccp",
+ "Sparse Conditional Constant Propagation", false, false);
// createSCCPPass - This is the public interface to this file.
FunctionPass *llvm::createSCCPPass() {
@@ -1708,8 +1708,9 @@
} // end anonymous namespace
char IPSCCP::ID = 0;
-static RegisterPass<IPSCCP>
-Y("ipsccp", "Interprocedural Sparse Conditional Constant Propagation");
+INITIALIZE_PASS(IPSCCP, "ipsccp",
+ "Interprocedural Sparse Conditional Constant Propagation",
+ false, false);
// createIPSCCPPass - This is the public interface to this file.
ModulePass *llvm::createIPSCCPPass() {
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/ScalarReplAggregates.cpp Sat Jul 31 19:59:02 2010
@@ -135,7 +135,8 @@
}
char SROA::ID = 0;
-static RegisterPass<SROA> X("scalarrepl", "Scalar Replacement of Aggregates");
+INITIALIZE_PASS(SROA, "scalarrepl",
+ "Scalar Replacement of Aggregates", false, false);
// Public interface to the ScalarReplAggregates pass
FunctionPass *llvm::createScalarReplAggregatesPass(signed int Threshold) {
@@ -969,7 +970,7 @@
ConstantInt *Length = dyn_cast<ConstantInt>(MI->getLength());
if (Length)
isSafeMemAccess(AI, Offset, Length->getZExtValue(), 0,
- UI.getOperandNo() == CallInst::ArgOffset, Info);
+ UI.getOperandNo() == 0, Info);
else
MarkUnsafe(Info);
} else if (LoadInst *LI = dyn_cast<LoadInst>(User)) {
@@ -1787,7 +1788,7 @@
if (isOffset) return false;
// If the memintrinsic isn't using the alloca as the dest, reject it.
- if (UI.getOperandNo() != CallInst::ArgOffset) return false;
+ if (UI.getOperandNo() != 0) return false;
// If the source of the memcpy/move is not a constant global, reject it.
if (!PointsToConstantGlobal(MI->getSource()))
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyCFGPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyCFGPass.cpp Sat Jul 31 19:59:02 2010
@@ -49,7 +49,8 @@
}
char CFGSimplifyPass::ID = 0;
-static RegisterPass<CFGSimplifyPass> X("simplifycfg", "Simplify the CFG");
+INITIALIZE_PASS(CFGSimplifyPass, "simplifycfg",
+ "Simplify the CFG", false, false);
// Public interface to the CFGSimplification pass
FunctionPass *llvm::createCFGSimplificationPass() {
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyHalfPowrLibCalls.cpp Sat Jul 31 19:59:02 2010
@@ -46,8 +46,8 @@
char SimplifyHalfPowrLibCalls::ID = 0;
} // end anonymous namespace.
-static RegisterPass<SimplifyHalfPowrLibCalls>
-X("simplify-libcalls-halfpowr", "Simplify half_powr library calls");
+INITIALIZE_PASS(SimplifyHalfPowrLibCalls, "simplify-libcalls-halfpowr",
+ "Simplify half_powr library calls", false, false);
// Public interface to the Simplify HalfPowr LibCalls pass.
FunctionPass *llvm::createSimplifyHalfPowrLibCallsPass() {
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/SimplifyLibCalls.cpp Sat Jul 31 19:59:02 2010
@@ -532,7 +532,7 @@
StrLen, B, TD);
for (Value::use_iterator UI = CI->use_begin(), UE = CI->use_end();
UI != UE; ) {
- ICmpInst *Old = cast<ICmpInst>(UI++);
+ ICmpInst *Old = cast<ICmpInst>(*UI++);
Value *Cmp = B.CreateICmp(Old->getPredicate(), StrNCmp,
ConstantInt::getNullValue(StrNCmp->getType()),
"cmp");
@@ -566,8 +566,8 @@
// fold strstr(x, "y") -> strchr(x, 'y').
if (HasStr2 && ToFindStr.size() == 1)
- return B.CreateBitCast(EmitStrChr(CI->getArgOperand(0), ToFindStr[0], B, TD),
- CI->getType());
+ return B.CreateBitCast(EmitStrChr(CI->getArgOperand(0),
+ ToFindStr[0], B, TD), CI->getType());
return 0;
}
};
@@ -681,8 +681,8 @@
return 0;
// memset(p, v, n) -> llvm.memset(p, v, n, 1)
- Value *Val = B.CreateIntCast(CI->getArgOperand(1), Type::getInt8Ty(*Context),
- false);
+ Value *Val = B.CreateIntCast(CI->getArgOperand(1),
+ Type::getInt8Ty(*Context), false);
EmitMemSet(CI->getArgOperand(0), Val, CI->getArgOperand(2), false, B, TD);
return CI->getArgOperand(0);
}
@@ -1042,9 +1042,9 @@
if (!TD) return 0;
// sprintf(str, fmt) -> llvm.memcpy(str, fmt, strlen(fmt)+1, 1)
- EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1), // Copy the nul byte.
- ConstantInt::get(TD->getIntPtrType(*Context),
- FormatStr.size()+1), 1, false, B, TD);
+ EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1), // Copy the
+ ConstantInt::get(TD->getIntPtrType(*Context), // nul byte.
+ FormatStr.size() + 1), 1, false, B, TD);
return ConstantInt::get(CI->getType(), FormatStr.size());
}
@@ -1080,7 +1080,8 @@
Value *IncLen = B.CreateAdd(Len,
ConstantInt::get(Len->getType(), 1),
"leninc");
- EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(2), IncLen, 1, false, B, TD);
+ EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(2),
+ IncLen, 1, false, B, TD);
// The sprintf result is the unincremented number of bytes in the string.
return B.CreateIntCast(Len, CI->getType(), false);
@@ -1253,8 +1254,8 @@
char SimplifyLibCalls::ID = 0;
} // end anonymous namespace.
-static RegisterPass<SimplifyLibCalls>
-X("simplify-libcalls", "Simplify well-known library calls");
+INITIALIZE_PASS(SimplifyLibCalls, "simplify-libcalls",
+ "Simplify well-known library calls", false, false);
// Public interface to the Simplify LibCalls pass.
FunctionPass *llvm::createSimplifyLibCallsPass() {
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/Sink.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/Sink.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/Sink.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/Sink.cpp Sat Jul 31 19:59:02 2010
@@ -56,8 +56,7 @@
} // end anonymous namespace
char Sinking::ID = 0;
-static RegisterPass<Sinking>
-X("sink", "Code sinking");
+INITIALIZE_PASS(Sinking, "sink", "Code sinking", false, false);
FunctionPass *llvm::createSinkingPass() { return new Sinking(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/TailDuplication.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/TailDuplication.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/TailDuplication.cpp Sat Jul 31 19:59:02 2010
@@ -59,7 +59,7 @@
}
char TailDup::ID = 0;
-static RegisterPass<TailDup> X("tailduplicate", "Tail Duplication");
+INITIALIZE_PASS(TailDup, "tailduplicate", "Tail Duplication", false, false);
// Public interface to the Tail Duplication pass
FunctionPass *llvm::createTailDuplicationPass() { return new TailDup(); }
Modified: llvm/branches/wendling/eh/lib/Transforms/Scalar/TailRecursionElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Scalar/TailRecursionElimination.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Scalar/TailRecursionElimination.cpp Sat Jul 31 19:59:02 2010
@@ -87,7 +87,8 @@
}
char TailCallElim::ID = 0;
-static RegisterPass<TailCallElim> X("tailcallelim", "Tail Call Elimination");
+INITIALIZE_PASS(TailCallElim, "tailcallelim",
+ "Tail Call Elimination", false, false);
// Public interface to the TailCallElimination pass
FunctionPass *llvm::createTailCallEliminationPass() {
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/BasicInliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/BasicInliner.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/BasicInliner.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/BasicInliner.cpp Sat Jul 31 19:59:02 2010
@@ -82,8 +82,8 @@
Function *F = *FI;
for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB)
for (BasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
- CallSite CS = CallSite::get(I);
- if (CS.getInstruction() && CS.getCalledFunction()
+ CallSite CS(cast<Value>(I));
+ if (CS && CS.getCalledFunction()
&& !CS.getCalledFunction()->isDeclaration())
CallSites.push_back(CS);
}
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/BreakCriticalEdges.cpp Sat Jul 31 19:59:02 2010
@@ -225,7 +225,7 @@
for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
UI != E; ) {
Value::use_iterator Use = UI++;
- if (PHINode *PN = dyn_cast<PHINode>(Use)) {
+ if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
// Remove one entry from each PHI.
if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
PN->setOperand(Use.getOperandNo(), NewBB);
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/BuildLibCalls.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/BuildLibCalls.cpp Sat Jul 31 19:59:02 2010
@@ -421,9 +421,9 @@
FT->getParamType(3) != TD->getIntPtrType(Context))
return false;
- if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
- EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2),
- 1, false, B, TD);
+ if (isFoldable(3, 2, false)) {
+ EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1),
+ CI->getArgOperand(2), 1, false, B, TD);
replaceCall(CI->getArgOperand(0));
return true;
}
@@ -444,9 +444,9 @@
FT->getParamType(3) != TD->getIntPtrType(Context))
return false;
- if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
- EmitMemMove(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2),
- 1, false, B, TD);
+ if (isFoldable(3, 2, false)) {
+ EmitMemMove(CI->getArgOperand(0), CI->getArgOperand(1),
+ CI->getArgOperand(2), 1, false, B, TD);
replaceCall(CI->getArgOperand(0));
return true;
}
@@ -462,10 +462,11 @@
FT->getParamType(3) != TD->getIntPtrType(Context))
return false;
- if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+ if (isFoldable(3, 2, false)) {
Value *Val = B.CreateIntCast(CI->getArgOperand(1), B.getInt8Ty(),
false);
- EmitMemSet(CI->getArgOperand(0), Val, CI->getArgOperand(2), false, B, TD);
+ EmitMemSet(CI->getArgOperand(0), Val, CI->getArgOperand(2),
+ false, B, TD);
replaceCall(CI->getArgOperand(0));
return true;
}
@@ -487,7 +488,7 @@
// st[rp]cpy_chk call which may fail at runtime if the size is too long.
// TODO: It might be nice to get a maximum length out of the possible
// string lengths for varying.
- if (isFoldable(2 + CallInst::ArgOffset, 1 + CallInst::ArgOffset, true)) {
+ if (isFoldable(2, 1, true)) {
Value *Ret = EmitStrCpy(CI->getArgOperand(0), CI->getArgOperand(1), B, TD,
Name.substr(2, 6));
replaceCall(Ret);
@@ -505,7 +506,7 @@
FT->getParamType(3) != TD->getIntPtrType(Context))
return false;
- if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+ if (isFoldable(3, 2, false)) {
Value *Ret = EmitStrNCpy(CI->getArgOperand(0), CI->getArgOperand(1),
CI->getArgOperand(2), B, TD, Name.substr(2, 7));
replaceCall(Ret);
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/CloneFunction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/CloneFunction.cpp Sat Jul 31 19:59:02 2010
@@ -334,25 +334,16 @@
Ops.size(), TD);
}
-static MDNode *UpdateInlinedAtInfo(MDNode *InsnMD, MDNode *TheCallMD) {
- DILocation ILoc(InsnMD);
- if (!ILoc.Verify()) return InsnMD;
-
- DILocation CallLoc(TheCallMD);
- if (!CallLoc.Verify()) return InsnMD;
-
- DILocation OrigLocation = ILoc.getOrigLocation();
- MDNode *NewLoc = TheCallMD;
- if (OrigLocation.Verify())
- NewLoc = UpdateInlinedAtInfo(OrigLocation, TheCallMD);
-
- Value *MDVs[] = {
- InsnMD->getOperand(0), // Line
- InsnMD->getOperand(1), // Col
- InsnMD->getOperand(2), // Scope
- NewLoc
- };
- return MDNode::get(InsnMD->getContext(), MDVs, 4);
+static DebugLoc
+UpdateInlinedAtInfo(const DebugLoc &InsnDL, const DebugLoc &TheCallDL,
+ LLVMContext &Ctx) {
+ DebugLoc NewLoc = TheCallDL;
+ if (MDNode *IA = InsnDL.getInlinedAt(Ctx))
+ NewLoc = UpdateInlinedAtInfo(DebugLoc::getFromDILocation(IA), TheCallDL,
+ Ctx);
+
+ return DebugLoc::get(InsnDL.getLine(), InsnDL.getCol(),
+ InsnDL.getScope(Ctx), NewLoc.getAsMDNode(Ctx));
}
/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,
@@ -408,10 +399,9 @@
//
BasicBlock::iterator I = NewBB->begin();
- unsigned DbgKind = OldFunc->getContext().getMDKindID("dbg");
- MDNode *TheCallMD = NULL;
- if (TheCall && TheCall->hasMetadata())
- TheCallMD = TheCall->getMetadata(DbgKind);
+ DebugLoc TheCallDL;
+ if (TheCall)
+ TheCallDL = TheCall->getDebugLoc();
// Handle PHI nodes specially, as we have to remove references to dead
// blocks.
@@ -420,15 +410,17 @@
BasicBlock::const_iterator OldI = BI->begin();
for (; (PN = dyn_cast<PHINode>(I)); ++I, ++OldI) {
if (I->hasMetadata()) {
- if (TheCallMD) {
- if (MDNode *IMD = I->getMetadata(DbgKind)) {
- MDNode *NewMD = UpdateInlinedAtInfo(IMD, TheCallMD);
- I->setMetadata(DbgKind, NewMD);
+ if (!TheCallDL.isUnknown()) {
+ DebugLoc IDL = I->getDebugLoc();
+ if (!IDL.isUnknown()) {
+ DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL,
+ I->getContext());
+ I->setDebugLoc(NewDL);
}
} else {
// The cloned instruction has dbg info but the call instruction
// does not have dbg info. Remove dbg info from cloned instruction.
- I->setMetadata(DbgKind, 0);
+ I->setDebugLoc(DebugLoc());
}
}
PHIToResolve.push_back(cast<PHINode>(OldI));
@@ -444,15 +436,17 @@
// Otherwise, remap the rest of the instructions normally.
for (; I != NewBB->end(); ++I) {
if (I->hasMetadata()) {
- if (TheCallMD) {
- if (MDNode *IMD = I->getMetadata(DbgKind)) {
- MDNode *NewMD = UpdateInlinedAtInfo(IMD, TheCallMD);
- I->setMetadata(DbgKind, NewMD);
+ if (!TheCallDL.isUnknown()) {
+ DebugLoc IDL = I->getDebugLoc();
+ if (!IDL.isUnknown()) {
+ DebugLoc NewDL = UpdateInlinedAtInfo(IDL, TheCallDL,
+ I->getContext());
+ I->setDebugLoc(NewDL);
}
} else {
// The cloned instruction has dbg info but the call instruction
// does not have dbg info. Remove dbg info from cloned instruction.
- I->setMetadata(DbgKind, 0);
+ I->setDebugLoc(DebugLoc());
}
}
RemapInstruction(I, VMap);
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/CloneModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/CloneModule.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/CloneModule.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/CloneModule.cpp Sat Jul 31 19:59:02 2010
@@ -127,11 +127,9 @@
for (Module::const_named_metadata_iterator I = M->named_metadata_begin(),
E = M->named_metadata_end(); I != E; ++I) {
const NamedMDNode &NMD = *I;
- SmallVector<MDNode*, 4> MDs;
+ NamedMDNode *NewNMD = New->getOrInsertNamedMetadata(NMD.getName());
for (unsigned i = 0, e = NMD.getNumOperands(); i != e; ++i)
- MDs.push_back(cast<MDNode>(MapValue(NMD.getOperand(i), VMap)));
- NamedMDNode::Create(New->getContext(), NMD.getName(),
- MDs.data(), MDs.size(), New);
+ NewNMD->addOperand(cast<MDNode>(MapValue(NMD.getOperand(i), VMap)));
}
// Update metadata attach with instructions.
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/InlineFunction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/InlineFunction.cpp Sat Jul 31 19:59:02 2010
@@ -216,12 +216,12 @@
if (I->second->getFunction() == 0)
if (Function *F = CallSite(NewCall).getCalledFunction()) {
// Indirect call site resolved to direct call.
- CallerNode->addCalledFunction(CallSite::get(NewCall), CG[F]);
-
+ CallerNode->addCalledFunction(CallSite(NewCall), CG[F]);
+
continue;
}
-
- CallerNode->addCalledFunction(CallSite::get(NewCall), I->second);
+
+ CallerNode->addCalledFunction(CallSite(NewCall), I->second);
}
// Update the call graph by deleting the edge from Callee to Caller. We must
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/LCSSA.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/LCSSA.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/LCSSA.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/LCSSA.cpp Sat Jul 31 19:59:02 2010
@@ -64,22 +64,13 @@
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
- // LCSSA doesn't actually require LoopSimplify, but the PassManager
- // doesn't know how to schedule LoopSimplify by itself.
- AU.addRequiredID(LoopSimplifyID);
- AU.addPreservedID(LoopSimplifyID);
- AU.addRequiredTransitive<LoopInfo>();
- AU.addPreserved<LoopInfo>();
- AU.addRequiredTransitive<DominatorTree>();
- AU.addPreserved<ScalarEvolution>();
+ AU.addRequired<DominatorTree>();
AU.addPreserved<DominatorTree>();
-
- // Request DominanceFrontier now, even though LCSSA does
- // not use it. This allows Pass Manager to schedule Dominance
- // Frontier early enough such that one LPPassManager can handle
- // multiple loop transformation passes.
- AU.addRequired<DominanceFrontier>();
AU.addPreserved<DominanceFrontier>();
+ AU.addRequired<LoopInfo>();
+ AU.addPreserved<LoopInfo>();
+ AU.addPreservedID(LoopSimplifyID);
+ AU.addPreserved<ScalarEvolution>();
}
private:
bool ProcessInstruction(Instruction *Inst,
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/Local.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/Local.cpp Sat Jul 31 19:59:02 2010
@@ -306,7 +306,7 @@
WeakVH BIHandle(BI);
ReplaceAndSimplifyAllUses(Inst, V, TD);
MadeChange = true;
- if (BIHandle == 0)
+ if (BIHandle != BI)
BI = BB->begin();
continue;
}
@@ -354,12 +354,13 @@
// value into all of its uses.
assert(PNV != PN && "hasConstantValue broken");
+ Value *OldPhiIt = PhiIt;
ReplaceAndSimplifyAllUses(PN, PNV, TD);
// If recursive simplification ended up deleting the next PHI node we would
// iterate to, then our iterator is invalid, restart scanning from the top
// of the block.
- if (PhiIt == 0) PhiIt = &BB->front();
+ if (PhiIt != OldPhiIt) PhiIt = &BB->front();
}
}
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/LoopSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/LoopSimplify.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/LoopSimplify.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/LoopSimplify.cpp Sat Jul 31 19:59:02 2010
@@ -77,15 +77,17 @@
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
// We need loop information to identify the loops...
- AU.addRequiredTransitive<LoopInfo>();
- AU.addRequiredTransitive<DominatorTree>();
+ AU.addRequired<DominatorTree>();
+ AU.addPreserved<DominatorTree>();
+ AU.addRequired<LoopInfo>();
AU.addPreserved<LoopInfo>();
- AU.addPreserved<DominatorTree>();
- AU.addPreserved<DominanceFrontier>();
+
AU.addPreserved<AliasAnalysis>();
AU.addPreserved<ScalarEvolution>();
AU.addPreservedID(BreakCriticalEdgesID); // No critical edges added.
+ AU.addPreserved<DominanceFrontier>();
+ AU.addPreservedID(LCSSAID);
}
/// verifyAnalysis() - Verify LoopSimplifyForm's guarantees.
@@ -141,15 +143,16 @@
BB != E; ++BB) {
if (*BB == L->getHeader()) continue;
- SmallPtrSet<BasicBlock *, 4> BadPreds;
- for (pred_iterator PI = pred_begin(*BB), PE = pred_end(*BB); PI != PE; ++PI){
+ SmallPtrSet<BasicBlock*, 4> BadPreds;
+ for (pred_iterator PI = pred_begin(*BB),
+ PE = pred_end(*BB); PI != PE; ++PI) {
BasicBlock *P = *PI;
if (!L->contains(P))
BadPreds.insert(P);
}
// Delete each unique out-of-loop (and thus dead) predecessor.
- for (SmallPtrSet<BasicBlock *, 4>::iterator I = BadPreds.begin(),
+ for (SmallPtrSet<BasicBlock*, 4>::iterator I = BadPreds.begin(),
E = BadPreds.end(); I != E; ++I) {
DEBUG(dbgs() << "LoopSimplify: Deleting edge from dead predecessor ";
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/LoopUnroll.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/LoopUnroll.cpp Sat Jul 31 19:59:02 2010
@@ -24,6 +24,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/LoopPass.h"
+#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -127,6 +128,11 @@
return false;
}
+ // Notify ScalarEvolution that the loop will be substantially changed,
+ // if not outright eliminated.
+ if (ScalarEvolution *SE = LPM->getAnalysisIfAvailable<ScalarEvolution>())
+ SE->forgetLoop(L);
+
// Find trip count
unsigned TripCount = L->getSmallConstantTripCount();
// Find trip multiple if count is not available
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/PromoteMemoryToRegister.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/PromoteMemoryToRegister.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/PromoteMemoryToRegister.cpp Sat Jul 31 19:59:02 2010
@@ -896,11 +896,12 @@
DIVar, SI);
// Propagate any debug metadata from the store onto the dbg.value.
- if (MDNode *SIMD = SI->getMetadata("dbg"))
- DbgVal->setMetadata("dbg", SIMD);
+ DebugLoc SIDL = SI->getDebugLoc();
+ if (!SIDL.isUnknown())
+ DbgVal->setDebugLoc(SIDL);
// Otherwise propagate debug metadata from dbg.declare.
- else if (MDNode *MD = DDI->getMetadata("dbg"))
- DbgVal->setMetadata("dbg", MD);
+ else
+ DbgVal->setDebugLoc(DDI->getDebugLoc());
}
// QueuePhiNode - queues a phi-node to be added to a basic-block for a specific
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/SSI.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/SSI.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/SSI.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/SSI.cpp Sat Jul 31 19:59:02 2010
@@ -80,12 +80,12 @@
for (Value::use_iterator begin = (*I)->use_begin(),
end = (*I)->use_end(); begin != end; ++begin) {
// Test if the Use of the Value is in a comparator
- if (CmpInst *CI = dyn_cast<CmpInst>(begin)) {
+ if (CmpInst *CI = dyn_cast<CmpInst>(*begin)) {
// Iterates through all uses of CmpInst
for (Value::use_iterator begin_ci = CI->use_begin(),
end_ci = CI->use_end(); begin_ci != end_ci; ++begin_ci) {
// Test if any use of CmpInst is in a Terminator
- if (TerminatorInst *TI = dyn_cast<TerminatorInst>(begin_ci)) {
+ if (TerminatorInst *TI = dyn_cast<TerminatorInst>(*begin_ci)) {
insertSigma(TI, *I);
}
}
@@ -391,7 +391,8 @@
FunctionPass *llvm::createSSIPass() { return new SSI(); }
char SSI::ID = 0;
-static RegisterPass<SSI> X("ssi", "Static Single Information Construction");
+INITIALIZE_PASS(SSI, "ssi",
+ "Static Single Information Construction", false, false);
/// SSIEverything - A pass that runs createSSI on every non-void variable,
/// intended for debugging.
@@ -428,5 +429,5 @@
FunctionPass *llvm::createSSIEverythingPass() { return new SSIEverything(); }
char SSIEverything::ID = 0;
-static RegisterPass<SSIEverything>
-Y("ssi-everything", "Static Single Information Construction");
+INITIALIZE_PASS(SSIEverything, "ssi-everything",
+ "Static Single Information Construction", false, false);
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/SimplifyCFG.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/SimplifyCFG.cpp Sat Jul 31 19:59:02 2010
@@ -949,7 +949,7 @@
UI != E; ++UI) {
// Ignore any user that is not a PHI node in BB2. These can only occur in
// unreachable blocks, because they would not be dominated by the instr.
- PHINode *PN = dyn_cast<PHINode>(UI);
+ PHINode *PN = dyn_cast<PHINode>(*UI);
if (!PN || PN->getParent() != BB2)
return false;
PHIUses.push_back(PN);
@@ -1395,9 +1395,8 @@
// register pressure or inhibit out-of-order execution.
Instruction *BonusInst = 0;
if (&*FrontIt != Cond &&
- (*FrontIt).hasOneUse() && *(*FrontIt).use_begin() == Cond &&
- (*FrontIt).isSafeToSpeculativelyExecute() &&
- !(*FrontIt).mayReadFromMemory()) {
+ FrontIt->hasOneUse() && *FrontIt->use_begin() == Cond &&
+ FrontIt->isSafeToSpeculativelyExecute()) {
BonusInst = &*FrontIt;
++FrontIt;
}
Modified: llvm/branches/wendling/eh/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp (original)
+++ llvm/branches/wendling/eh/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp Sat Jul 31 19:59:02 2010
@@ -24,8 +24,8 @@
using namespace llvm;
char UnifyFunctionExitNodes::ID = 0;
-static RegisterPass<UnifyFunctionExitNodes>
-X("mergereturn", "Unify function exit nodes");
+INITIALIZE_PASS(UnifyFunctionExitNodes, "mergereturn",
+ "Unify function exit nodes", false, false);
Pass *llvm::createUnifyFunctionExitNodesPass() {
return new UnifyFunctionExitNodes();
Modified: llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/AsmWriter.cpp Sat Jul 31 19:59:02 2010
@@ -63,8 +63,6 @@
if (const GlobalValue *GV = dyn_cast<GlobalValue>(V))
return GV->getParent();
- if (const NamedMDNode *NMD = dyn_cast<NamedMDNode>(V))
- return NMD->getParent();
return 0;
}
@@ -581,8 +579,12 @@
if (const Function *Func = dyn_cast<Function>(V))
return new SlotTracker(Func);
- if (isa<MDNode>(V))
+ if (const MDNode *MD = dyn_cast<MDNode>(V)) {
+ if (!MD->isFunctionLocal())
+ return new SlotTracker(MD->getFunction());
+
return new SlotTracker((Function *)0);
+ }
return 0;
}
@@ -634,10 +636,8 @@
I = TheModule->named_metadata_begin(),
E = TheModule->named_metadata_end(); I != E; ++I) {
const NamedMDNode *NMD = I;
- for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
- if (MDNode *MD = NMD->getOperand(i))
- CreateMetadataSlot(MD);
- }
+ for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
+ CreateMetadataSlot(NMD->getOperand(i));
}
// Add all the unnamed functions to the table.
@@ -778,15 +778,14 @@
// Don't insert if N is a function-local metadata, these are always printed
// inline.
- if (N->isFunctionLocal())
- return;
-
- mdn_iterator I = mdnMap.find(N);
- if (I != mdnMap.end())
- return;
+ if (!N->isFunctionLocal()) {
+ mdn_iterator I = mdnMap.find(N);
+ if (I != mdnMap.end())
+ return;
- unsigned DestSlot = mdnNext++;
- mdnMap[N] = DestSlot;
+ unsigned DestSlot = mdnNext++;
+ mdnMap[N] = DestSlot;
+ }
// Recursively add any MDNodes referenced by operands.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
@@ -800,7 +799,8 @@
static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
TypePrinting *TypePrinter,
- SlotTracker *Machine);
+ SlotTracker *Machine,
+ const Module *Context);
@@ -856,7 +856,8 @@
static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
TypePrinting &TypePrinter,
- SlotTracker *Machine) {
+ SlotTracker *Machine,
+ const Module *Context) {
if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
if (CI->getType()->isIntegerTy(1)) {
Out << (CI->getZExtValue() ? "true" : "false");
@@ -972,9 +973,11 @@
if (const BlockAddress *BA = dyn_cast<BlockAddress>(CV)) {
Out << "blockaddress(";
- WriteAsOperandInternal(Out, BA->getFunction(), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, BA->getFunction(), &TypePrinter, Machine,
+ Context);
Out << ", ";
- WriteAsOperandInternal(Out, BA->getBasicBlock(), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, BA->getBasicBlock(), &TypePrinter, Machine,
+ Context);
Out << ")";
return;
}
@@ -994,12 +997,14 @@
TypePrinter.print(ETy, Out);
Out << ' ';
WriteAsOperandInternal(Out, CA->getOperand(0),
- &TypePrinter, Machine);
+ &TypePrinter, Machine,
+ Context);
for (unsigned i = 1, e = CA->getNumOperands(); i != e; ++i) {
Out << ", ";
TypePrinter.print(ETy, Out);
Out << ' ';
- WriteAsOperandInternal(Out, CA->getOperand(i), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CA->getOperand(i), &TypePrinter, Machine,
+ Context);
}
}
Out << ']';
@@ -1017,14 +1022,16 @@
TypePrinter.print(CS->getOperand(0)->getType(), Out);
Out << ' ';
- WriteAsOperandInternal(Out, CS->getOperand(0), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CS->getOperand(0), &TypePrinter, Machine,
+ Context);
for (unsigned i = 1; i < N; i++) {
Out << ", ";
TypePrinter.print(CS->getOperand(i)->getType(), Out);
Out << ' ';
- WriteAsOperandInternal(Out, CS->getOperand(i), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CS->getOperand(i), &TypePrinter, Machine,
+ Context);
}
Out << ' ';
}
@@ -1039,7 +1046,8 @@
Out << "{ ";
TypePrinter.print(CU->getOperand(0)->getType(), Out);
Out << ' ';
- WriteAsOperandInternal(Out, CU->getOperand(0), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CU->getOperand(0), &TypePrinter, Machine,
+ Context);
Out << " }";
return;
}
@@ -1051,12 +1059,14 @@
Out << '<';
TypePrinter.print(ETy, Out);
Out << ' ';
- WriteAsOperandInternal(Out, CP->getOperand(0), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CP->getOperand(0), &TypePrinter, Machine,
+ Context);
for (unsigned i = 1, e = CP->getNumOperands(); i != e; ++i) {
Out << ", ";
TypePrinter.print(ETy, Out);
Out << ' ';
- WriteAsOperandInternal(Out, CP->getOperand(i), &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, CP->getOperand(i), &TypePrinter, Machine,
+ Context);
}
Out << '>';
return;
@@ -1087,7 +1097,7 @@
for (User::const_op_iterator OI=CE->op_begin(); OI != CE->op_end(); ++OI) {
TypePrinter.print((*OI)->getType(), Out);
Out << ' ';
- WriteAsOperandInternal(Out, *OI, &TypePrinter, Machine);
+ WriteAsOperandInternal(Out, *OI, &TypePrinter, Machine, Context);
if (OI+1 != CE->op_end())
Out << ", ";
}
@@ -1112,7 +1122,8 @@
static void WriteMDNodeBodyInternal(raw_ostream &Out, const MDNode *Node,
TypePrinting *TypePrinter,
- SlotTracker *Machine) {
+ SlotTracker *Machine,
+ const Module *Context) {
Out << "!{";
for (unsigned mi = 0, me = Node->getNumOperands(); mi != me; ++mi) {
const Value *V = Node->getOperand(mi);
@@ -1122,7 +1133,7 @@
TypePrinter->print(V->getType(), Out);
Out << ' ';
WriteAsOperandInternal(Out, Node->getOperand(mi),
- TypePrinter, Machine);
+ TypePrinter, Machine, Context);
}
if (mi + 1 != me)
Out << ", ";
@@ -1138,7 +1149,8 @@
///
static void WriteAsOperandInternal(raw_ostream &Out, const Value *V,
TypePrinting *TypePrinter,
- SlotTracker *Machine) {
+ SlotTracker *Machine,
+ const Module *Context) {
if (V->hasName()) {
PrintLLVMName(Out, V);
return;
@@ -1147,7 +1159,7 @@
const Constant *CV = dyn_cast<Constant>(V);
if (CV && !isa<GlobalValue>(CV)) {
assert(TypePrinter && "Constants require TypePrinting!");
- WriteConstantInternal(Out, CV, *TypePrinter, Machine);
+ WriteConstantInternal(Out, CV, *TypePrinter, Machine, Context);
return;
}
@@ -1168,12 +1180,16 @@
if (const MDNode *N = dyn_cast<MDNode>(V)) {
if (N->isFunctionLocal()) {
// Print metadata inline, not via slot reference number.
- WriteMDNodeBodyInternal(Out, N, TypePrinter, Machine);
+ WriteMDNodeBodyInternal(Out, N, TypePrinter, Machine, Context);
return;
}
- if (!Machine)
- Machine = createSlotTracker(V);
+ if (!Machine) {
+ if (N->isFunctionLocal())
+ Machine = new SlotTracker(N->getFunction());
+ else
+ Machine = new SlotTracker(Context);
+ }
Out << '!' << Machine->getMetadataSlot(N);
return;
}
@@ -1227,8 +1243,9 @@
// Fast path: Don't construct and populate a TypePrinting object if we
// won't be needing any types printed.
if (!PrintType &&
- (!isa<Constant>(V) || V->hasName() || isa<GlobalValue>(V))) {
- WriteAsOperandInternal(Out, V, 0, 0);
+ ((!isa<Constant>(V) && !isa<MDNode>(V)) ||
+ V->hasName() || isa<GlobalValue>(V))) {
+ WriteAsOperandInternal(Out, V, 0, 0, Context);
return;
}
@@ -1242,7 +1259,7 @@
Out << ' ';
}
- WriteAsOperandInternal(Out, V, &TypePrinter, 0);
+ WriteAsOperandInternal(Out, V, &TypePrinter, 0, Context);
}
namespace {
@@ -1297,7 +1314,7 @@
TypePrinter.print(Operand->getType(), Out);
Out << ' ';
}
- WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine);
+ WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule);
}
void AssemblyWriter::writeParamOperand(const Value *Operand,
@@ -1314,7 +1331,7 @@
Out << ' ' << Attribute::getAsString(Attrs);
Out << ' ';
// Print the operand
- WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine);
+ WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule);
}
void AssemblyWriter::printModule(const Module *M) {
@@ -1403,10 +1420,7 @@
Out << "!" << NMD->getName() << " = !{";
for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
if (i) Out << ", ";
- if (MDNode *MD = NMD->getOperand(i))
- Out << '!' << Machine.getMetadataSlot(MD);
- else
- Out << "null";
+ Out << '!' << Machine.getMetadataSlot(NMD->getOperand(i));
}
Out << "}\n";
}
@@ -1451,7 +1465,7 @@
if (GV->isMaterializable())
Out << "; Materializable\n";
- WriteAsOperandInternal(Out, GV, &TypePrinter, &Machine);
+ WriteAsOperandInternal(Out, GV, &TypePrinter, &Machine, GV->getParent());
Out << " = ";
if (!GV->hasInitializer() && GV->hasExternalLinkage())
@@ -1510,7 +1524,7 @@
TypePrinter.print(F->getFunctionType(), Out);
Out << "* ";
- WriteAsOperandInternal(Out, F, &TypePrinter, &Machine);
+ WriteAsOperandInternal(Out, F, &TypePrinter, &Machine, F->getParent());
} else if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(Aliasee)) {
TypePrinter.print(GA->getType(), Out);
Out << ' ';
@@ -1593,7 +1607,7 @@
Out << Attribute::getAsString(Attrs.getRetAttributes()) << ' ';
TypePrinter.print(F->getReturnType(), Out);
Out << ' ';
- WriteAsOperandInternal(Out, F, &TypePrinter, &Machine);
+ WriteAsOperandInternal(Out, F, &TypePrinter, &Machine, F->getParent());
Out << '(';
Machine.incorporateFunction(F);
@@ -2055,7 +2069,9 @@
} else {
Out << ", !<unknown kind #" << Kind << ">";
}
- Out << " !" << Machine.getMetadataSlot(InstMD[i].second);
+ Out << ' ';
+ WriteAsOperandInternal(Out, InstMD[i].second, &TypePrinter, &Machine,
+ TheModule);
}
}
printInfoComment(I);
@@ -2103,7 +2119,7 @@
}
void AssemblyWriter::printMDNodeBody(const MDNode *Node) {
- WriteMDNodeBodyInternal(Out, Node, &TypePrinter, &Machine);
+ WriteMDNodeBodyInternal(Out, Node, &TypePrinter, &Machine, TheModule);
WriteMDNodeComment(Node, Out);
Out << "\n";
}
@@ -2119,6 +2135,13 @@
W.printModule(this);
}
+void NamedMDNode::print(raw_ostream &ROS, AssemblyAnnotationWriter *AAW) const {
+ SlotTracker SlotTable(getParent());
+ formatted_raw_ostream OS(ROS);
+ AssemblyWriter W(OS, SlotTable, getParent(), AAW);
+ W.printNamedMDNode(this);
+}
+
void Type::print(raw_ostream &OS) const {
if (this == 0) {
OS << "<null Type>";
@@ -2156,15 +2179,11 @@
SlotTracker SlotTable(F);
AssemblyWriter W(OS, SlotTable, F ? F->getParent() : 0, AAW);
W.printMDNodeBody(N);
- } else if (const NamedMDNode *N = dyn_cast<NamedMDNode>(this)) {
- SlotTracker SlotTable(N->getParent());
- AssemblyWriter W(OS, SlotTable, N->getParent(), AAW);
- W.printNamedMDNode(N);
} else if (const Constant *C = dyn_cast<Constant>(this)) {
TypePrinting TypePrinter;
TypePrinter.print(C->getType(), OS);
OS << ' ';
- WriteConstantInternal(OS, C, TypePrinter, 0);
+ WriteConstantInternal(OS, C, TypePrinter, 0, 0);
} else if (isa<InlineAsm>(this) || isa<MDString>(this) ||
isa<Argument>(this)) {
WriteAsOperand(OS, this, true, 0);
Modified: llvm/branches/wendling/eh/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/AutoUpgrade.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/AutoUpgrade.cpp Sat Jul 31 19:59:02 2010
@@ -398,7 +398,8 @@
SI = new ShuffleVectorInst(Op0, Op1, Mask, "upgraded.", CI);
} else if (isShufPD) {
Value *Op1 = CI->getArgOperand(1);
- unsigned MaskVal = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
+ unsigned MaskVal =
+ cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
Idxs.push_back(ConstantInt::get(Type::getInt32Ty(C), MaskVal & 1));
Idxs.push_back(ConstantInt::get(Type::getInt32Ty(C),
((MaskVal >> 1) & 1)+2));
Modified: llvm/branches/wendling/eh/lib/VMCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/lib/VMCore/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -23,6 +23,7 @@
Module.cpp
Pass.cpp
PassManager.cpp
+ PassRegistry.cpp
PrintModulePass.cpp
Type.cpp
TypeSymbolTable.cpp
Modified: llvm/branches/wendling/eh/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Constants.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Constants.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Constants.cpp Sat Jul 31 19:59:02 2010
@@ -956,14 +956,14 @@
/// destroyConstant - Remove the constant from the constant table...
///
void ConstantAggregateZero::destroyConstant() {
- getType()->getContext().pImpl->AggZeroConstants.remove(this);
+ getRawType()->getContext().pImpl->AggZeroConstants.remove(this);
destroyConstantImpl();
}
/// destroyConstant - Remove the constant from the constant table...
///
void ConstantArray::destroyConstant() {
- getType()->getContext().pImpl->ArrayConstants.remove(this);
+ getRawType()->getContext().pImpl->ArrayConstants.remove(this);
destroyConstantImpl();
}
@@ -1027,21 +1027,21 @@
// destroyConstant - Remove the constant from the constant table...
//
void ConstantStruct::destroyConstant() {
- getType()->getContext().pImpl->StructConstants.remove(this);
+ getRawType()->getContext().pImpl->StructConstants.remove(this);
destroyConstantImpl();
}
// destroyConstant - Remove the constant from the constant table...
//
void ConstantUnion::destroyConstant() {
- getType()->getContext().pImpl->UnionConstants.remove(this);
+ getRawType()->getContext().pImpl->UnionConstants.remove(this);
destroyConstantImpl();
}
// destroyConstant - Remove the constant from the constant table...
//
void ConstantVector::destroyConstant() {
- getType()->getContext().pImpl->VectorConstants.remove(this);
+ getRawType()->getContext().pImpl->VectorConstants.remove(this);
destroyConstantImpl();
}
@@ -1082,7 +1082,7 @@
// destroyConstant - Remove the constant from the constant table...
//
void ConstantPointerNull::destroyConstant() {
- getType()->getContext().pImpl->NullPtrConstants.remove(this);
+ getRawType()->getContext().pImpl->NullPtrConstants.remove(this);
destroyConstantImpl();
}
@@ -1097,7 +1097,7 @@
// destroyConstant - Remove the constant from the constant table.
//
void UndefValue::destroyConstant() {
- getType()->getContext().pImpl->UndefValueConstants.remove(this);
+ getRawType()->getContext().pImpl->UndefValueConstants.remove(this);
destroyConstantImpl();
}
@@ -1131,7 +1131,7 @@
// destroyConstant - Remove the constant from the constant table.
//
void BlockAddress::destroyConstant() {
- getFunction()->getType()->getContext().pImpl
+ getFunction()->getRawType()->getContext().pImpl
->BlockAddresses.erase(std::make_pair(getFunction(), getBasicBlock()));
getBasicBlock()->AdjustBlockAddressRefCount(-1);
destroyConstantImpl();
@@ -1930,7 +1930,7 @@
// destroyConstant - Remove the constant from the constant table...
//
void ConstantExpr::destroyConstant() {
- getType()->getContext().pImpl->ExprConstants.remove(this);
+ getRawType()->getContext().pImpl->ExprConstants.remove(this);
destroyConstantImpl();
}
@@ -1971,11 +1971,10 @@
assert(isa<Constant>(To) && "Cannot make Constant refer to non-constant!");
Constant *ToC = cast<Constant>(To);
- LLVMContext &Context = getType()->getContext();
- LLVMContextImpl *pImpl = Context.pImpl;
+ LLVMContextImpl *pImpl = getRawType()->getContext().pImpl;
std::pair<LLVMContextImpl::ArrayConstantsTy::MapKey, ConstantArray*> Lookup;
- Lookup.first.first = getType();
+ Lookup.first.first = cast<ArrayType>(getRawType());
Lookup.second = this;
std::vector<Constant*> &Values = Lookup.first.second;
@@ -2009,7 +2008,7 @@
Constant *Replacement = 0;
if (isAllZeros) {
- Replacement = ConstantAggregateZero::get(getType());
+ Replacement = ConstantAggregateZero::get(getRawType());
} else {
// Check to see if we have this array type already.
bool Exists;
@@ -2060,7 +2059,7 @@
assert(getOperand(OperandToUpdate) == From && "ReplaceAllUsesWith broken!");
std::pair<LLVMContextImpl::StructConstantsTy::MapKey, ConstantStruct*> Lookup;
- Lookup.first.first = getType();
+ Lookup.first.first = cast<StructType>(getRawType());
Lookup.second = this;
std::vector<Constant*> &Values = Lookup.first.second;
Values.reserve(getNumOperands()); // Build replacement struct.
@@ -2082,14 +2081,13 @@
}
Values[OperandToUpdate] = ToC;
- LLVMContext &Context = getType()->getContext();
- LLVMContextImpl *pImpl = Context.pImpl;
+ LLVMContextImpl *pImpl = getRawType()->getContext().pImpl;
Constant *Replacement = 0;
if (isAllZeros) {
- Replacement = ConstantAggregateZero::get(getType());
+ Replacement = ConstantAggregateZero::get(getRawType());
} else {
- // Check to see if we have this array type already.
+ // Check to see if we have this struct type already.
bool Exists;
LLVMContextImpl::StructConstantsTy::MapTy::iterator I =
pImpl->StructConstants.InsertOrGetItem(Lookup, Exists);
@@ -2128,16 +2126,15 @@
assert(getOperand(0) == From && "ReplaceAllUsesWith broken!");
std::pair<LLVMContextImpl::UnionConstantsTy::MapKey, ConstantUnion*> Lookup;
- Lookup.first.first = getType();
+ Lookup.first.first = cast<UnionType>(getRawType());
Lookup.second = this;
Lookup.first.second = ToC;
- LLVMContext &Context = getType()->getContext();
- LLVMContextImpl *pImpl = Context.pImpl;
+ LLVMContextImpl *pImpl = getRawType()->getContext().pImpl;
Constant *Replacement = 0;
if (ToC->isNullValue()) {
- Replacement = ConstantAggregateZero::get(getType());
+ Replacement = ConstantAggregateZero::get(getRawType());
} else {
// Check to see if we have this union type already.
bool Exists;
@@ -2180,7 +2177,7 @@
Values.push_back(Val);
}
- Constant *Replacement = get(getType(), Values);
+ Constant *Replacement = get(cast<VectorType>(getRawType()), Values);
assert(Replacement != this && "I didn't contain From!");
// Everyone using this now uses the replacement.
@@ -2227,7 +2224,7 @@
&Indices[0], Indices.size());
} else if (isCast()) {
assert(getOperand(0) == From && "Cast only has one use!");
- Replacement = ConstantExpr::getCast(getOpcode(), To, getType());
+ Replacement = ConstantExpr::getCast(getOpcode(), To, getRawType());
} else if (getOpcode() == Instruction::Select) {
Constant *C1 = getOperand(0);
Constant *C2 = getOperand(1);
Modified: llvm/branches/wendling/eh/lib/VMCore/ConstantsContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/ConstantsContext.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/ConstantsContext.h (original)
+++ llvm/branches/wendling/eh/lib/VMCore/ConstantsContext.h Sat Jul 31 19:59:02 2010
@@ -757,9 +757,13 @@
// If this constant is the representative element for its abstract type,
// update the AbstractTypeMap so that the representative element is I.
- if (C->getType()->isAbstract()) {
+ //
+ // This must use getRawType() because if the type is under refinement, we
+ // will get the refineAbstractType callback below, and we don't want to
+ // kick union find in on the constant.
+ if (C->getRawType()->isAbstract()) {
typename AbstractTypeMapTy::iterator ATI =
- AbstractTypeMap.find(C->getType());
+ AbstractTypeMap.find(cast<DerivedType>(C->getRawType()));
assert(ATI != AbstractTypeMap.end() &&
"Abstract type not in AbstractTypeMap?");
if (ATI->second == OldI)
Modified: llvm/branches/wendling/eh/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Core.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Core.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Core.cpp Sat Jul 31 19:59:02 2010
@@ -1515,6 +1515,14 @@
unwrap(BBRef)->eraseFromParent();
}
+void LLVMMoveBasicBlockBefore(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos) {
+ unwrap(BB)->moveBefore(unwrap(MovePos));
+}
+
+void LLVMMoveBasicBlockAfter(LLVMBasicBlockRef BB, LLVMBasicBlockRef MovePos) {
+ unwrap(BB)->moveAfter(unwrap(MovePos));
+}
+
/*--.. Operations on instructions ..........................................--*/
LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst) {
Modified: llvm/branches/wendling/eh/lib/VMCore/Dominators.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Dominators.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Dominators.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Dominators.cpp Sat Jul 31 19:59:02 2010
@@ -17,6 +17,7 @@
#include "llvm/Analysis/Dominators.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -51,8 +52,8 @@
TEMPLATE_INSTANTIATION(class llvm::DominatorTreeBase<BasicBlock>);
char DominatorTree::ID = 0;
-static RegisterPass<DominatorTree>
-E("domtree", "Dominator Tree Construction", true, true);
+INITIALIZE_PASS(DominatorTree, "domtree",
+ "Dominator Tree Construction", true, true);
bool DominatorTree::runOnFunction(Function &F) {
DT->recalculate(F);
@@ -105,8 +106,8 @@
//===----------------------------------------------------------------------===//
char DominanceFrontier::ID = 0;
-static RegisterPass<DominanceFrontier>
-G("domfrontier", "Dominance Frontier Construction", true, true);
+INITIALIZE_PASS(DominanceFrontier, "domfrontier",
+ "Dominance Frontier Construction", true, true);
void DominanceFrontier::verifyAnalysis() const {
if (!VerifyDomInfo) return;
@@ -122,36 +123,23 @@
// NewBB is split and now it has one successor. Update dominance frontier to
// reflect this change.
void DominanceFrontier::splitBlock(BasicBlock *NewBB) {
- assert(NewBB->getTerminator()->getNumSuccessors() == 1
- && "NewBB should have a single successor!");
+ assert(NewBB->getTerminator()->getNumSuccessors() == 1 &&
+ "NewBB should have a single successor!");
BasicBlock *NewBBSucc = NewBB->getTerminator()->getSuccessor(0);
- SmallVector<BasicBlock*, 8> PredBlocks;
- for (pred_iterator PI = pred_begin(NewBB), PE = pred_end(NewBB);
- PI != PE; ++PI)
- PredBlocks.push_back(*PI);
-
- if (PredBlocks.empty())
- // If NewBB does not have any predecessors then it is a entry block.
- // In this case, NewBB and its successor NewBBSucc dominates all
- // other blocks.
- return;
-
// NewBBSucc inherits original NewBB frontier.
DominanceFrontier::iterator NewBBI = find(NewBB);
- if (NewBBI != end()) {
- DominanceFrontier::DomSetType NewBBSet = NewBBI->second;
- DominanceFrontier::DomSetType NewBBSuccSet;
- NewBBSuccSet.insert(NewBBSet.begin(), NewBBSet.end());
- addBasicBlock(NewBBSucc, NewBBSuccSet);
- }
+ if (NewBBI != end())
+ addBasicBlock(NewBBSucc, NewBBI->second);
// If NewBB dominates NewBBSucc, then DF(NewBB) is now going to be the
- // DF(PredBlocks[0]) without the stuff that the new block does not dominate
+ // DF(NewBBSucc) without the stuff that the new block does not dominate
// a predecessor of.
DominatorTree &DT = getAnalysis<DominatorTree>();
- if (DT.dominates(NewBB, NewBBSucc)) {
- DominanceFrontier::iterator DFI = find(PredBlocks[0]);
+ DomTreeNode *NewBBNode = DT.getNode(NewBB);
+ DomTreeNode *NewBBSuccNode = DT.getNode(NewBBSucc);
+ if (DT.dominates(NewBBNode, NewBBSuccNode)) {
+ DominanceFrontier::iterator DFI = find(NewBBSucc);
if (DFI != end()) {
DominanceFrontier::DomSetType Set = DFI->second;
// Filter out stuff in Set that we do not dominate a predecessor of.
@@ -160,8 +148,10 @@
bool DominatesPred = false;
for (pred_iterator PI = pred_begin(*SetI), E = pred_end(*SetI);
PI != E; ++PI)
- if (DT.dominates(NewBB, *PI))
+ if (DT.dominates(NewBBNode, DT.getNode(*PI))) {
DominatesPred = true;
+ break;
+ }
if (!DominatesPred)
Set.erase(SetI++);
else
@@ -186,50 +176,71 @@
NewDFSet.insert(NewBBSucc);
addBasicBlock(NewBB, NewDFSet);
}
-
- // Now we must loop over all of the dominance frontiers in the function,
- // replacing occurrences of NewBBSucc with NewBB in some cases. All
- // blocks that dominate a block in PredBlocks and contained NewBBSucc in
- // their dominance frontier must be updated to contain NewBB instead.
- //
- for (Function::iterator FI = NewBB->getParent()->begin(),
- FE = NewBB->getParent()->end(); FI != FE; ++FI) {
- DominanceFrontier::iterator DFI = find(FI);
- if (DFI == end()) continue; // unreachable block.
-
- // Only consider nodes that have NewBBSucc in their dominator frontier.
- if (!DFI->second.count(NewBBSucc)) continue;
- // Verify whether this block dominates a block in predblocks. If not, do
- // not update it.
- bool BlockDominatesAny = false;
- for (SmallVectorImpl<BasicBlock*>::const_iterator BI = PredBlocks.begin(),
- BE = PredBlocks.end(); BI != BE; ++BI) {
- if (DT.dominates(FI, *BI)) {
- BlockDominatesAny = true;
+ // Now update dominance frontiers which either used to contain NewBBSucc
+ // or which now need to include NewBB.
+
+ // Collect the set of blocks which dominate a predecessor of NewBB or
+ // NewSuccBB and which don't dominate both. This is an initial
+ // approximation of the blocks whose dominance frontiers will need updates.
+ SmallVector<DomTreeNode *, 16> AllPredDoms;
+
+ // Compute the block which dominates both NewBBSucc and NewBB. This is
+ // the immediate dominator of NewBBSucc unless NewBB dominates NewBBSucc.
+ // The code below which climbs dominator trees will stop at this point,
+ // because from this point up, dominance frontiers are unaffected.
+ DomTreeNode *DominatesBoth = 0;
+ if (NewBBSuccNode) {
+ DominatesBoth = NewBBSuccNode->getIDom();
+ if (DominatesBoth == NewBBNode)
+ DominatesBoth = NewBBNode->getIDom();
+ }
+
+ // Collect the set of all blocks which dominate a predecessor of NewBB.
+ SmallPtrSet<DomTreeNode *, 8> NewBBPredDoms;
+ for (pred_iterator PI = pred_begin(NewBB), E = pred_end(NewBB); PI != E; ++PI)
+ for (DomTreeNode *DTN = DT.getNode(*PI); DTN; DTN = DTN->getIDom()) {
+ if (DTN == DominatesBoth)
break;
- }
+ if (!NewBBPredDoms.insert(DTN))
+ break;
+ AllPredDoms.push_back(DTN);
}
- // If NewBBSucc should not stay in our dominator frontier, remove it.
- // We remove it unless there is a predecessor of NewBBSucc that we
- // dominate, but we don't strictly dominate NewBBSucc.
- bool ShouldRemove = true;
- if ((BasicBlock*)FI == NewBBSucc || !DT.dominates(FI, NewBBSucc)) {
- // Okay, we know that PredDom does not strictly dominate NewBBSucc.
- // Check to see if it dominates any predecessors of NewBBSucc.
- for (pred_iterator PI = pred_begin(NewBBSucc),
- E = pred_end(NewBBSucc); PI != E; ++PI)
- if (DT.dominates(FI, *PI)) {
- ShouldRemove = false;
- break;
- }
+ // Collect the set of all blocks which dominate a predecessor of NewSuccBB.
+ SmallPtrSet<DomTreeNode *, 8> NewBBSuccPredDoms;
+ for (pred_iterator PI = pred_begin(NewBBSucc),
+ E = pred_end(NewBBSucc); PI != E; ++PI)
+ for (DomTreeNode *DTN = DT.getNode(*PI); DTN; DTN = DTN->getIDom()) {
+ if (DTN == DominatesBoth)
+ break;
+ if (!NewBBSuccPredDoms.insert(DTN))
+ break;
+ if (!NewBBPredDoms.count(DTN))
+ AllPredDoms.push_back(DTN);
}
-
- if (ShouldRemove)
- removeFromFrontier(DFI, NewBBSucc);
- if (BlockDominatesAny && (&*FI == NewBB || !DT.dominates(FI, NewBB)))
+
+ // Visit all relevant dominance frontiers and make any needed updates.
+ for (SmallVectorImpl<DomTreeNode *>::const_iterator I = AllPredDoms.begin(),
+ E = AllPredDoms.end(); I != E; ++I) {
+ DomTreeNode *DTN = *I;
+ iterator DFI = find((*I)->getBlock());
+
+ // Only consider nodes that have NewBBSucc in their dominator frontier.
+ if (DFI == end() || !DFI->second.count(NewBBSucc)) continue;
+
+ // If the block dominates a predecessor of NewBB but does not properly
+ // dominate NewBB itself, add NewBB to its dominance frontier.
+ if (NewBBPredDoms.count(DTN) &&
+ !DT.properlyDominates(DTN, NewBBNode))
addToFrontier(DFI, NewBB);
+
+ // If the block does not dominate a predecessor of NewBBSucc or
+ // properly dominates NewBBSucc itself, remove NewBBSucc from its
+ // dominance frontier.
+ if (!NewBBSuccPredDoms.count(DTN) ||
+ DT.properlyDominates(DTN, NewBBSuccNode))
+ removeFromFrontier(DFI, NewBBSucc);
}
}
@@ -343,3 +354,7 @@
}
}
+void DominanceFrontierBase::dump() const {
+ print(dbgs());
+}
+
Modified: llvm/branches/wendling/eh/lib/VMCore/Globals.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Globals.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Globals.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Globals.cpp Sat Jul 31 19:59:02 2010
@@ -102,7 +102,14 @@
setVisibility(Src->getVisibility());
}
-
+void GlobalValue::setAlignment(unsigned Align) {
+ assert((Align & (Align-1)) == 0 && "Alignment is not a power of 2!");
+ assert(Align <= MaximumAlignment &&
+ "Alignment is greater than MaximumAlignment!");
+ Alignment = Log2_32(Align) + 1;
+ assert(getAlignment() == Align && "Alignment representation error!");
+}
+
//===----------------------------------------------------------------------===//
// GlobalVariable Implementation
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/VMCore/InlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/InlineAsm.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/InlineAsm.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/InlineAsm.cpp Sat Jul 31 19:59:02 2010
@@ -164,7 +164,7 @@
StringRef::iterator ConstraintEnd = std::find(I, E, ',');
if (ConstraintEnd == I || // Empty constraint like ",,"
- Info.Parse(std::string(I, ConstraintEnd), Result)) {
+ Info.Parse(StringRef(I, ConstraintEnd-I), Result)) {
Result.clear(); // Erroneous constraint?
break;
}
Modified: llvm/branches/wendling/eh/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Instruction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Instruction.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Instruction.cpp Sat Jul 31 19:59:02 2010
@@ -49,8 +49,8 @@
// Out of line virtual method, so the vtable, etc has a home.
Instruction::~Instruction() {
assert(Parent == 0 && "Instruction still linked in the program!");
- if (hasMetadata())
- removeAllMetadata();
+ if (hasMetadataHashEntry())
+ clearMetadataHashEntries();
}
Modified: llvm/branches/wendling/eh/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Instructions.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Instructions.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Instructions.cpp Sat Jul 31 19:59:02 2010
@@ -33,10 +33,8 @@
User::op_iterator CallSite::getCallee() const {
Instruction *II(getInstruction());
return isCall()
- ? (CallInst::ArgOffset
- ? cast</*FIXME: CallInst*/User>(II)->op_begin()
- : cast</*FIXME: CallInst*/User>(II)->op_end() - 1)
- : cast<InvokeInst>(II)->op_end() - 4; // Skip PersFn, BB, BB, Function
+ ? cast</*FIXME: CallInst*/User>(II)->op_end() - 1 // Skip Callee
+ : cast<InvokeInst>(II)->op_end() - 4; // Skip PersFn, BB, BB, Callee
}
//===----------------------------------------------------------------------===//
@@ -233,7 +231,7 @@
void CallInst::init(Value *Func, Value* const *Params, unsigned NumParams) {
assert(NumOperands == NumParams+1 && "NumOperands not set up?");
- Op<ArgOffset -1>() = Func;
+ Op<-1>() = Func;
const FunctionType *FTy =
cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -246,15 +244,15 @@
assert((i >= FTy->getNumParams() ||
FTy->getParamType(i) == Params[i]->getType()) &&
"Calling a function with a bad signature!");
- OperandList[i + ArgOffset] = Params[i];
+ OperandList[i] = Params[i];
}
}
void CallInst::init(Value *Func, Value *Actual1, Value *Actual2) {
assert(NumOperands == 3 && "NumOperands not set up?");
- Op<ArgOffset -1>() = Func;
- Op<ArgOffset + 0>() = Actual1;
- Op<ArgOffset + 1>() = Actual2;
+ Op<-1>() = Func;
+ Op<0>() = Actual1;
+ Op<1>() = Actual2;
const FunctionType *FTy =
cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -273,8 +271,8 @@
void CallInst::init(Value *Func, Value *Actual) {
assert(NumOperands == 2 && "NumOperands not set up?");
- Op<ArgOffset -1>() = Func;
- Op<ArgOffset + 0>() = Actual;
+ Op<-1>() = Func;
+ Op<0>() = Actual;
const FunctionType *FTy =
cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -290,7 +288,7 @@
void CallInst::init(Value *Func) {
assert(NumOperands == 1 && "NumOperands not set up?");
- Op<ArgOffset -1>() = Func;
+ Op<-1>() = Func;
const FunctionType *FTy =
cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -922,6 +920,8 @@
void AllocaInst::setAlignment(unsigned Align) {
assert((Align & (Align-1)) == 0 && "Alignment is not a power of 2!");
+ assert(Align <= MaximumAlignment &&
+ "Alignment is greater than MaximumAlignment!");
setInstructionSubclassData(Log2_32(Align) + 1);
assert(getAlignment() == Align && "Alignment representation error!");
}
@@ -1057,8 +1057,11 @@
void LoadInst::setAlignment(unsigned Align) {
assert((Align & (Align-1)) == 0 && "Alignment is not a power of 2!");
+ assert(Align <= MaximumAlignment &&
+ "Alignment is greater than MaximumAlignment!");
setInstructionSubclassData((getSubclassDataFromInstruction() & 1) |
((Log2_32(Align)+1)<<1));
+ assert(getAlignment() == Align && "Alignment representation error!");
}
//===----------------------------------------------------------------------===//
@@ -1153,8 +1156,11 @@
void StoreInst::setAlignment(unsigned Align) {
assert((Align & (Align-1)) == 0 && "Alignment is not a power of 2!");
+ assert(Align <= MaximumAlignment &&
+ "Alignment is greater than MaximumAlignment!");
setInstructionSubclassData((getSubclassDataFromInstruction() & 1) |
((Log2_32(Align)+1) << 1));
+ assert(getAlignment() == Align && "Alignment representation error!");
}
//===----------------------------------------------------------------------===//
Modified: llvm/branches/wendling/eh/lib/VMCore/LLVMContext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/LLVMContext.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/LLVMContext.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/LLVMContext.cpp Sat Jul 31 19:59:02 2010
@@ -110,21 +110,18 @@
/// getMDKindID - Return a unique non-zero ID for the specified metadata kind.
unsigned LLVMContext::getMDKindID(StringRef Name) const {
assert(isValidName(Name) && "Invalid MDNode name");
-
- unsigned &Entry = pImpl->CustomMDKindNames[Name];
-
+
// If this is new, assign it its ID.
- if (Entry == 0) Entry = pImpl->CustomMDKindNames.size();
- return Entry;
+ return
+ pImpl->CustomMDKindNames.GetOrCreateValue(
+ Name, pImpl->CustomMDKindNames.size()).second;
}
/// getHandlerNames - Populate client supplied smallvector using custome
/// metadata name and ID.
void LLVMContext::getMDKindNames(SmallVectorImpl<StringRef> &Names) const {
- Names.resize(pImpl->CustomMDKindNames.size()+1);
- Names[0] = "";
+ Names.resize(pImpl->CustomMDKindNames.size());
for (StringMap<unsigned>::const_iterator I = pImpl->CustomMDKindNames.begin(),
E = pImpl->CustomMDKindNames.end(); I != E; ++I)
- // MD Handlers are numbered from 1.
Names[I->second] = I->first();
}
Modified: llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Metadata.cpp Sat Jul 31 19:59:02 2010
@@ -330,53 +330,13 @@
// NamedMDNode implementation.
//
-namespace llvm {
-// SymbolTableListTraits specialization for MDSymbolTable.
-void ilist_traits<NamedMDNode>
-::addNodeToList(NamedMDNode *N) {
- assert(N->getParent() == 0 && "Value already in a container!!");
- Module *Owner = getListOwner();
- N->setParent(Owner);
- MDSymbolTable &ST = Owner->getMDSymbolTable();
- ST.insert(N->getName(), N);
+static SmallVector<TrackingVH<MDNode>, 4> &getNMDOps(void *Operands) {
+ return *(SmallVector<TrackingVH<MDNode>, 4>*)Operands;
}
-void ilist_traits<NamedMDNode>::removeNodeFromList(NamedMDNode *N) {
- N->setParent(0);
- Module *Owner = getListOwner();
- MDSymbolTable &ST = Owner->getMDSymbolTable();
- ST.remove(N->getName());
-}
-}
-
-static SmallVector<WeakVH, 4> &getNMDOps(void *Operands) {
- return *(SmallVector<WeakVH, 4>*)Operands;
-}
-
-NamedMDNode::NamedMDNode(LLVMContext &C, const Twine &N,
- MDNode *const *MDs,
- unsigned NumMDs, Module *ParentModule)
- : Value(Type::getMetadataTy(C), Value::NamedMDNodeVal), Parent(0) {
- setName(N);
- Operands = new SmallVector<WeakVH, 4>();
-
- SmallVector<WeakVH, 4> &Node = getNMDOps(Operands);
- for (unsigned i = 0; i != NumMDs; ++i)
- Node.push_back(WeakVH(MDs[i]));
-
- if (ParentModule)
- ParentModule->getNamedMDList().push_back(this);
-}
-
-NamedMDNode *NamedMDNode::Create(const NamedMDNode *NMD, Module *M) {
- assert(NMD && "Invalid source NamedMDNode!");
- SmallVector<MDNode *, 4> Elems;
- Elems.reserve(NMD->getNumOperands());
-
- for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
- Elems.push_back(NMD->getOperand(i));
- return new NamedMDNode(NMD->getContext(), NMD->getName().data(),
- Elems.data(), Elems.size(), M);
+NamedMDNode::NamedMDNode(const Twine &N)
+ : Name(N.str()), Parent(0),
+ Operands(new SmallVector<TrackingVH<MDNode>, 4>()) {
}
NamedMDNode::~NamedMDNode() {
@@ -392,18 +352,18 @@
/// getOperand - Return specified operand.
MDNode *NamedMDNode::getOperand(unsigned i) const {
assert(i < getNumOperands() && "Invalid Operand number!");
- return dyn_cast_or_null<MDNode>(getNMDOps(Operands)[i]);
+ return dyn_cast<MDNode>(&*getNMDOps(Operands)[i]);
}
/// addOperand - Add metadata Operand.
void NamedMDNode::addOperand(MDNode *M) {
- getNMDOps(Operands).push_back(WeakVH(M));
+ getNMDOps(Operands).push_back(TrackingVH<MDNode>(M));
}
/// eraseFromParent - Drop all references and remove the node from parent
/// module.
void NamedMDNode::eraseFromParent() {
- getParent()->getNamedMDList().erase(this);
+ getParent()->eraseNamedMetadata(this);
}
/// dropAllReferences - Remove all uses and clear node vector.
@@ -411,22 +371,6 @@
getNMDOps(Operands).clear();
}
-/// setName - Set the name of this named metadata.
-void NamedMDNode::setName(const Twine &NewName) {
- assert (!NewName.isTriviallyEmpty() && "Invalid named metadata name!");
-
- SmallString<256> NameData;
- StringRef NameRef = NewName.toStringRef(NameData);
-
- // Name isn't changing?
- if (getName() == NameRef)
- return;
-
- Name = NameRef.str();
- if (Parent)
- Parent->getMDSymbolTable().insert(NameRef, this);
-}
-
/// getName - Return a constant reference to this named metadata's name.
StringRef NamedMDNode::getName() const {
return StringRef(Name);
@@ -445,10 +389,6 @@
return getMetadataImpl(getContext().getMDKindID(Kind));
}
-void Instruction::setDbgMetadata(MDNode *Node) {
- DbgLoc = DebugLoc::getFromDILocation(Node);
-}
-
/// setMetadata - Set the metadata of of the specified kind to the specified
/// node. This updates/replaces metadata if already present, or removes it if
/// Node is null.
@@ -567,13 +507,11 @@
}
-/// removeAllMetadata - Remove all metadata from this instruction.
-void Instruction::removeAllMetadata() {
- assert(hasMetadata() && "Caller should check");
- DbgLoc = DebugLoc();
- if (hasMetadataHashEntry()) {
- getContext().pImpl->MetadataStore.erase(this);
- setHasMetadataHashEntry(false);
- }
+/// clearMetadataHashEntries - Clear all hashtable-based metadata from
+/// this instruction.
+void Instruction::clearMetadataHashEntries() {
+ assert(hasMetadataHashEntry() && "Caller should check");
+ getContext().pImpl->MetadataStore.erase(this);
+ setHasMetadataHashEntry(false);
}
Modified: llvm/branches/wendling/eh/lib/VMCore/Module.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Module.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Module.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Module.cpp Sat Jul 31 19:59:02 2010
@@ -61,7 +61,7 @@
: Context(C), Materializer(NULL), ModuleID(MID), DataLayout("") {
ValSymTab = new ValueSymbolTable();
TypeSymTab = new TypeSymbolTable();
- NamedMDSymTab = new MDSymbolTable();
+ NamedMDSymTab = new StringMap<NamedMDNode *>();
}
Module::~Module() {
@@ -73,7 +73,7 @@
NamedMDList.clear();
delete ValSymTab;
delete TypeSymTab;
- delete NamedMDSymTab;
+ delete static_cast<StringMap<NamedMDNode *> *>(NamedMDSymTab);
}
/// Target endian information...
@@ -316,19 +316,28 @@
NamedMDNode *Module::getNamedMetadata(const Twine &Name) const {
SmallString<256> NameData;
StringRef NameRef = Name.toStringRef(NameData);
- return NamedMDSymTab->lookup(NameRef);
+ return static_cast<StringMap<NamedMDNode*> *>(NamedMDSymTab)->lookup(NameRef);
}
/// getOrInsertNamedMetadata - Return the first named MDNode in the module
/// with the specified name. This method returns a new NamedMDNode if a
/// NamedMDNode with the specified name is not found.
NamedMDNode *Module::getOrInsertNamedMetadata(StringRef Name) {
- NamedMDNode *NMD = NamedMDSymTab->lookup(Name);
- if (!NMD)
- NMD = NamedMDNode::Create(getContext(), Name, NULL, 0, this);
+ NamedMDNode *&NMD =
+ (*static_cast<StringMap<NamedMDNode *> *>(NamedMDSymTab))[Name];
+ if (!NMD) {
+ NMD = new NamedMDNode(Name);
+ NMD->setParent(this);
+ NamedMDList.push_back(NMD);
+ }
return NMD;
}
+void Module::eraseNamedMetadata(NamedMDNode *NMD) {
+ static_cast<StringMap<NamedMDNode *> *>(NamedMDSymTab)->erase(NMD->getName());
+ NamedMDList.erase(NMD);
+}
+
//===----------------------------------------------------------------------===//
// Methods for easy access to the types in the module.
//
Modified: llvm/branches/wendling/eh/lib/VMCore/Pass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Pass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Pass.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Pass.cpp Sat Jul 31 19:59:02 2010
@@ -15,6 +15,7 @@
#include "llvm/Pass.h"
#include "llvm/PassManager.h"
+#include "llvm/PassRegistry.h"
#include "llvm/Module.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringMap.h"
@@ -233,134 +234,6 @@
return PMT_BasicBlockPassManager;
}
-//===----------------------------------------------------------------------===//
-// Pass Registration mechanism
-//
-namespace {
-class PassRegistrar {
- /// Guards the contents of this class.
- mutable sys::SmartMutex<true> Lock;
-
- /// PassInfoMap - Keep track of the passinfo object for each registered llvm
- /// pass.
- typedef std::map<intptr_t, const PassInfo*> MapType;
- MapType PassInfoMap;
-
- typedef StringMap<const PassInfo*> StringMapType;
- StringMapType PassInfoStringMap;
-
- /// AnalysisGroupInfo - Keep track of information for each analysis group.
- struct AnalysisGroupInfo {
- std::set<const PassInfo *> Implementations;
- };
-
- /// AnalysisGroupInfoMap - Information for each analysis group.
- std::map<const PassInfo *, AnalysisGroupInfo> AnalysisGroupInfoMap;
-
-public:
-
- const PassInfo *GetPassInfo(intptr_t TI) const {
- sys::SmartScopedLock<true> Guard(Lock);
- MapType::const_iterator I = PassInfoMap.find(TI);
- return I != PassInfoMap.end() ? I->second : 0;
- }
-
- const PassInfo *GetPassInfo(StringRef Arg) const {
- sys::SmartScopedLock<true> Guard(Lock);
- StringMapType::const_iterator I = PassInfoStringMap.find(Arg);
- return I != PassInfoStringMap.end() ? I->second : 0;
- }
-
- void RegisterPass(const PassInfo &PI) {
- sys::SmartScopedLock<true> Guard(Lock);
- bool Inserted =
- PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second;
- assert(Inserted && "Pass registered multiple times!"); Inserted=Inserted;
- PassInfoStringMap[PI.getPassArgument()] = &PI;
- }
-
- void UnregisterPass(const PassInfo &PI) {
- sys::SmartScopedLock<true> Guard(Lock);
- MapType::iterator I = PassInfoMap.find(PI.getTypeInfo());
- assert(I != PassInfoMap.end() && "Pass registered but not in map!");
-
- // Remove pass from the map.
- PassInfoMap.erase(I);
- PassInfoStringMap.erase(PI.getPassArgument());
- }
-
- void EnumerateWith(PassRegistrationListener *L) {
- sys::SmartScopedLock<true> Guard(Lock);
- for (MapType::const_iterator I = PassInfoMap.begin(),
- E = PassInfoMap.end(); I != E; ++I)
- L->passEnumerate(I->second);
- }
-
-
- /// Analysis Group Mechanisms.
- void RegisterAnalysisGroup(PassInfo *InterfaceInfo,
- const PassInfo *ImplementationInfo,
- bool isDefault) {
- sys::SmartScopedLock<true> Guard(Lock);
- AnalysisGroupInfo &AGI = AnalysisGroupInfoMap[InterfaceInfo];
- assert(AGI.Implementations.count(ImplementationInfo) == 0 &&
- "Cannot add a pass to the same analysis group more than once!");
- AGI.Implementations.insert(ImplementationInfo);
- if (isDefault) {
- assert(InterfaceInfo->getNormalCtor() == 0 &&
- "Default implementation for analysis group already specified!");
- assert(ImplementationInfo->getNormalCtor() &&
- "Cannot specify pass as default if it does not have a default ctor");
- InterfaceInfo->setNormalCtor(ImplementationInfo->getNormalCtor());
- }
- }
-};
-}
-
-static std::vector<PassRegistrationListener*> *Listeners = 0;
-static sys::SmartMutex<true> ListenersLock;
-
-static PassRegistrar *PassRegistrarObj = 0;
-static PassRegistrar *getPassRegistrar() {
- // Use double-checked locking to safely initialize the registrar when
- // we're running in multithreaded mode.
- PassRegistrar* tmp = PassRegistrarObj;
- if (llvm_is_multithreaded()) {
- sys::MemoryFence();
- if (!tmp) {
- llvm_acquire_global_lock();
- tmp = PassRegistrarObj;
- if (!tmp) {
- tmp = new PassRegistrar();
- sys::MemoryFence();
- PassRegistrarObj = tmp;
- }
- llvm_release_global_lock();
- }
- } else if (!tmp) {
- PassRegistrarObj = new PassRegistrar();
- }
-
- return PassRegistrarObj;
-}
-
-namespace {
-
-// FIXME: We use ManagedCleanup to erase the pass registrar on shutdown.
-// Unfortunately, passes are registered with static ctors, and having
-// llvm_shutdown clear this map prevents successful ressurection after
-// llvm_shutdown is run. Ideally we should find a solution so that we don't
-// leak the map, AND can still resurrect after shutdown.
-void cleanupPassRegistrar(void*) {
- if (PassRegistrarObj) {
- delete PassRegistrarObj;
- PassRegistrarObj = 0;
- }
-}
-ManagedCleanup<&cleanupPassRegistrar> registrarCleanup ATTRIBUTE_USED;
-
-}
-
// getPassInfo - Return the PassInfo data structure that corresponds to this
// pass...
const PassInfo *Pass::getPassInfo() const {
@@ -368,26 +241,11 @@
}
const PassInfo *Pass::lookupPassInfo(intptr_t TI) {
- return getPassRegistrar()->GetPassInfo(TI);
+ return PassRegistry::getPassRegistry()->getPassInfo(TI);
}
const PassInfo *Pass::lookupPassInfo(StringRef Arg) {
- return getPassRegistrar()->GetPassInfo(Arg);
-}
-
-void PassInfo::registerPass() {
- getPassRegistrar()->RegisterPass(*this);
-
- // Notify any listeners.
- sys::SmartScopedLock<true> Lock(ListenersLock);
- if (Listeners)
- for (std::vector<PassRegistrationListener*>::iterator
- I = Listeners->begin(), E = Listeners->end(); I != E; ++I)
- (*I)->passRegistered(this);
-}
-
-void PassInfo::unregisterPass() {
- getPassRegistrar()->UnregisterPass(*this);
+ return PassRegistry::getPassRegistry()->getPassInfo(Arg);
}
Pass *PassInfo::createPass() const {
@@ -406,30 +264,9 @@
//
RegisterAGBase::RegisterAGBase(const char *Name, intptr_t InterfaceID,
intptr_t PassID, bool isDefault)
- : PassInfo(Name, InterfaceID) {
-
- PassInfo *InterfaceInfo =
- const_cast<PassInfo*>(Pass::lookupPassInfo(InterfaceID));
- if (InterfaceInfo == 0) {
- // First reference to Interface, register it now.
- registerPass();
- InterfaceInfo = this;
- }
- assert(isAnalysisGroup() &&
- "Trying to join an analysis group that is a normal pass!");
-
- if (PassID) {
- const PassInfo *ImplementationInfo = Pass::lookupPassInfo(PassID);
- assert(ImplementationInfo &&
- "Must register pass before adding to AnalysisGroup!");
-
- // Make sure we keep track of the fact that the implementation implements
- // the interface.
- PassInfo *IIPI = const_cast<PassInfo*>(ImplementationInfo);
- IIPI->addInterfaceImplemented(InterfaceInfo);
-
- getPassRegistrar()->RegisterAnalysisGroup(InterfaceInfo, IIPI, isDefault);
- }
+ : PassInfo(Name, InterfaceID) {
+ PassRegistry::getPassRegistry()->registerAnalysisGroup(InterfaceID, PassID,
+ *this, isDefault);
}
@@ -440,31 +277,19 @@
// PassRegistrationListener ctor - Add the current object to the list of
// PassRegistrationListeners...
PassRegistrationListener::PassRegistrationListener() {
- sys::SmartScopedLock<true> Lock(ListenersLock);
- if (!Listeners) Listeners = new std::vector<PassRegistrationListener*>();
- Listeners->push_back(this);
+ PassRegistry::getPassRegistry()->addRegistrationListener(this);
}
// dtor - Remove object from list of listeners...
PassRegistrationListener::~PassRegistrationListener() {
- sys::SmartScopedLock<true> Lock(ListenersLock);
- std::vector<PassRegistrationListener*>::iterator I =
- std::find(Listeners->begin(), Listeners->end(), this);
- assert(Listeners && I != Listeners->end() &&
- "PassRegistrationListener not registered!");
- Listeners->erase(I);
-
- if (Listeners->empty()) {
- delete Listeners;
- Listeners = 0;
- }
+ PassRegistry::getPassRegistry()->removeRegistrationListener(this);
}
// enumeratePasses - Iterate over the registered passes, calling the
// passEnumerate callback on each PassInfo object.
//
void PassRegistrationListener::enumeratePasses() {
- getPassRegistrar()->EnumerateWith(this);
+ PassRegistry::getPassRegistry()->enumerateWith(this);
}
PassNameParser::~PassNameParser() {}
Modified: llvm/branches/wendling/eh/lib/VMCore/PrintModulePass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/PrintModulePass.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/PrintModulePass.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/PrintModulePass.cpp Sat Jul 31 19:59:02 2010
@@ -77,11 +77,11 @@
}
char PrintModulePass::ID = 0;
-static RegisterPass<PrintModulePass>
-X("print-module", "Print module to stderr");
+INITIALIZE_PASS(PrintModulePass, "print-module",
+ "Print module to stderr", false, false);
char PrintFunctionPass::ID = 0;
-static RegisterPass<PrintFunctionPass>
-Y("print-function","Print function to stderr");
+INITIALIZE_PASS(PrintFunctionPass, "print-function",
+ "Print function to stderr", false, false);
/// createPrintModulePass - Create and return a pass that writes the
/// module to the specified raw_ostream.
Modified: llvm/branches/wendling/eh/lib/VMCore/Type.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Type.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Type.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Type.cpp Sat Jul 31 19:59:02 2010
@@ -455,8 +455,8 @@
/// isValidReturnType - Return true if the specified type is valid as a return
/// type.
bool FunctionType::isValidReturnType(const Type *RetTy) {
- return RetTy->getTypeID() != LabelTyID &&
- RetTy->getTypeID() != MetadataTyID;
+ return !RetTy->isFunctionTy() && !RetTy->isLabelTy() &&
+ !RetTy->isMetadataTy();
}
/// isValidArgumentType - Return true if the specified type is valid as an
@@ -603,8 +603,8 @@
static inline ChildIteratorType child_begin(NodeType *N) {
if (N->isAbstract())
return N->subtype_begin();
- else // No need to process children of concrete types.
- return N->subtype_end();
+ // No need to process children of concrete types.
+ return N->subtype_end();
}
static inline ChildIteratorType child_end(NodeType *N) {
return N->subtype_end();
@@ -627,35 +627,35 @@
// Concrete types are leaves in the tree. Since an SCC will either be all
// abstract or all concrete, we only need to check one type.
- if (SCC[0]->isAbstract()) {
- if (SCC[0]->isOpaqueTy())
- return; // Not going to be concrete, sorry.
-
- // If all of the children of all of the types in this SCC are concrete,
- // then this SCC is now concrete as well. If not, neither this SCC, nor
- // any parent SCCs will be concrete, so we might as well just exit.
- for (unsigned i = 0, e = SCC.size(); i != e; ++i)
- for (Type::subtype_iterator CI = SCC[i]->subtype_begin(),
- E = SCC[i]->subtype_end(); CI != E; ++CI)
- if ((*CI)->isAbstract())
- // If the child type is in our SCC, it doesn't make the entire SCC
- // abstract unless there is a non-SCC abstract type.
- if (std::find(SCC.begin(), SCC.end(), *CI) == SCC.end())
- return; // Not going to be concrete, sorry.
-
- // Okay, we just discovered this whole SCC is now concrete, mark it as
- // such!
- for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
- assert(SCC[i]->isAbstract() && "Why are we processing concrete types?");
-
- SCC[i]->setAbstract(false);
- }
-
- for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
- assert(!SCC[i]->isAbstract() && "Concrete type became abstract?");
- // The type just became concrete, notify all users!
- cast<DerivedType>(SCC[i])->notifyUsesThatTypeBecameConcrete();
- }
+ if (!SCC[0]->isAbstract()) continue;
+
+ if (SCC[0]->isOpaqueTy())
+ return; // Not going to be concrete, sorry.
+
+ // If all of the children of all of the types in this SCC are concrete,
+ // then this SCC is now concrete as well. If not, neither this SCC, nor
+ // any parent SCCs will be concrete, so we might as well just exit.
+ for (unsigned i = 0, e = SCC.size(); i != e; ++i)
+ for (Type::subtype_iterator CI = SCC[i]->subtype_begin(),
+ E = SCC[i]->subtype_end(); CI != E; ++CI)
+ if ((*CI)->isAbstract())
+ // If the child type is in our SCC, it doesn't make the entire SCC
+ // abstract unless there is a non-SCC abstract type.
+ if (std::find(SCC.begin(), SCC.end(), *CI) == SCC.end())
+ return; // Not going to be concrete, sorry.
+
+ // Okay, we just discovered this whole SCC is now concrete, mark it as
+ // such!
+ for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
+ assert(SCC[i]->isAbstract() && "Why are we processing concrete types?");
+
+ SCC[i]->setAbstract(false);
+ }
+
+ for (unsigned i = 0, e = SCC.size(); i != e; ++i) {
+ assert(!SCC[i]->isAbstract() && "Concrete type became abstract?");
+ // The type just became concrete, notify all users!
+ cast<DerivedType>(SCC[i])->notifyUsesThatTypeBecameConcrete();
}
}
}
@@ -693,11 +693,15 @@
if (const IntegerType *ITy = dyn_cast<IntegerType>(Ty)) {
const IntegerType *ITy2 = cast<IntegerType>(Ty2);
return ITy->getBitWidth() == ITy2->getBitWidth();
- } else if (const PointerType *PTy = dyn_cast<PointerType>(Ty)) {
+ }
+
+ if (const PointerType *PTy = dyn_cast<PointerType>(Ty)) {
const PointerType *PTy2 = cast<PointerType>(Ty2);
return PTy->getAddressSpace() == PTy2->getAddressSpace() &&
TypesEqual(PTy->getElementType(), PTy2->getElementType(), EqTypes);
- } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
+ }
+
+ if (const StructType *STy = dyn_cast<StructType>(Ty)) {
const StructType *STy2 = cast<StructType>(Ty2);
if (STy->getNumElements() != STy2->getNumElements()) return false;
if (STy->isPacked() != STy2->isPacked()) return false;
@@ -705,22 +709,30 @@
if (!TypesEqual(STy->getElementType(i), STy2->getElementType(i), EqTypes))
return false;
return true;
- } else if (const UnionType *UTy = dyn_cast<UnionType>(Ty)) {
+ }
+
+ if (const UnionType *UTy = dyn_cast<UnionType>(Ty)) {
const UnionType *UTy2 = cast<UnionType>(Ty2);
if (UTy->getNumElements() != UTy2->getNumElements()) return false;
for (unsigned i = 0, e = UTy2->getNumElements(); i != e; ++i)
if (!TypesEqual(UTy->getElementType(i), UTy2->getElementType(i), EqTypes))
return false;
return true;
- } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
+ }
+
+ if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
const ArrayType *ATy2 = cast<ArrayType>(Ty2);
return ATy->getNumElements() == ATy2->getNumElements() &&
TypesEqual(ATy->getElementType(), ATy2->getElementType(), EqTypes);
- } else if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) {
+ }
+
+ if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) {
const VectorType *PTy2 = cast<VectorType>(Ty2);
return PTy->getNumElements() == PTy2->getNumElements() &&
TypesEqual(PTy->getElementType(), PTy2->getElementType(), EqTypes);
- } else if (const FunctionType *FTy = dyn_cast<FunctionType>(Ty)) {
+ }
+
+ if (const FunctionType *FTy = dyn_cast<FunctionType>(Ty)) {
const FunctionType *FTy2 = cast<FunctionType>(Ty2);
if (FTy->isVarArg() != FTy2->isVarArg() ||
FTy->getNumParams() != FTy2->getNumParams() ||
@@ -731,10 +743,10 @@
return false;
}
return true;
- } else {
- llvm_unreachable("Unknown derived type!");
- return false;
}
+
+ llvm_unreachable("Unknown derived type!");
+ return false;
}
namespace llvm { // in namespace llvm so findable by ADL
@@ -808,13 +820,13 @@
// Check for the built-in integer types
switch (NumBits) {
- case 1: return cast<IntegerType>(Type::getInt1Ty(C));
- case 8: return cast<IntegerType>(Type::getInt8Ty(C));
- case 16: return cast<IntegerType>(Type::getInt16Ty(C));
- case 32: return cast<IntegerType>(Type::getInt32Ty(C));
- case 64: return cast<IntegerType>(Type::getInt64Ty(C));
- default:
- break;
+ case 1: return cast<IntegerType>(Type::getInt1Ty(C));
+ case 8: return cast<IntegerType>(Type::getInt8Ty(C));
+ case 16: return cast<IntegerType>(Type::getInt16Ty(C));
+ case 32: return cast<IntegerType>(Type::getInt32Ty(C));
+ case 64: return cast<IntegerType>(Type::getInt64Ty(C));
+ default:
+ break;
}
LLVMContextImpl *pImpl = C.pImpl;
@@ -902,8 +914,8 @@
}
bool ArrayType::isValidElementType(const Type *ElemTy) {
- return ElemTy->getTypeID() != VoidTyID && ElemTy->getTypeID() != LabelTyID &&
- ElemTy->getTypeID() != MetadataTyID && !ElemTy->isFunctionTy();
+ return !ElemTy->isVoidTy() && !ElemTy->isLabelTy() &&
+ !ElemTy->isMetadataTy() && !ElemTy->isFunctionTy();
}
VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) {
@@ -1060,9 +1072,8 @@
}
bool PointerType::isValidElementType(const Type *ElemTy) {
- return ElemTy->getTypeID() != VoidTyID &&
- ElemTy->getTypeID() != LabelTyID &&
- ElemTy->getTypeID() != MetadataTyID;
+ return !ElemTy->isVoidTy() && !ElemTy->isLabelTy() &&
+ !ElemTy->isMetadataTy();
}
@@ -1071,8 +1082,7 @@
//
OpaqueType *OpaqueType::get(LLVMContext &C) {
- OpaqueType *OT = new OpaqueType(C); // All opaque types are distinct
-
+ OpaqueType *OT = new OpaqueType(C); // All opaque types are distinct.
LLVMContextImpl *pImpl = C.pImpl;
pImpl->OpaqueTypes.insert(OT);
return OT;
@@ -1123,18 +1133,17 @@
<< ">[" << (void*)this << "]" << "\n");
#endif
- this->destroy();
+ this->destroy();
}
-
}
-// unlockedRefineAbstractTypeTo - This function is used when it is discovered
+// refineAbstractTypeTo - This function is used when it is discovered
// that the 'this' abstract type is actually equivalent to the NewType
// specified. This causes all users of 'this' to switch to reference the more
// concrete type NewType and for 'this' to be deleted. Only used for internal
// callers.
//
-void DerivedType::unlockedRefineAbstractTypeTo(const Type *NewType) {
+void DerivedType::refineAbstractTypeTo(const Type *NewType) {
assert(isAbstract() && "refineAbstractTypeTo: Current type is not abstract!");
assert(this != NewType && "Can't refine to myself!");
assert(ForwardType == 0 && "This type has already been refined!");
@@ -1199,15 +1208,6 @@
// destroyed.
}
-// refineAbstractTypeTo - This function is used by external callers to notify
-// us that this abstract type is equivalent to another type.
-//
-void DerivedType::refineAbstractTypeTo(const Type *NewType) {
- // All recursive calls will go through unlockedRefineAbstractTypeTo,
- // to avoid deadlock problems.
- unlockedRefineAbstractTypeTo(NewType);
-}
-
// notifyUsesThatTypeBecameConcrete - Notify AbstractTypeUsers of this type that
// the current type has transitioned from being abstract to being concrete.
//
Modified: llvm/branches/wendling/eh/lib/VMCore/TypesContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/TypesContext.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/TypesContext.h (original)
+++ llvm/branches/wendling/eh/lib/VMCore/TypesContext.h Sat Jul 31 19:59:02 2010
@@ -370,7 +370,7 @@
// We already have this type in the table. Get rid of the newly refined
// type.
TypeClass *NewTy = cast<TypeClass>((Type*)I->second.get());
- Ty->unlockedRefineAbstractTypeTo(NewTy);
+ Ty->refineAbstractTypeTo(NewTy);
return;
}
} else {
@@ -385,31 +385,33 @@
if (I->second == Ty) {
// Remember the position of the old type if we see it in our scan.
Entry = I;
- } else {
- if (TypesEqual(Ty, I->second)) {
- TypeClass *NewTy = cast<TypeClass>((Type*)I->second.get());
+ continue;
+ }
+
+ if (!TypesEqual(Ty, I->second))
+ continue;
+
+ TypeClass *NewTy = cast<TypeClass>((Type*)I->second.get());
- // Remove the old entry form TypesByHash. If the hash values differ
- // now, remove it from the old place. Otherwise, continue scanning
- // withing this hashcode to reduce work.
- if (NewTypeHash != OldTypeHash) {
- RemoveFromTypesByHash(OldTypeHash, Ty);
- } else {
- if (Entry == E) {
- // Find the location of Ty in the TypesByHash structure if we
- // haven't seen it already.
- while (I->second != Ty) {
- ++I;
- assert(I != E && "Structure doesn't contain type??");
- }
- Entry = I;
- }
- TypesByHash.erase(Entry);
+ // Remove the old entry form TypesByHash. If the hash values differ
+ // now, remove it from the old place. Otherwise, continue scanning
+ // withing this hashcode to reduce work.
+ if (NewTypeHash != OldTypeHash) {
+ RemoveFromTypesByHash(OldTypeHash, Ty);
+ } else {
+ if (Entry == E) {
+ // Find the location of Ty in the TypesByHash structure if we
+ // haven't seen it already.
+ while (I->second != Ty) {
+ ++I;
+ assert(I != E && "Structure doesn't contain type??");
}
- Ty->unlockedRefineAbstractTypeTo(NewTy);
- return;
+ Entry = I;
}
+ TypesByHash.erase(Entry);
}
+ Ty->refineAbstractTypeTo(NewTy);
+ return;
}
// If there is no existing type of the same structure, we reinsert an
Modified: llvm/branches/wendling/eh/lib/VMCore/Use.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Use.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Use.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Use.cpp Sat Jul 31 19:59:02 2010
@@ -86,14 +86,27 @@
//===----------------------------------------------------------------------===//
Use *Use::initTags(Use * const Start, Use *Stop, ptrdiff_t Done) {
+ while (Done < 20) {
+ if (Start == Stop--)
+ return Start;
+ static const PrevPtrTag tags[20] = { fullStopTag, oneDigitTag, stopTag,
+ oneDigitTag, oneDigitTag, stopTag,
+ zeroDigitTag, oneDigitTag, oneDigitTag,
+ stopTag, zeroDigitTag, oneDigitTag,
+ zeroDigitTag, oneDigitTag, stopTag,
+ oneDigitTag, oneDigitTag, oneDigitTag,
+ oneDigitTag, stopTag
+ };
+ Stop->Prev.setFromOpaqueValue(reinterpret_cast<Use**>(tags[Done++]));
+ Stop->Val = 0;
+ }
+
ptrdiff_t Count = Done;
while (Start != Stop) {
--Stop;
Stop->Val = 0;
if (!Count) {
- Stop->Prev.setFromOpaqueValue(reinterpret_cast<Use**>(Done == 0
- ? fullStopTag
- : stopTag));
+ Stop->Prev.setFromOpaqueValue(reinterpret_cast<Use**>(stopTag));
++Done;
Count = Done;
} else {
Modified: llvm/branches/wendling/eh/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Value.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Value.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Value.cpp Sat Jul 31 19:59:02 2010
@@ -139,10 +139,6 @@
} else if (Argument *A = dyn_cast<Argument>(V)) {
if (Function *P = A->getParent())
ST = &P->getValueSymbolTable();
- } else if (NamedMDNode *N = dyn_cast<NamedMDNode>(V)) {
- if (Module *P = N->getParent()) {
- ST = &P->getValueSymbolTable();
- }
} else if (isa<MDString>(V))
return true;
else {
@@ -492,10 +488,15 @@
ValueHandleBase *Entry = pImpl->ValueHandles[V];
assert(Entry && "Value bit set but no entries exist");
- // We use a local ValueHandleBase as an iterator so that
- // ValueHandles can add and remove themselves from the list without
- // breaking our iteration. This is not really an AssertingVH; we
- // just have to give ValueHandleBase some kind.
+ // We use a local ValueHandleBase as an iterator so that ValueHandles can add
+ // and remove themselves from the list without breaking our iteration. This
+ // is not really an AssertingVH; we just have to give ValueHandleBase a kind.
+ // Note that we deliberately do not the support the case when dropping a value
+ // handle results in a new value handle being permanently added to the list
+ // (as might occur in theory for CallbackVH's): the new value handle will not
+ // be processed and the checking code will mete out righteous punishment if
+ // the handle is still present once we have finished processing all the other
+ // value handles (it is fine to momentarily add then remove a value handle).
for (ValueHandleBase Iterator(Assert, *Entry); Entry; Entry = Iterator.Next) {
Iterator.RemoveFromUseList();
Iterator.AddToExistingUseListAfter(Entry);
@@ -576,6 +577,24 @@
break;
}
}
+
+#ifndef NDEBUG
+ // If any new tracking or weak value handles were added while processing the
+ // list, then complain about it now.
+ if (Old->HasValueHandle)
+ for (Entry = pImpl->ValueHandles[Old]; Entry; Entry = Entry->Next)
+ switch (Entry->getKind()) {
+ case Tracking:
+ case Weak:
+ dbgs() << "After RAUW from " << *Old->getType() << " %"
+ << Old->getNameStr() << " to " << *New->getType() << " %"
+ << New->getNameStr() << "\n";
+ llvm_unreachable("A tracking or weak value handle still pointed to the"
+ " old value!\n");
+ default:
+ break;
+ }
+#endif
}
/// ~CallbackVH. Empty, but defined here to avoid emitting the vtable
Modified: llvm/branches/wendling/eh/lib/VMCore/ValueSymbolTable.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/ValueSymbolTable.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/ValueSymbolTable.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/ValueSymbolTable.cpp Sat Jul 31 19:59:02 2010
@@ -115,5 +115,3 @@
//DEBUG(dbgs() << "\n");
}
}
-
-MDSymbolTable::~MDSymbolTable() { }
Modified: llvm/branches/wendling/eh/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/lib/VMCore/Verifier.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/lib/VMCore/Verifier.cpp (original)
+++ llvm/branches/wendling/eh/lib/VMCore/Verifier.cpp Sat Jul 31 19:59:02 2010
@@ -504,8 +504,8 @@
if (!MD)
continue;
- Assert2(!MD->isFunctionLocal(),
- "Named metadata operand cannot be function local!", &NMD, MD);
+ Assert1(!MD->isFunctionLocal(),
+ "Named metadata operand cannot be function local!", MD);
visitMDNode(*MD, 0);
}
}
@@ -520,7 +520,7 @@
Value *Op = MD.getOperand(i);
if (!Op)
continue;
- if (isa<Constant>(Op) || isa<MDString>(Op) || isa<NamedMDNode>(Op))
+ if (isa<Constant>(Op) || isa<MDString>(Op))
continue;
if (MDNode *N = dyn_cast<MDNode>(Op)) {
Assert2(MD.isFunctionLocal() || !N->isFunctionLocal(),
Propchange: llvm/branches/wendling/eh/test/Analysis/RegionInfo/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -0,0 +1 @@
+Output
Modified: llvm/branches/wendling/eh/test/CodeGen/ARM/arguments.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/ARM/arguments.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/ARM/arguments.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/ARM/arguments.ll Sat Jul 31 19:59:02 2010
@@ -1,11 +1,29 @@
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
-; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=arm-linux-gnueabi -mattr=+vfp2 | FileCheck %s -check-prefix=ELF
+; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
-define i32 @f(i32 %a, i64 %b) {
+define i32 @f1(i32 %a, i64 %b) {
+; ELF: f1:
; ELF: mov r0, r2
+; DARWIN: f1:
; DARWIN: mov r0, r1
- %tmp = call i32 @g(i64 %b)
+ %tmp = call i32 @g1(i64 %b)
ret i32 %tmp
}
-declare i32 @g(i64)
+; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
+define i32 @f2() nounwind optsize {
+; ELF: f2:
+; ELF: mov r0, #128
+; ELF: str r0, [sp]
+; DARWIN: f2:
+; DARWIN: mov r3, #128
+entry:
+ %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
+ %not. = icmp ne i32 %0, 128 ; <i1> [#uses=1]
+ %.0 = zext i1 %not. to i32 ; <i32> [#uses=1]
+ ret i32 %.0
+}
+
+declare i32 @g1(i64)
+
+declare i32 @g2(i32 %i, ...)
Modified: llvm/branches/wendling/eh/test/CodeGen/ARM/lsr-on-unrolled-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Sat Jul 31 19:59:02 2010
@@ -4,14 +4,14 @@
; constant offset addressing, so that each of the following stores
; uses the same register.
-; CHECK: vstr.32 s0, [r9, #-128]
-; CHECK: vstr.32 s0, [r9, #-96]
-; CHECK: vstr.32 s0, [r9, #-64]
-; CHECK: vstr.32 s0, [r9, #-32]
-; CHECK: vstr.32 s0, [r9]
-; CHECK: vstr.32 s0, [r9, #32]
-; CHECK: vstr.32 s0, [r9, #64]
-; CHECK: vstr.32 s0, [r9, #96]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-128]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-96]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-64]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #-32]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #32]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #64]
+; CHECK: vstr.32 s{{.*}}, [r{{.*}}, #96]
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
Modified: llvm/branches/wendling/eh/test/CodeGen/CellSPU/call_indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/CellSPU/call_indirect.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/CellSPU/call_indirect.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/CellSPU/call_indirect.ll Sat Jul 31 19:59:02 2010
@@ -12,7 +12,7 @@
; RUN: grep rotqby %t2.s | count 5
; RUN: grep lqd %t2.s | count 13
; RUN: grep ilhu %t2.s | count 2
-; RUN: grep ai %t2.s | count 8
+; RUN: grep ai %t2.s | count 9
; RUN: grep dispatch_tab %t2.s | count 6
; ModuleID = 'call_indirect.bc'
Removed: llvm/branches/wendling/eh/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (removed)
@@ -1,8 +0,0 @@
-; RUN: llc < %s -march=ppc32 | grep nop
-target triple = "powerpc-apple-darwin8"
-
-
-define void @bork() noreturn nounwind {
-entry:
- unreachable
-}
Modified: llvm/branches/wendling/eh/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Sat Jul 31 19:59:02 2010
@@ -7,15 +7,17 @@
define void @t() nounwind ssp {
entry:
; CHECK: t:
-; CHECK: mov r0, sp
-; CHECK: bfc r0, #0, #3
-; CHECK: subs r0, #16
-; CHECK: mov sp, r0
-; Yes, this is stupid codegen, but it's correct.
-; CHECK: mov r0, sp
-; CHECK: bfc r0, #0, #3
-; CHECK: subs r0, #16
-; CHECK: mov sp, r0
+; CHECK: push {r4, r7}
+; CHECK: mov r0, sp
+; CHECK: add r7, sp, #4
+; CHECK: bic r0, r0, #7
+; CHECK: subs r0, #16
+; CHECK: mov sp, r0
+; CHECK: mov r0, sp
+; CHECK: bic r0, r0, #7
+; CHECK: subs r0, #16
+; CHECK: mov sp, r0
+
%size = mul i32 8, 2
%vla_a = alloca i8, i32 %size, align 8
%vla_b = alloca i8, i32 %size, align 8
Modified: llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-and2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-and2.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-and2.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-and2.ll Sat Jul 31 19:59:02 2010
@@ -30,7 +30,7 @@
ret i32 %tmp
}
; CHECK: f4:
-; CHECK: and r0, r0, #1448498774
+; CHECK: bic r0, r0, #-1448498775
; 66846720 = 0x03fc0000
define i32 @f5(i32 %a) {
Modified: llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-uxtb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-uxtb.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-uxtb.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/Thumb2/thumb2-uxtb.ll Sat Jul 31 19:59:02 2010
@@ -6,7 +6,7 @@
; ARMv7A: uxtb16 r0, r0
; ARMv7M: test1
-; ARMv7M: and r0, r0, #16711935
+; ARMv7M: bic r0, r0, #-16711936
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/2006-05-22-FPSetEQ.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/2006-05-22-FPSetEQ.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/2006-05-22-FPSetEQ.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Sat Jul 31 19:59:02 2010
@@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 | grep setnp
-; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-finite-only-fp-math | \
+; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-no-nans-fp-math | \
; RUN: not grep setnp
define i32 @test(float %f) {
Removed: llvm/branches/wendling/eh/test/CodeGen/X86/2007-06-14-branchfold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/2007-06-14-branchfold.ll?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/2007-06-14-branchfold.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/2007-06-14-branchfold.ll (removed)
@@ -1,133 +0,0 @@
-; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp
-; check that branch folding understands FP_REG_KILL is not a branch
-
-target triple = "i686-pc-linux-gnu"
- %struct.FRAME.c34003a = type { float, float }
- at report_E = global i8 0 ; <i8*> [#uses=0]
-
-define void @main() {
-entry:
- %FRAME.31 = alloca %struct.FRAME.c34003a, align 8 ; <%struct.FRAME.c34003a*> [#uses=4]
- %tmp20 = call i32 @report__ident_int( i32 -50 ) ; <i32> [#uses=1]
- %tmp2021 = sitofp i32 %tmp20 to float ; <float> [#uses=5]
- %tmp23 = fcmp ult float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
- %tmp26 = fcmp ugt float %tmp2021, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
- %bothcond = or i1 %tmp23, %tmp26 ; <i1> [#uses=1]
- br i1 %bothcond, label %bb, label %bb30
-
-bb: ; preds = %entry
- unwind
-
-bb30: ; preds = %entry
- %tmp35 = call i32 @report__ident_int( i32 50 ) ; <i32> [#uses=1]
- %tmp3536 = sitofp i32 %tmp35 to float ; <float> [#uses=4]
- %tmp38 = fcmp ult float %tmp3536, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
- %tmp44 = fcmp ugt float %tmp3536, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
- %bothcond226 = or i1 %tmp38, %tmp44 ; <i1> [#uses=1]
- br i1 %bothcond226, label %bb47, label %bb49
-
-bb47: ; preds = %bb30
- unwind
-
-bb49: ; preds = %bb30
- %tmp60 = fcmp ult float %tmp3536, %tmp2021 ; <i1> [#uses=1]
- %tmp60.not = xor i1 %tmp60, true ; <i1> [#uses=1]
- %tmp65 = fcmp olt float %tmp2021, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
- %bothcond227 = and i1 %tmp65, %tmp60.not ; <i1> [#uses=1]
- br i1 %bothcond227, label %cond_true68, label %cond_next70
-
-cond_true68: ; preds = %bb49
- unwind
-
-cond_next70: ; preds = %bb49
- %tmp71 = call i32 @report__ident_int( i32 -30 ) ; <i32> [#uses=1]
- %tmp7172 = sitofp i32 %tmp71 to float ; <float> [#uses=3]
- %tmp74 = fcmp ult float %tmp7172, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
- %tmp80 = fcmp ugt float %tmp7172, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
- %bothcond228 = or i1 %tmp74, %tmp80 ; <i1> [#uses=1]
- br i1 %bothcond228, label %bb83, label %bb85
-
-bb83: ; preds = %cond_next70
- unwind
-
-bb85: ; preds = %cond_next70
- %tmp90 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 1 ; <float*> [#uses=3]
- store float %tmp7172, float* %tmp90
- %tmp92 = call i32 @report__ident_int( i32 30 ) ; <i32> [#uses=1]
- %tmp9293 = sitofp i32 %tmp92 to float ; <float> [#uses=7]
- %tmp95 = fcmp ult float %tmp9293, 0xC7EFFFFFE0000000 ; <i1> [#uses=1]
- %tmp101 = fcmp ugt float %tmp9293, 0x47EFFFFFE0000000 ; <i1> [#uses=1]
- %bothcond229 = or i1 %tmp95, %tmp101 ; <i1> [#uses=1]
- br i1 %bothcond229, label %bb104, label %bb106
-
-bb104: ; preds = %bb85
- unwind
-
-bb106: ; preds = %bb85
- %tmp111 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 0 ; <float*> [#uses=2]
- store float %tmp9293, float* %tmp111
- %tmp123 = load float* %tmp90 ; <float> [#uses=4]
- %tmp125 = fcmp ult float %tmp9293, %tmp123 ; <i1> [#uses=1]
- br i1 %tmp125, label %cond_next147, label %cond_true128
-
-cond_true128: ; preds = %bb106
- %tmp133 = fcmp olt float %tmp123, %tmp2021 ; <i1> [#uses=1]
- %tmp142 = fcmp ogt float %tmp9293, %tmp3536 ; <i1> [#uses=1]
- %bothcond230 = or i1 %tmp133, %tmp142 ; <i1> [#uses=1]
- br i1 %bothcond230, label %bb145, label %cond_next147
-
-bb145: ; preds = %cond_true128
- unwind
-
-cond_next147: ; preds = %cond_true128, %bb106
- %tmp157 = fcmp ugt float %tmp123, -3.000000e+01 ; <i1> [#uses=1]
- %tmp165 = fcmp ult float %tmp9293, -3.000000e+01 ; <i1> [#uses=1]
- %bothcond231 = or i1 %tmp157, %tmp165 ; <i1> [#uses=1]
- br i1 %bothcond231, label %bb168, label %bb169
-
-bb168: ; preds = %cond_next147
- unwind
-
-bb169: ; preds = %cond_next147
- %tmp176 = fcmp ugt float %tmp123, 3.000000e+01 ; <i1> [#uses=1]
- %tmp184 = fcmp ult float %tmp9293, 3.000000e+01 ; <i1> [#uses=1]
- %bothcond232 = or i1 %tmp176, %tmp184 ; <i1> [#uses=1]
- br i1 %bothcond232, label %bb187, label %bb188
-
-bb187: ; preds = %bb169
- unwind
-
-bb188: ; preds = %bb169
- %tmp192 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 3.000000e+01 ) ; <float> [#uses=2]
- %tmp194 = load float* %tmp90 ; <float> [#uses=1]
- %tmp196 = fcmp ugt float %tmp194, 0.000000e+00 ; <i1> [#uses=1]
- br i1 %tmp196, label %bb207, label %cond_next200
-
-cond_next200: ; preds = %bb188
- %tmp202 = load float* %tmp111 ; <float> [#uses=1]
- %tmp204 = fcmp ult float %tmp202, 0.000000e+00 ; <i1> [#uses=1]
- br i1 %tmp204, label %bb207, label %bb208
-
-bb207: ; preds = %cond_next200, %bb188
- unwind
-
-bb208: ; preds = %cond_next200
- %tmp212 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 0.000000e+00 ) ; <float> [#uses=1]
- %tmp214 = fcmp oge float %tmp212, %tmp192 ; <i1> [#uses=1]
- %tmp217 = fcmp oge float %tmp192, 1.000000e+02 ; <i1> [#uses=1]
- %tmp221 = or i1 %tmp214, %tmp217 ; <i1> [#uses=1]
- br i1 %tmp221, label %cond_true224, label %UnifiedReturnBlock
-
-cond_true224: ; preds = %bb208
- call void @abort( ) noreturn
- ret void
-
-UnifiedReturnBlock: ; preds = %bb208
- ret void
-}
-
-declare fastcc float @c34003a__ident.154(%struct.FRAME.c34003a* %CHAIN.32, float %x)
-
-declare i32 @report__ident_int(i32 %x)
-
-declare void @abort() noreturn
Removed: llvm/branches/wendling/eh/test/CodeGen/X86/2008-01-25-EmptyFunction.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/2008-01-25-EmptyFunction.ll?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (removed)
@@ -1,8 +0,0 @@
-; RUN: llc < %s -march=x86 | grep nop
-target triple = "i686-apple-darwin8"
-
-
-define void @bork() noreturn nounwind {
-entry:
- unreachable
-}
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/fabs.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/fabs.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/fabs.ll Sat Jul 31 19:59:02 2010
@@ -1,7 +1,7 @@
; Make sure this testcase codegens to the fabs instruction, not a call to fabsf
; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \
; RUN: count 2
-; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-finite-only-fp-math | \
+; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-no-nans-fp-math | \
; RUN: grep fabs\$ | count 3
declare float @fabsf(float)
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-gep.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-gep.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-gep.ll Sat Jul 31 19:59:02 2010
@@ -9,7 +9,7 @@
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
; X32: test1:
-; X32: movl (%ecx,%eax,4), %eax
+; X32: movl (%eax,%ecx,4), %eax
; X32: ret
; X64: test1:
@@ -23,7 +23,7 @@
%t15 = load i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
; X32: test2:
-; X32: movl (%eax,%ecx,4), %eax
+; X32: movl (%edx,%ecx,4), %eax
; X32: ret
; X64: test2:
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/fast-isel-shift-imm.ll Sat Jul 31 19:59:02 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %eax}
+; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %e}
; PR3242
define void @foo(i32 %x, i32* %p) nounwind {
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/global-sections.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/global-sections.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/global-sections.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/global-sections.ll Sat Jul 31 19:59:02 2010
@@ -20,7 +20,7 @@
; TODO: linux drops this into .rodata, we drop it into ".gnu.linkonce.r.G2"
-; DARWIN: .section __TEXT,__const_coal,coalesced
+; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions
; DARWIN: _G2:
; DARWIN: .long 42
@@ -85,7 +85,7 @@
; LINUX: .byte 1
; LINUX: .size G6, 1
-; DARWIN: .section __TEXT,__const_coal,coalesced
+; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions
; DARWIN: .globl _G6
; DARWIN: .weak_definition _G6
; DARWIN:_G6:
Modified: llvm/branches/wendling/eh/test/CodeGen/X86/sse-minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/CodeGen/X86/sse-minmax.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/CodeGen/X86/sse-minmax.ll (original)
+++ llvm/branches/wendling/eh/test/CodeGen/X86/sse-minmax.ll Sat Jul 31 19:59:02 2010
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s
-; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=UNSAFE %s
-; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
+; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s
; Some of these patterns can be matched as SSE min or max. Some of
; then can be matched provided that the operands are swapped.
Modified: llvm/branches/wendling/eh/test/Feature/NamedMDNode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Feature/NamedMDNode.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Feature/NamedMDNode.ll (original)
+++ llvm/branches/wendling/eh/test/Feature/NamedMDNode.ll Sat Jul 31 19:59:02 2010
@@ -3,7 +3,7 @@
;; Simple NamedMDNode
!0 = metadata !{i32 42}
!1 = metadata !{metadata !"foo"}
-!llvm.stuff = !{!0, !1, null}
+!llvm.stuff = !{!0, !1}
!samename = !{!0, !1}
declare void @samename()
Modified: llvm/branches/wendling/eh/test/FrontendC++/2009-07-15-LineNumbers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/FrontendC%2B%2B/2009-07-15-LineNumbers.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/FrontendC++/2009-07-15-LineNumbers.cpp (original)
+++ llvm/branches/wendling/eh/test/FrontendC++/2009-07-15-LineNumbers.cpp Sat Jul 31 19:59:02 2010
@@ -1,7 +1,7 @@
// This is a regression test on debug info to make sure that we can
// print line numbers in asm.
// RUN: %llvmgcc -S -O0 -g %s -o - | \
-// RUN: llc --disable-fp-elim -O0 -relocation-model=pic | grep { 2009-07-15-LineNumbers.cpp:25$}
+// RUN: llc --disable-fp-elim -O0 -relocation-model=pic | grep {2009-07-15-LineNumbers.cpp:25$}
#include <stdlib.h>
Modified: llvm/branches/wendling/eh/test/FrontendC/vla-1.c
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/FrontendC/vla-1.c?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/FrontendC/vla-1.c (original)
+++ llvm/branches/wendling/eh/test/FrontendC/vla-1.c Sat Jul 31 19:59:02 2010
@@ -1,5 +1,6 @@
-// RUN: true
-// %llvmgcc -std=gnu99 %s -S |& grep {error: "is greater than the stack alignment" }
+// RUN: %llvmgcc_only -std=gnu99 %s -S |& grep {warning: alignment for}
+// ppc does not support this feature, and gets a fatal error at runtime.
+// XFAIL: powerpc
int foo(int a)
{
Modified: llvm/branches/wendling/eh/test/FrontendObjC/2009-08-17-DebugInfo.m
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/FrontendObjC/2009-08-17-DebugInfo.m?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/FrontendObjC/2009-08-17-DebugInfo.m (original)
+++ llvm/branches/wendling/eh/test/FrontendObjC/2009-08-17-DebugInfo.m Sat Jul 31 19:59:02 2010
@@ -5,7 +5,7 @@
// RUN: %link %t.o -o %t.exe -framework Foundation
// RUN: echo {break randomFunc\n} > %t.in
// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \
-// RUN: grep {Breakpoint 1 at 0x.*: file 2009-08-17-DebugInfo.m, line 21}
+// RUN: grep {Breakpoint 1 at 0x.*: file .*2009-08-17-DebugInfo.m, line 21}
// XTARGET: darwin
@interface MyClass
{
Propchange: llvm/branches/wendling/eh/test/MC/AsmParser/ELF/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -0,0 +1 @@
+Output
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-encoding.s Sat Jul 31 19:59:02 2010
@@ -10047,2882 +10047,23 @@
// CHECK: encoding: [0xde,0x1d,0xed,0x7e,0x00,0x00]
ficomps 32493
-// CHECK: vaddss %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0x58,0xd4]
- vaddss %xmm4, %xmm6, %xmm2
-
-// CHECK: vmulss %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0x59,0xd4]
- vmulss %xmm4, %xmm6, %xmm2
-
-// CHECK: vsubss %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0x5c,0xd4]
- vsubss %xmm4, %xmm6, %xmm2
-
-// CHECK: vdivss %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0x5e,0xd4]
- vdivss %xmm4, %xmm6, %xmm2
-
-// CHECK: vaddsd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0x58,0xd4]
- vaddsd %xmm4, %xmm6, %xmm2
-
-// CHECK: vmulsd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0x59,0xd4]
- vmulsd %xmm4, %xmm6, %xmm2
-
-// CHECK: vsubsd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0x5c,0xd4]
- vsubsd %xmm4, %xmm6, %xmm2
-
-// CHECK: vdivsd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0x5e,0xd4]
- vdivsd %xmm4, %xmm6, %xmm2
-
-// CHECK: vaddss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vaddss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vsubss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vsubss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmulss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vmulss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vdivss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vdivss 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vaddsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vaddsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vsubsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vsubsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmulsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vmulsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vdivsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vdivsd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vaddps %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0x58,0xd4]
- vaddps %xmm4, %xmm6, %xmm2
-
-// CHECK: vsubps %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0x5c,0xd4]
- vsubps %xmm4, %xmm6, %xmm2
-
-// CHECK: vmulps %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0x59,0xd4]
- vmulps %xmm4, %xmm6, %xmm2
-
-// CHECK: vdivps %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0x5e,0xd4]
- vdivps %xmm4, %xmm6, %xmm2
-
-// CHECK: vaddpd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0x58,0xd4]
- vaddpd %xmm4, %xmm6, %xmm2
-
-// CHECK: vsubpd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0x5c,0xd4]
- vsubpd %xmm4, %xmm6, %xmm2
-
-// CHECK: vmulpd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0x59,0xd4]
- vmulpd %xmm4, %xmm6, %xmm2
-
-// CHECK: vdivpd %xmm4, %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0x5e,0xd4]
- vdivpd %xmm4, %xmm6, %xmm2
-
-// CHECK: vaddps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vaddps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vsubps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vsubps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmulps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vmulps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vdivps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vdivps 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vaddpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x58,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vaddpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vsubpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x5c,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vsubpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmulpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x59,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vmulpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
- vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: vmaxss %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xda,0x5f,0xf2]
- vmaxss %xmm2, %xmm4, %xmm6
-
-// CHECK: vmaxsd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xdb,0x5f,0xf2]
- vmaxsd %xmm2, %xmm4, %xmm6
-
-// CHECK: vminss %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xda,0x5d,0xf2]
- vminss %xmm2, %xmm4, %xmm6
-
-// CHECK: vminsd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xdb,0x5d,0xf2]
- vminsd %xmm2, %xmm4, %xmm6
-
-// CHECK: vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x5f,0x6c,0xcb,0xfc]
- vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x5f,0x6c,0xcb,0xfc]
- vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vminss -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x5d,0x6c,0xcb,0xfc]
- vminss -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x5d,0x6c,0xcb,0xfc]
- vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmaxps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x5f,0xf2]
- vmaxps %xmm2, %xmm4, %xmm6
-
-// CHECK: vmaxpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x5f,0xf2]
- vmaxpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vminps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x5d,0xf2]
- vminps %xmm2, %xmm4, %xmm6
-
-// CHECK: vminpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x5d,0xf2]
- vminpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x5f,0x6c,0xcb,0xfc]
- vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x5f,0x6c,0xcb,0xfc]
- vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vminps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x5d,0x6c,0xcb,0xfc]
- vminps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x5d,0x6c,0xcb,0xfc]
- vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vandps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x54,0xf2]
- vandps %xmm2, %xmm4, %xmm6
-
-// CHECK: vandpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x54,0xf2]
- vandpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vandps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x54,0x6c,0xcb,0xfc]
- vandps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x54,0x6c,0xcb,0xfc]
- vandpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vorps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x56,0xf2]
- vorps %xmm2, %xmm4, %xmm6
-
-// CHECK: vorpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x56,0xf2]
- vorpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vorps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x56,0x6c,0xcb,0xfc]
- vorps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x56,0x6c,0xcb,0xfc]
- vorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vxorps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x57,0xf2]
- vxorps %xmm2, %xmm4, %xmm6
-
-// CHECK: vxorpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x57,0xf2]
- vxorpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x57,0x6c,0xcb,0xfc]
- vxorps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x57,0x6c,0xcb,0xfc]
- vxorpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vandnps %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd8,0x55,0xf2]
- vandnps %xmm2, %xmm4, %xmm6
-
-// CHECK: vandnpd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xd9,0x55,0xf2]
- vandnpd %xmm2, %xmm4, %xmm6
-
-// CHECK: vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x55,0x6c,0xcb,0xfc]
- vandnps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x55,0x6c,0xcb,0xfc]
- vandnpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vmovss -4(%ebx,%ecx,8), %xmm5
-// CHECK: encoding: [0xc5,0xfa,0x10,0x6c,0xcb,0xfc]
- vmovss -4(%ebx,%ecx,8), %xmm5
-
-// CHECK: vmovss %xmm4, %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xea,0x10,0xec]
- vmovss %xmm4, %xmm2, %xmm5
-
-// CHECK: vmovsd -4(%ebx,%ecx,8), %xmm5
-// CHECK: encoding: [0xc5,0xfb,0x10,0x6c,0xcb,0xfc]
- vmovsd -4(%ebx,%ecx,8), %xmm5
-
-// CHECK: vmovsd %xmm4, %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xeb,0x10,0xec]
- vmovsd %xmm4, %xmm2, %xmm5
-
-// CHECK: vunpckhps %xmm1, %xmm2, %xmm4
-// CHECK: encoding: [0xc5,0xe8,0x15,0xe1]
- vunpckhps %xmm1, %xmm2, %xmm4
-
-// CHECK: vunpckhpd %xmm1, %xmm2, %xmm4
-// CHECK: encoding: [0xc5,0xe9,0x15,0xe1]
- vunpckhpd %xmm1, %xmm2, %xmm4
-
-// CHECK: vunpcklps %xmm1, %xmm2, %xmm4
-// CHECK: encoding: [0xc5,0xe8,0x14,0xe1]
- vunpcklps %xmm1, %xmm2, %xmm4
-
-// CHECK: vunpcklpd %xmm1, %xmm2, %xmm4
-// CHECK: encoding: [0xc5,0xe9,0x14,0xe1]
- vunpcklpd %xmm1, %xmm2, %xmm4
-
-// CHECK: vunpckhps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x15,0x6c,0xcb,0xfc]
- vunpckhps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vunpckhpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x15,0x6c,0xcb,0xfc]
- vunpckhpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vunpcklps -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe8,0x14,0x6c,0xcb,0xfc]
- vunpcklps -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vunpcklpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0x14,0x6c,0xcb,0xfc]
- vunpcklpd -4(%ebx,%ecx,8), %xmm2, %xmm5
-
-// CHECK: vcmpps $0, %xmm0, %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc8,0xc2,0xc8,0x00]
- vcmpps $0, %xmm0, %xmm6, %xmm1
-
-// CHECK: vcmpps $0, (%eax), %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc8,0xc2,0x08,0x00]
- vcmpps $0, (%eax), %xmm6, %xmm1
-
-// CHECK: vcmpps $7, %xmm0, %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc8,0xc2,0xc8,0x07]
- vcmpps $7, %xmm0, %xmm6, %xmm1
-
-// CHECK: vcmppd $0, %xmm0, %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc9,0xc2,0xc8,0x00]
- vcmppd $0, %xmm0, %xmm6, %xmm1
-
-// CHECK: vcmppd $0, (%eax), %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc9,0xc2,0x08,0x00]
- vcmppd $0, (%eax), %xmm6, %xmm1
-
-// CHECK: vcmppd $7, %xmm0, %xmm6, %xmm1
-// CHECK: encoding: [0xc5,0xc9,0xc2,0xc8,0x07]
- vcmppd $7, %xmm0, %xmm6, %xmm1
-
-// CHECK: vshufps $8, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc6,0xd9,0x08]
- vshufps $8, %xmm1, %xmm2, %xmm3
-
-// CHECK: vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc6,0x5c,0xcb,0xfc,0x08]
- vshufps $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vshufpd $8, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc6,0xd9,0x08]
- vshufpd $8, %xmm1, %xmm2, %xmm3
-
-// CHECK: vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc6,0x5c,0xcb,0xfc,0x08]
- vshufpd $8, -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $0, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x00]
- vcmpeqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $2, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x02]
- vcmpleps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $1, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x01]
- vcmpltps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $4, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x04]
- vcmpneqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $6, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x06]
- vcmpnleps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $5, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x05]
- vcmpnltps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x07]
- vcmpordps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $3, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x03]
- vcmpunordps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmpleps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnleps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpps $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordps -4(%ebx,%ecx,8), %xmm6, %xmm2
-
-// CHECK: vcmpps $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordps -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $0, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x00]
- vcmpeqpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $2, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x02]
- vcmplepd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $1, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x01]
- vcmpltpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $4, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x04]
- vcmpneqpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $6, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x06]
- vcmpnlepd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $5, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x05]
- vcmpnltpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x07]
- vcmpordpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $3, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0xd9,0x03]
- vcmpunordpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmppd $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqpd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmplepd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltpd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqpd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnlepd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltpd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmppd $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordpd -4(%ebx,%ecx,8), %xmm6, %xmm2
-
-// CHECK: vcmppd $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordpd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vmovmskps %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf8,0x50,0xc2]
- vmovmskps %xmm2, %eax
-
-// CHECK: vmovmskpd %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf9,0x50,0xc2]
- vmovmskpd %xmm2, %eax
-
-// CHECK: vcmpss $0, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x00]
- vcmpeqss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $2, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x02]
- vcmpless %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $1, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x01]
- vcmpltss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $4, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x04]
- vcmpneqss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $6, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x06]
- vcmpnless %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $5, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x05]
- vcmpnltss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x07]
- vcmpordss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $3, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0xd9,0x03]
- vcmpunordss %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpss $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqss -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmpless -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltss -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqss -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnless -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltss -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpss $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordss -4(%ebx,%ecx,8), %xmm6, %xmm2
-
-// CHECK: vcmpss $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordss -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $0, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x00]
- vcmpeqsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $2, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x02]
- vcmplesd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $1, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x01]
- vcmpltsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $4, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x04]
- vcmpneqsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $6, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x06]
- vcmpnlesd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $5, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x05]
- vcmpnltsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x07]
- vcmpordsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $3, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0xd9,0x03]
- vcmpunordsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpsd $0, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqsd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $2, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmplesd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $1, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltsd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $4, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqsd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $6, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnlesd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $5, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltsd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vcmpsd $7, -4(%ebx,%ecx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordsd -4(%ebx,%ecx,8), %xmm6, %xmm2
-
-// CHECK: vcmpsd $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordsd -4(%ebx,%ecx,8), %xmm2, %xmm3
-
-// CHECK: vucomiss %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x2e,0xd1]
- vucomiss %xmm1, %xmm2
-
-// CHECK: vucomiss (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x2e,0x10]
- vucomiss (%eax), %xmm2
-
-// CHECK: vcomiss %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x2f,0xd1]
- vcomiss %xmm1, %xmm2
-
-// CHECK: vcomiss (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x2f,0x10]
- vcomiss (%eax), %xmm2
-
-// CHECK: vucomisd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x2e,0xd1]
- vucomisd %xmm1, %xmm2
-
-// CHECK: vucomisd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x2e,0x10]
- vucomisd (%eax), %xmm2
-
-// CHECK: vcomisd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x2f,0xd1]
- vcomisd %xmm1, %xmm2
-
-// CHECK: vcomisd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x2f,0x10]
- vcomisd (%eax), %xmm2
-
-// CHECK: vcvttss2si %xmm1, %eax
-// CHECK: encoding: [0xc5,0xfa,0x2c,0xc1]
- vcvttss2si %xmm1, %eax
-
-// CHECK: vcvttss2si (%ecx), %eax
-// CHECK: encoding: [0xc5,0xfa,0x2c,0x01]
- vcvttss2si (%ecx), %eax
-
-// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
- vcvtsi2ss (%eax), %xmm1, %xmm2
-
-// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
- vcvtsi2ss (%eax), %xmm1, %xmm2
-
-// CHECK: vcvttsd2si %xmm1, %eax
-// CHECK: encoding: [0xc5,0xfb,0x2c,0xc1]
- vcvttsd2si %xmm1, %eax
-
-// CHECK: vcvttsd2si (%ecx), %eax
-// CHECK: encoding: [0xc5,0xfb,0x2c,0x01]
- vcvttsd2si (%ecx), %eax
-
-// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
- vcvtsi2sd (%eax), %xmm1, %xmm2
-
-// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
- vcvtsi2sd (%eax), %xmm1, %xmm2
-
-// CHECK: vmovaps (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x28,0x10]
- vmovaps (%eax), %xmm2
-
-// CHECK: vmovaps %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x28,0xd1]
- vmovaps %xmm1, %xmm2
-
-// CHECK: vmovaps %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf8,0x29,0x08]
- vmovaps %xmm1, (%eax)
-
-// CHECK: vmovapd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x28,0x10]
- vmovapd (%eax), %xmm2
-
-// CHECK: vmovapd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x28,0xd1]
- vmovapd %xmm1, %xmm2
-
-// CHECK: vmovapd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x29,0x08]
- vmovapd %xmm1, (%eax)
-
-// CHECK: vmovups (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x10,0x10]
- vmovups (%eax), %xmm2
-
-// CHECK: vmovups %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x10,0xd1]
- vmovups %xmm1, %xmm2
-
-// CHECK: vmovups %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf8,0x11,0x08]
- vmovups %xmm1, (%eax)
-
-// CHECK: vmovupd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x10,0x10]
- vmovupd (%eax), %xmm2
-
-// CHECK: vmovupd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x10,0xd1]
- vmovupd %xmm1, %xmm2
-
-// CHECK: vmovupd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x11,0x08]
- vmovupd %xmm1, (%eax)
-
-// CHECK: vmovlps %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf8,0x13,0x08]
- vmovlps %xmm1, (%eax)
-
-// CHECK: vmovlps (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0x12,0x18]
- vmovlps (%eax), %xmm2, %xmm3
-
-// CHECK: vmovlpd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x13,0x08]
- vmovlpd %xmm1, (%eax)
-
-// CHECK: vmovlpd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x12,0x18]
- vmovlpd (%eax), %xmm2, %xmm3
-
-// CHECK: vmovhps %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf8,0x17,0x08]
- vmovhps %xmm1, (%eax)
-
-// CHECK: vmovhps (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0x16,0x18]
- vmovhps (%eax), %xmm2, %xmm3
-
-// CHECK: vmovhpd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x17,0x08]
- vmovhpd %xmm1, (%eax)
-
-// CHECK: vmovhpd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x16,0x18]
- vmovhpd (%eax), %xmm2, %xmm3
-
-// CHECK: vmovlhps %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0x16,0xd9]
- vmovlhps %xmm1, %xmm2, %xmm3
-
-// CHECK: vmovhlps %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0x12,0xd9]
- vmovhlps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcvtss2sil %xmm1, %eax
-// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1]
- vcvtss2si %xmm1, %eax
-
-// CHECK: vcvtss2sil (%eax), %ebx
-// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
- vcvtss2si (%eax), %ebx
-
-// CHECK: vcvtdq2ps %xmm5, %xmm6
-// CHECK: encoding: [0xc5,0xf8,0x5b,0xf5]
- vcvtdq2ps %xmm5, %xmm6
-
-// CHECK: vcvtdq2ps (%eax), %xmm6
-// CHECK: encoding: [0xc5,0xf8,0x5b,0x30]
- vcvtdq2ps (%eax), %xmm6
-
-// CHECK: vcvtsd2ss %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xdb,0x5a,0xf2]
- vcvtsd2ss %xmm2, %xmm4, %xmm6
-
-// CHECK: vcvtsd2ss (%eax), %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xdb,0x5a,0x30]
- vcvtsd2ss (%eax), %xmm4, %xmm6
-
-// CHECK: vcvtps2dq %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xf9,0x5b,0xda]
- vcvtps2dq %xmm2, %xmm3
-
-// CHECK: vcvtps2dq (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xf9,0x5b,0x18]
- vcvtps2dq (%eax), %xmm3
-
-// CHECK: vcvtss2sd %xmm2, %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xda,0x5a,0xf2]
- vcvtss2sd %xmm2, %xmm4, %xmm6
-
-// CHECK: vcvtss2sd (%eax), %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xda,0x5a,0x30]
- vcvtss2sd (%eax), %xmm4, %xmm6
-
-// CHECK: vcvtdq2ps %xmm4, %xmm6
-// CHECK: encoding: [0xc5,0xf8,0x5b,0xf4]
- vcvtdq2ps %xmm4, %xmm6
-
-// CHECK: vcvtdq2ps (%ecx), %xmm4
-// CHECK: encoding: [0xc5,0xf8,0x5b,0x21]
- vcvtdq2ps (%ecx), %xmm4
-
-// CHECK: vcvttps2dq %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xfa,0x5b,0xda]
- vcvttps2dq %xmm2, %xmm3
-
-// CHECK: vcvttps2dq (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xfa,0x5b,0x18]
- vcvttps2dq (%eax), %xmm3
-
-// CHECK: vcvtps2pd %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xf8,0x5a,0xda]
- vcvtps2pd %xmm2, %xmm3
-
-// CHECK: vcvtps2pd (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xf8,0x5a,0x18]
- vcvtps2pd (%eax), %xmm3
-
-// CHECK: vcvtpd2ps %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xf9,0x5a,0xda]
- vcvtpd2ps %xmm2, %xmm3
-
-// CHECK: vsqrtpd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x51,0xd1]
- vsqrtpd %xmm1, %xmm2
-
-// CHECK: vsqrtpd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf9,0x51,0x10]
- vsqrtpd (%eax), %xmm2
-
-// CHECK: vsqrtps %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x51,0xd1]
- vsqrtps %xmm1, %xmm2
-
-// CHECK: vsqrtps (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x51,0x10]
- vsqrtps (%eax), %xmm2
-
-// CHECK: vsqrtsd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x51,0xd9]
- vsqrtsd %xmm1, %xmm2, %xmm3
-
-// CHECK: vsqrtsd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x51,0x18]
- vsqrtsd (%eax), %xmm2, %xmm3
-
-// CHECK: vsqrtss %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x51,0xd9]
- vsqrtss %xmm1, %xmm2, %xmm3
-
-// CHECK: vsqrtss (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x51,0x18]
- vsqrtss (%eax), %xmm2, %xmm3
-
-// CHECK: vrsqrtps %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x52,0xd1]
- vrsqrtps %xmm1, %xmm2
-
-// CHECK: vrsqrtps (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x52,0x10]
- vrsqrtps (%eax), %xmm2
-
-// CHECK: vrsqrtss %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x52,0xd9]
- vrsqrtss %xmm1, %xmm2, %xmm3
-
-// CHECK: vrsqrtss (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x52,0x18]
- vrsqrtss (%eax), %xmm2, %xmm3
-
-// CHECK: vrcpps %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x53,0xd1]
- vrcpps %xmm1, %xmm2
-
-// CHECK: vrcpps (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xf8,0x53,0x10]
- vrcpps (%eax), %xmm2
-
-// CHECK: vrcpss %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x53,0xd9]
- vrcpss %xmm1, %xmm2, %xmm3
-
-// CHECK: vrcpss (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xea,0x53,0x18]
- vrcpss (%eax), %xmm2, %xmm3
-
-// CHECK: vmovntdq %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0xe7,0x08]
- vmovntdq %xmm1, (%eax)
-
-// CHECK: vmovntpd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x2b,0x08]
- vmovntpd %xmm1, (%eax)
-
-// CHECK: vmovntps %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf8,0x2b,0x08]
- vmovntps %xmm1, (%eax)
-
-// CHECK: vldmxcsr (%eax)
-// CHECK: encoding: [0xc5,0xf8,0xae,0x10]
- vldmxcsr (%eax)
-
-// CHECK: vstmxcsr (%eax)
-// CHECK: encoding: [0xc5,0xf8,0xae,0x18]
- vstmxcsr (%eax)
-
-// CHECK: vldmxcsr 3735928559
-// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde]
- vldmxcsr 0xdeadbeef
-
-// CHECK: vstmxcsr 3735928559
-// CHECK: encoding: [0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde]
- vstmxcsr 0xdeadbeef
-
-// CHECK: vpsubb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf8,0xd9]
- vpsubb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf8,0x18]
- vpsubb (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf9,0xd9]
- vpsubw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf9,0x18]
- vpsubw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfa,0xd9]
- vpsubd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfa,0x18]
- vpsubd (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfb,0xd9]
- vpsubq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfb,0x18]
- vpsubq (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubsb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe8,0xd9]
- vpsubsb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubsb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe8,0x18]
- vpsubsb (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe9,0xd9]
- vpsubsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe9,0x18]
- vpsubsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubusb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd8,0xd9]
- vpsubusb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubusb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd8,0x18]
- vpsubusb (%eax), %xmm2, %xmm3
-
-// CHECK: vpsubusw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd9,0xd9]
- vpsubusw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsubusw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd9,0x18]
- vpsubusw (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfc,0xd9]
- vpaddb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfc,0x18]
- vpaddb (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfd,0xd9]
- vpaddw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfd,0x18]
- vpaddw (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfe,0xd9]
- vpaddd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xfe,0x18]
- vpaddd (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd4,0xd9]
- vpaddq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd4,0x18]
- vpaddq (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddsb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xec,0xd9]
- vpaddsb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddsb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xec,0x18]
- vpaddsb (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xed,0xd9]
- vpaddsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xed,0x18]
- vpaddsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddusb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdc,0xd9]
- vpaddusb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddusb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdc,0x18]
- vpaddusb (%eax), %xmm2, %xmm3
-
-// CHECK: vpaddusw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdd,0xd9]
- vpaddusw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpaddusw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdd,0x18]
- vpaddusw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmulhuw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe4,0xd9]
- vpmulhuw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmulhuw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe4,0x18]
- vpmulhuw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmulhw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe5,0xd9]
- vpmulhw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmulhw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe5,0x18]
- vpmulhw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmullw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd5,0xd9]
- vpmullw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmullw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd5,0x18]
- vpmullw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmuludq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf4,0xd9]
- vpmuludq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmuludq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf4,0x18]
- vpmuludq (%eax), %xmm2, %xmm3
-
-// CHECK: vpavgb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe0,0xd9]
- vpavgb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpavgb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe0,0x18]
- vpavgb (%eax), %xmm2, %xmm3
-
-// CHECK: vpavgw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe3,0xd9]
- vpavgw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpavgw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe3,0x18]
- vpavgw (%eax), %xmm2, %xmm3
-
-// CHECK: vpminsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xea,0xd9]
- vpminsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpminsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xea,0x18]
- vpminsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpminub %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xda,0xd9]
- vpminub %xmm1, %xmm2, %xmm3
-
-// CHECK: vpminub (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xda,0x18]
- vpminub (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xee,0xd9]
- vpmaxsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmaxsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xee,0x18]
- vpmaxsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxub %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xde,0xd9]
- vpmaxub %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmaxub (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xde,0x18]
- vpmaxub (%eax), %xmm2, %xmm3
-
-// CHECK: vpsadbw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf6,0xd9]
- vpsadbw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsadbw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf6,0x18]
- vpsadbw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsllw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf1,0xd9]
- vpsllw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsllw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf1,0x18]
- vpsllw (%eax), %xmm2, %xmm3
-
-// CHECK: vpslld %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf2,0xd9]
- vpslld %xmm1, %xmm2, %xmm3
-
-// CHECK: vpslld (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf2,0x18]
- vpslld (%eax), %xmm2, %xmm3
-
-// CHECK: vpsllq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf3,0xd9]
- vpsllq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsllq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xf3,0x18]
- vpsllq (%eax), %xmm2, %xmm3
-
-// CHECK: vpsraw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe1,0xd9]
- vpsraw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsraw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe1,0x18]
- vpsraw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsrad %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe2,0xd9]
- vpsrad %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsrad (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xe2,0x18]
- vpsrad (%eax), %xmm2, %xmm3
-
-// CHECK: vpsrlw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd1,0xd9]
- vpsrlw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsrlw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd1,0x18]
- vpsrlw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsrld %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd2,0xd9]
- vpsrld %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsrld (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd2,0x18]
- vpsrld (%eax), %xmm2, %xmm3
-
-// CHECK: vpsrlq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd3,0xd9]
- vpsrlq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsrlq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd3,0x18]
- vpsrlq (%eax), %xmm2, %xmm3
-
-// CHECK: vpslld $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
- vpslld $10, %xmm2, %xmm3
-
-// CHECK: vpslldq $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x73,0xfa,0x0a]
- vpslldq $10, %xmm2, %xmm3
-
-// CHECK: vpsllq $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x73,0xf2,0x0a]
- vpsllq $10, %xmm2, %xmm3
-
-// CHECK: vpsllw $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x71,0xf2,0x0a]
- vpsllw $10, %xmm2, %xmm3
-
-// CHECK: vpsrad $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x72,0xe2,0x0a]
- vpsrad $10, %xmm2, %xmm3
-
-// CHECK: vpsraw $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x71,0xe2,0x0a]
- vpsraw $10, %xmm2, %xmm3
-
-// CHECK: vpsrld $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x72,0xd2,0x0a]
- vpsrld $10, %xmm2, %xmm3
-
-// CHECK: vpsrldq $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x73,0xda,0x0a]
- vpsrldq $10, %xmm2, %xmm3
-
-// CHECK: vpsrlq $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x73,0xd2,0x0a]
- vpsrlq $10, %xmm2, %xmm3
-
-// CHECK: vpsrlw $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x71,0xd2,0x0a]
- vpsrlw $10, %xmm2, %xmm3
-
-// CHECK: vpslld $10, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
- vpslld $10, %xmm2, %xmm3
-
-// CHECK: vpand %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdb,0xd9]
- vpand %xmm1, %xmm2, %xmm3
-
-// CHECK: vpand (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdb,0x18]
- vpand (%eax), %xmm2, %xmm3
-
-// CHECK: vpor %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xeb,0xd9]
- vpor %xmm1, %xmm2, %xmm3
-
-// CHECK: vpor (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xeb,0x18]
- vpor (%eax), %xmm2, %xmm3
-
-// CHECK: vpxor %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xef,0xd9]
- vpxor %xmm1, %xmm2, %xmm3
-
-// CHECK: vpxor (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xef,0x18]
- vpxor (%eax), %xmm2, %xmm3
-
-// CHECK: vpandn %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdf,0xd9]
- vpandn %xmm1, %xmm2, %xmm3
-
-// CHECK: vpandn (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xdf,0x18]
- vpandn (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpeqb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x74,0xd9]
- vpcmpeqb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpeqb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x74,0x18]
- vpcmpeqb (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpeqw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x75,0xd9]
- vpcmpeqw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpeqw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x75,0x18]
- vpcmpeqw (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpeqd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x76,0xd9]
- vpcmpeqd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpeqd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x76,0x18]
- vpcmpeqd (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpgtb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x64,0xd9]
- vpcmpgtb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpgtb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x64,0x18]
- vpcmpgtb (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpgtw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x65,0xd9]
- vpcmpgtw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpgtw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x65,0x18]
- vpcmpgtw (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpgtd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x66,0xd9]
- vpcmpgtd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpcmpgtd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x66,0x18]
- vpcmpgtd (%eax), %xmm2, %xmm3
-
-// CHECK: vpacksswb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x63,0xd9]
- vpacksswb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpacksswb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x63,0x18]
- vpacksswb (%eax), %xmm2, %xmm3
-
-// CHECK: vpackssdw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6b,0xd9]
- vpackssdw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpackssdw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6b,0x18]
- vpackssdw (%eax), %xmm2, %xmm3
-
-// CHECK: vpackuswb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x67,0xd9]
- vpackuswb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpackuswb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x67,0x18]
- vpackuswb (%eax), %xmm2, %xmm3
-
-// CHECK: vpshufd $4, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xf9,0x70,0xda,0x04]
- vpshufd $4, %xmm2, %xmm3
-
-// CHECK: vpshufd $4, (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xf9,0x70,0x18,0x04]
- vpshufd $4, (%eax), %xmm3
-
-// CHECK: vpshufhw $4, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xfa,0x70,0xda,0x04]
- vpshufhw $4, %xmm2, %xmm3
-
-// CHECK: vpshufhw $4, (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xfa,0x70,0x18,0x04]
- vpshufhw $4, (%eax), %xmm3
-
-// CHECK: vpshuflw $4, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xfb,0x70,0xda,0x04]
- vpshuflw $4, %xmm2, %xmm3
-
-// CHECK: vpshuflw $4, (%eax), %xmm3
-// CHECK: encoding: [0xc5,0xfb,0x70,0x18,0x04]
- vpshuflw $4, (%eax), %xmm3
-
-// CHECK: vpunpcklbw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x60,0xd9]
- vpunpcklbw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpcklbw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x60,0x18]
- vpunpcklbw (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpcklwd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x61,0xd9]
- vpunpcklwd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpcklwd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x61,0x18]
- vpunpcklwd (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpckldq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x62,0xd9]
- vpunpckldq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpckldq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x62,0x18]
- vpunpckldq (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpcklqdq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6c,0xd9]
- vpunpcklqdq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpcklqdq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6c,0x18]
- vpunpcklqdq (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpckhbw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x68,0xd9]
- vpunpckhbw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpckhbw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x68,0x18]
- vpunpckhbw (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpckhwd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x69,0xd9]
- vpunpckhwd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpckhwd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x69,0x18]
- vpunpckhwd (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpckhdq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6a,0xd9]
- vpunpckhdq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpckhdq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6a,0x18]
- vpunpckhdq (%eax), %xmm2, %xmm3
-
-// CHECK: vpunpckhqdq %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6d,0xd9]
- vpunpckhqdq %xmm1, %xmm2, %xmm3
-
-// CHECK: vpunpckhqdq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x6d,0x18]
- vpunpckhqdq (%eax), %xmm2, %xmm3
-
-// CHECK: vpinsrw $7, %eax, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc4,0xd8,0x07]
- vpinsrw $7, %eax, %xmm2, %xmm3
-
-// CHECK: vpinsrw $7, (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xc4,0x18,0x07]
- vpinsrw $7, (%eax), %xmm2, %xmm3
-
-// CHECK: vpextrw $7, %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
- vpextrw $7, %xmm2, %eax
-
-// CHECK: vpmovmskb %xmm1, %eax
-// CHECK: encoding: [0xc5,0xf9,0xd7,0xc1]
- vpmovmskb %xmm1, %eax
-
-// CHECK: vmaskmovdqu %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf9,0xf7,0xd1]
- vmaskmovdqu %xmm1, %xmm2
-
-// CHECK: vmovd %xmm1, %eax
-// CHECK: encoding: [0xc5,0xf9,0x7e,0xc8]
- vmovd %xmm1, %eax
-
-// CHECK: vmovd %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0x7e,0x08]
- vmovd %xmm1, (%eax)
-
-// CHECK: vmovd %eax, %xmm1
-// CHECK: encoding: [0xc5,0xf9,0x6e,0xc8]
- vmovd %eax, %xmm1
-
-// CHECK: vmovd (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xf9,0x6e,0x08]
- vmovd (%eax), %xmm1
-
-// CHECK: vmovq %xmm1, (%eax)
-// CHECK: encoding: [0xc5,0xf9,0xd6,0x08]
- vmovq %xmm1, (%eax)
-
-// CHECK: vmovq %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfa,0x7e,0xd1]
- vmovq %xmm1, %xmm2
-
-// CHECK: vmovq (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xfa,0x7e,0x08]
- vmovq (%eax), %xmm1
-
-// CHECK: vcvtpd2dq %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfb,0xe6,0xd1]
- vcvtpd2dq %xmm1, %xmm2
-
-// CHECK: vcvtdq2pd %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfa,0xe6,0xd1]
- vcvtdq2pd %xmm1, %xmm2
-
-// CHECK: vcvtdq2pd (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xfa,0xe6,0x10]
- vcvtdq2pd (%eax), %xmm2
-
-// CHECK: vmovshdup %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfa,0x16,0xd1]
- vmovshdup %xmm1, %xmm2
-
-// CHECK: vmovshdup (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xfa,0x16,0x10]
- vmovshdup (%eax), %xmm2
-
-// CHECK: vmovsldup %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfa,0x12,0xd1]
- vmovsldup %xmm1, %xmm2
-
-// CHECK: vmovsldup (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xfa,0x12,0x10]
- vmovsldup (%eax), %xmm2
-
-// CHECK: vmovddup %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xfb,0x12,0xd1]
- vmovddup %xmm1, %xmm2
-
-// CHECK: vmovddup (%eax), %xmm2
-// CHECK: encoding: [0xc5,0xfb,0x12,0x10]
- vmovddup (%eax), %xmm2
-
-// CHECK: vaddsubps %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0xd0,0xd9]
- vaddsubps %xmm1, %xmm2, %xmm3
-
-// CHECK: vaddsubps (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf3,0xd0,0x10]
- vaddsubps (%eax), %xmm1, %xmm2
-
-// CHECK: vaddsubpd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0xd0,0xd9]
- vaddsubpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vaddsubpd (%eax), %xmm1, %xmm2
-// CHECK: encoding: [0xc5,0xf1,0xd0,0x10]
- vaddsubpd (%eax), %xmm1, %xmm2
-
-// CHECK: vhaddps %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x7c,0xd9]
- vhaddps %xmm1, %xmm2, %xmm3
-
-// CHECK: vhaddps (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x7c,0x18]
- vhaddps (%eax), %xmm2, %xmm3
-
-// CHECK: vhaddpd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x7c,0xd9]
- vhaddpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vhaddpd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x7c,0x18]
- vhaddpd (%eax), %xmm2, %xmm3
-
-// CHECK: vhsubps %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x7d,0xd9]
- vhsubps %xmm1, %xmm2, %xmm3
-
-// CHECK: vhsubps (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xeb,0x7d,0x18]
- vhsubps (%eax), %xmm2, %xmm3
-
-// CHECK: vhsubpd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x7d,0xd9]
- vhsubpd %xmm1, %xmm2, %xmm3
-
-// CHECK: vhsubpd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe9,0x7d,0x18]
- vhsubpd (%eax), %xmm2, %xmm3
-
-// CHECK: vpabsb %xmm1, %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0xd1]
- vpabsb %xmm1, %xmm2
-
-// CHECK: vpabsb (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0x10]
- vpabsb (%eax), %xmm2
-
-// CHECK: vpabsw %xmm1, %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0xd1]
- vpabsw %xmm1, %xmm2
-
-// CHECK: vpabsw (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0x10]
- vpabsw (%eax), %xmm2
-
-// CHECK: vpabsd %xmm1, %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0xd1]
- vpabsd %xmm1, %xmm2
-
-// CHECK: vpabsd (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0x10]
- vpabsd (%eax), %xmm2
-
-// CHECK: vphaddw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0xd9]
- vphaddw %xmm1, %xmm2, %xmm3
-
-// CHECK: vphaddw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0x18]
- vphaddw (%eax), %xmm2, %xmm3
-
-// CHECK: vphaddd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0xd9]
- vphaddd %xmm1, %xmm2, %xmm3
-
-// CHECK: vphaddd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0x18]
- vphaddd (%eax), %xmm2, %xmm3
-
-// CHECK: vphaddsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0xd9]
- vphaddsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vphaddsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0x18]
- vphaddsw (%eax), %xmm2, %xmm3
-
-// CHECK: vphsubw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0xd9]
- vphsubw %xmm1, %xmm2, %xmm3
-
-// CHECK: vphsubw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0x18]
- vphsubw (%eax), %xmm2, %xmm3
-
-// CHECK: vphsubd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0xd9]
- vphsubd %xmm1, %xmm2, %xmm3
-
-// CHECK: vphsubd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0x18]
- vphsubd (%eax), %xmm2, %xmm3
-
-// CHECK: vphsubsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0xd9]
- vphsubsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vphsubsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0x18]
- vphsubsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaddubsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0xd9]
- vpmaddubsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmaddubsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0x18]
- vpmaddubsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpshufb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0xd9]
- vpshufb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpshufb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0x18]
- vpshufb (%eax), %xmm2, %xmm3
-
-// CHECK: vpsignb %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0xd9]
- vpsignb %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsignb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0x18]
- vpsignb (%eax), %xmm2, %xmm3
-
-// CHECK: vpsignw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0xd9]
- vpsignw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsignw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0x18]
- vpsignw (%eax), %xmm2, %xmm3
-
-// CHECK: vpsignd %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0xd9]
- vpsignd %xmm1, %xmm2, %xmm3
-
-// CHECK: vpsignd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0x18]
- vpsignd (%eax), %xmm2, %xmm3
-
-// CHECK: vpmulhrsw %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0xd9]
- vpmulhrsw %xmm1, %xmm2, %xmm3
-
-// CHECK: vpmulhrsw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0x18]
- vpmulhrsw (%eax), %xmm2, %xmm3
-
-// CHECK: vpalignr $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0xd9,0x07]
- vpalignr $7, %xmm1, %xmm2, %xmm3
-
-// CHECK: vpalignr $7, (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
- vpalignr $7, (%eax), %xmm2, %xmm3
-
-// CHECK: vroundsd $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07]
- vroundsd $7, %xmm1, %xmm2, %xmm3
-
-// CHECK: vroundsd $7, (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07]
- vroundsd $7, (%eax), %xmm2, %xmm3
-
-// CHECK: vroundss $7, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07]
- vroundss $7, %xmm1, %xmm2, %xmm3
-
-// CHECK: vroundss $7, (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07]
- vroundss $7, (%eax), %xmm2, %xmm3
-
-// CHECK: vroundpd $7, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07]
- vroundpd $7, %xmm2, %xmm3
-
-// CHECK: vroundpd $7, (%eax), %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07]
- vroundpd $7, (%eax), %xmm3
-
-// CHECK: vroundps $7, %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07]
- vroundps $7, %xmm2, %xmm3
-
-// CHECK: vroundps $7, (%eax), %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
- vroundps $7, (%eax), %xmm3
-
-// CHECK: vphminposuw %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0xda]
- vphminposuw %xmm2, %xmm3
-
-// CHECK: vphminposuw (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0x10]
- vphminposuw (%eax), %xmm2
-
-// CHECK: vpackusdw %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x2b,0xca]
- vpackusdw %xmm2, %xmm3, %xmm1
-
-// CHECK: vpackusdw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x2b,0x18]
- vpackusdw (%eax), %xmm2, %xmm3
-
-// CHECK: vpcmpeqq %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x29,0xca]
- vpcmpeqq %xmm2, %xmm3, %xmm1
-
-// CHECK: vpcmpeqq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x29,0x18]
- vpcmpeqq (%eax), %xmm2, %xmm3
-
-// CHECK: vpminsb %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x38,0xca]
- vpminsb %xmm2, %xmm3, %xmm1
-
-// CHECK: vpminsb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x38,0x18]
- vpminsb (%eax), %xmm2, %xmm3
-
-// CHECK: vpminsd %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x39,0xca]
- vpminsd %xmm2, %xmm3, %xmm1
-
-// CHECK: vpminsd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x39,0x18]
- vpminsd (%eax), %xmm2, %xmm3
-
-// CHECK: vpminud %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3b,0xca]
- vpminud %xmm2, %xmm3, %xmm1
-
-// CHECK: vpminud (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3b,0x18]
- vpminud (%eax), %xmm2, %xmm3
-
-// CHECK: vpminuw %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3a,0xca]
- vpminuw %xmm2, %xmm3, %xmm1
-
-// CHECK: vpminuw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3a,0x18]
- vpminuw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxsb %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3c,0xca]
- vpmaxsb %xmm2, %xmm3, %xmm1
-
-// CHECK: vpmaxsb (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3c,0x18]
- vpmaxsb (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxsd %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3d,0xca]
- vpmaxsd %xmm2, %xmm3, %xmm1
-
-// CHECK: vpmaxsd (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3d,0x18]
- vpmaxsd (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxud %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3f,0xca]
- vpmaxud %xmm2, %xmm3, %xmm1
-
-// CHECK: vpmaxud (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3f,0x18]
- vpmaxud (%eax), %xmm2, %xmm3
-
-// CHECK: vpmaxuw %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x3e,0xca]
- vpmaxuw %xmm2, %xmm3, %xmm1
-
-// CHECK: vpmaxuw (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x3e,0x18]
- vpmaxuw (%eax), %xmm2, %xmm3
-
-// CHECK: vpmuldq %xmm2, %xmm3, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x61,0x28,0xca]
- vpmuldq %xmm2, %xmm3, %xmm1
-
-// CHECK: vpmuldq (%eax), %xmm2, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x69,0x28,0x18]
- vpmuldq (%eax), %xmm2, %xmm3
-
-// CHECK: vpmulld %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0xca]
- vpmulld %xmm2, %xmm5, %xmm1
-
-// CHECK: vpmulld (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0x18]
- vpmulld (%eax), %xmm5, %xmm3
-
-// CHECK: vblendps $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0xca,0x03]
- vblendps $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vblendps $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0x08,0x03]
- vblendps $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vblendpd $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0xca,0x03]
- vblendpd $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vblendpd $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0x08,0x03]
- vblendpd $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vpblendw $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0xca,0x03]
- vpblendw $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vpblendw $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0x08,0x03]
- vpblendw $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vmpsadbw $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0xca,0x03]
- vmpsadbw $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vmpsadbw $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0x08,0x03]
- vmpsadbw $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vdpps $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0xca,0x03]
- vdpps $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vdpps $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0x08,0x03]
- vdpps $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vdppd $3, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0xca,0x03]
- vdppd $3, %xmm2, %xmm5, %xmm1
-
-// CHECK: vdppd $3, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0x08,0x03]
- vdppd $3, (%eax), %xmm5, %xmm1
-
-// CHECK: vblendvpd %xmm2, %xmm5, %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4b,0xdd,0x20]
- vblendvpd %xmm2, %xmm5, %xmm1, %xmm3
-
-// CHECK: vblendvpd %xmm2, (%eax), %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4b,0x18,0x20]
- vblendvpd %xmm2, (%eax), %xmm1, %xmm3
-
-// CHECK: vblendvps %xmm2, %xmm5, %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4a,0xdd,0x20]
- vblendvps %xmm2, %xmm5, %xmm1, %xmm3
-
-// CHECK: vblendvps %xmm2, (%eax), %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4a,0x18,0x20]
- vblendvps %xmm2, (%eax), %xmm1, %xmm3
-
-// CHECK: vpblendvb %xmm2, %xmm5, %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4c,0xdd,0x20]
- vpblendvb %xmm2, %xmm5, %xmm1, %xmm3
-
-// CHECK: vpblendvb %xmm2, (%eax), %xmm1, %xmm3
-// CHECK: encoding: [0xc4,0xe3,0x71,0x4c,0x18,0x20]
- vpblendvb %xmm2, (%eax), %xmm1, %xmm3
-
-// CHECK: vpmovsxbw %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x20,0xea]
- vpmovsxbw %xmm2, %xmm5
-
-// CHECK: vpmovsxbw (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x20,0x10]
- vpmovsxbw (%eax), %xmm2
-
-// CHECK: vpmovsxwd %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x23,0xea]
- vpmovsxwd %xmm2, %xmm5
-
-// CHECK: vpmovsxwd (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x23,0x10]
- vpmovsxwd (%eax), %xmm2
-
-// CHECK: vpmovsxdq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x25,0xea]
- vpmovsxdq %xmm2, %xmm5
-
-// CHECK: vpmovsxdq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x25,0x10]
- vpmovsxdq (%eax), %xmm2
-
-// CHECK: vpmovzxbw %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x30,0xea]
- vpmovzxbw %xmm2, %xmm5
-
-// CHECK: vpmovzxbw (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x30,0x10]
- vpmovzxbw (%eax), %xmm2
-
-// CHECK: vpmovzxwd %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x33,0xea]
- vpmovzxwd %xmm2, %xmm5
-
-// CHECK: vpmovzxwd (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x33,0x10]
- vpmovzxwd (%eax), %xmm2
-
-// CHECK: vpmovzxdq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x35,0xea]
- vpmovzxdq %xmm2, %xmm5
-
-// CHECK: vpmovzxdq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x35,0x10]
- vpmovzxdq (%eax), %xmm2
-
-// CHECK: vpmovsxbq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x22,0xea]
- vpmovsxbq %xmm2, %xmm5
-
-// CHECK: vpmovsxbq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x22,0x10]
- vpmovsxbq (%eax), %xmm2
-
-// CHECK: vpmovzxbq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x32,0xea]
- vpmovzxbq %xmm2, %xmm5
-
-// CHECK: vpmovzxbq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x32,0x10]
- vpmovzxbq (%eax), %xmm2
-
-// CHECK: vpmovsxbd %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x21,0xea]
- vpmovsxbd %xmm2, %xmm5
-
-// CHECK: vpmovsxbd (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x21,0x10]
- vpmovsxbd (%eax), %xmm2
-
-// CHECK: vpmovsxwq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x24,0xea]
- vpmovsxwq %xmm2, %xmm5
-
-// CHECK: vpmovsxwq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x24,0x10]
- vpmovsxwq (%eax), %xmm2
-
-// CHECK: vpmovzxbd %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x31,0xea]
- vpmovzxbd %xmm2, %xmm5
-
-// CHECK: vpmovzxbd (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x31,0x10]
- vpmovzxbd (%eax), %xmm2
-
-// CHECK: vpmovzxwq %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x34,0xea]
- vpmovzxwq %xmm2, %xmm5
-
-// CHECK: vpmovzxwq (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x34,0x10]
- vpmovzxwq (%eax), %xmm2
-
-// CHECK: vpextrw $7, %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
- vpextrw $7, %xmm2, %eax
-
-// CHECK: vpextrw $7, %xmm2, (%eax)
-// CHECK: encoding: [0xc4,0xe3,0x79,0x15,0x10,0x07]
- vpextrw $7, %xmm2, (%eax)
-
-// CHECK: vpextrd $7, %xmm2, %eax
-// CHECK: encoding: [0xc4,0xe3,0x79,0x16,0xd0,0x07]
- vpextrd $7, %xmm2, %eax
-
-// CHECK: vpextrd $7, %xmm2, (%eax)
-// CHECK: encoding: [0xc4,0xe3,0x79,0x16,0x10,0x07]
- vpextrd $7, %xmm2, (%eax)
-
-// CHECK: vpextrb $7, %xmm2, %eax
-// CHECK: encoding: [0xc4,0xe3,0x79,0x14,0xd0,0x07]
- vpextrb $7, %xmm2, %eax
-
-// CHECK: vpextrb $7, %xmm2, (%eax)
-// CHECK: encoding: [0xc4,0xe3,0x79,0x14,0x10,0x07]
- vpextrb $7, %xmm2, (%eax)
-
-// CHECK: vextractps $7, %xmm2, (%eax)
-// CHECK: encoding: [0xc4,0xe3,0x79,0x17,0x10,0x07]
- vextractps $7, %xmm2, (%eax)
-
-// CHECK: vextractps $7, %xmm2, %eax
-// CHECK: encoding: [0xc4,0xe3,0x79,0x17,0xd0,0x07]
- vextractps $7, %xmm2, %eax
-
-// CHECK: vpinsrw $7, %eax, %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0xc4,0xe8,0x07]
- vpinsrw $7, %eax, %xmm2, %xmm5
-
-// CHECK: vpinsrw $7, (%eax), %xmm2, %xmm5
-// CHECK: encoding: [0xc5,0xe9,0xc4,0x28,0x07]
- vpinsrw $7, (%eax), %xmm2, %xmm5
-
-// CHECK: vpinsrb $7, %eax, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x69,0x20,0xe8,0x07]
- vpinsrb $7, %eax, %xmm2, %xmm5
-
-// CHECK: vpinsrb $7, (%eax), %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x69,0x20,0x28,0x07]
- vpinsrb $7, (%eax), %xmm2, %xmm5
-
-// CHECK: vpinsrd $7, %eax, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x69,0x22,0xe8,0x07]
- vpinsrd $7, %eax, %xmm2, %xmm5
-
-// CHECK: vpinsrd $7, (%eax), %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x69,0x22,0x28,0x07]
- vpinsrd $7, (%eax), %xmm2, %xmm5
-
-// CHECK: vinsertps $7, %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x21,0xca,0x07]
- vinsertps $7, %xmm2, %xmm5, %xmm1
-
-// CHECK: vinsertps $7, (%eax), %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe3,0x51,0x21,0x08,0x07]
- vinsertps $7, (%eax), %xmm5, %xmm1
-
-// CHECK: vptest %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0x17,0xea]
- vptest %xmm2, %xmm5
-
-// CHECK: vptest (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x17,0x10]
- vptest (%eax), %xmm2
-
-// CHECK: vmovntdqa (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0x2a,0x10]
- vmovntdqa (%eax), %xmm2
-
-// CHECK: vpcmpgtq %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0xca]
- vpcmpgtq %xmm2, %xmm5, %xmm1
-
-// CHECK: vpcmpgtq (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0x18]
- vpcmpgtq (%eax), %xmm5, %xmm3
-
-// CHECK: vpcmpistrm $7, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0xea,0x07]
- vpcmpistrm $7, %xmm2, %xmm5
-
-// CHECK: vpcmpistrm $7, (%eax), %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0x28,0x07]
- vpcmpistrm $7, (%eax), %xmm5
-
-// CHECK: vpcmpestrm $7, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0xea,0x07]
- vpcmpestrm $7, %xmm2, %xmm5
-
-// CHECK: vpcmpestrm $7, (%eax), %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0x28,0x07]
- vpcmpestrm $7, (%eax), %xmm5
-
-// CHECK: vpcmpistri $7, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0xea,0x07]
- vpcmpistri $7, %xmm2, %xmm5
-
-// CHECK: vpcmpistri $7, (%eax), %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0x28,0x07]
- vpcmpistri $7, (%eax), %xmm5
-
-// CHECK: vpcmpestri $7, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0xea,0x07]
- vpcmpestri $7, %xmm2, %xmm5
-
-// CHECK: vpcmpestri $7, (%eax), %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0x28,0x07]
- vpcmpestri $7, (%eax), %xmm5
-
-// CHECK: vaesimc %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe2,0x79,0xdb,0xea]
- vaesimc %xmm2, %xmm5
-
-// CHECK: vaesimc (%eax), %xmm2
-// CHECK: encoding: [0xc4,0xe2,0x79,0xdb,0x10]
- vaesimc (%eax), %xmm2
-
-// CHECK: vaesenc %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdc,0xca]
- vaesenc %xmm2, %xmm5, %xmm1
-
-// CHECK: vaesenc (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdc,0x18]
- vaesenc (%eax), %xmm5, %xmm3
-
-// CHECK: vaesenclast %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdd,0xca]
- vaesenclast %xmm2, %xmm5, %xmm1
-
-// CHECK: vaesenclast (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdd,0x18]
- vaesenclast (%eax), %xmm5, %xmm3
-
-// CHECK: vaesdec %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0xde,0xca]
- vaesdec %xmm2, %xmm5, %xmm1
-
-// CHECK: vaesdec (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0xde,0x18]
- vaesdec (%eax), %xmm5, %xmm3
-
-// CHECK: vaesdeclast %xmm2, %xmm5, %xmm1
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdf,0xca]
- vaesdeclast %xmm2, %xmm5, %xmm1
-
-// CHECK: vaesdeclast (%eax), %xmm5, %xmm3
-// CHECK: encoding: [0xc4,0xe2,0x51,0xdf,0x18]
- vaesdeclast (%eax), %xmm5, %xmm3
-
-// CHECK: vaeskeygenassist $7, %xmm2, %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0xdf,0xea,0x07]
- vaeskeygenassist $7, %xmm2, %xmm5
-
-// CHECK: vaeskeygenassist $7, (%eax), %xmm5
-// CHECK: encoding: [0xc4,0xe3,0x79,0xdf,0x28,0x07]
- vaeskeygenassist $7, (%eax), %xmm5
-
-// CHECK: vcmpps $8, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x08]
- vcmpeq_uqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $9, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x09]
- vcmpngeps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $10, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0a]
- vcmpngtps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $11, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0b]
- vcmpfalseps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $12, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0c]
- vcmpneq_oqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $13, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0d]
- vcmpgeps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $14, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0e]
- vcmpgtps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $15, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x0f]
- vcmptrueps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $16, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x10]
- vcmpeq_osps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $17, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x11]
- vcmplt_oqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $18, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x12]
- vcmple_oqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $19, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x13]
- vcmpunord_sps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $20, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x14]
- vcmpneq_usps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $21, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x15]
- vcmpnlt_uqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $22, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x16]
- vcmpnle_uqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $23, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x17]
- vcmpord_sps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $24, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x18]
- vcmpeq_usps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $25, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x19]
- vcmpnge_uqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $26, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1a]
- vcmpngt_uqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $27, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1b]
- vcmpfalse_osps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $28, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1c]
- vcmpneq_osps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $29, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1d]
- vcmpge_oqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $30, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1e]
- vcmpgt_oqps %xmm1, %xmm2, %xmm3
-
-// CHECK: vcmpps $31, %xmm1, %xmm2, %xmm3
-// CHECK: encoding: [0xc5,0xe8,0xc2,0xd9,0x1f]
- vcmptrue_usps %xmm1, %xmm2, %xmm3
-
-// CHECK: vmovaps (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x28,0x10]
- vmovaps (%eax), %ymm2
-
-// CHECK: vmovaps %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x28,0xd1]
- vmovaps %ymm1, %ymm2
-
-// CHECK: vmovaps %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfc,0x29,0x08]
- vmovaps %ymm1, (%eax)
-
-// CHECK: vmovapd (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x28,0x10]
- vmovapd (%eax), %ymm2
-
-// CHECK: vmovapd %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x28,0xd1]
- vmovapd %ymm1, %ymm2
-
-// CHECK: vmovapd %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfd,0x29,0x08]
- vmovapd %ymm1, (%eax)
-
-// CHECK: vmovups (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x10,0x10]
- vmovups (%eax), %ymm2
-
-// CHECK: vmovups %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x10,0xd1]
- vmovups %ymm1, %ymm2
-
-// CHECK: vmovups %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfc,0x11,0x08]
- vmovups %ymm1, (%eax)
-
-// CHECK: vmovupd (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x10,0x10]
- vmovupd (%eax), %ymm2
-
-// CHECK: vmovupd %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x10,0xd1]
- vmovupd %ymm1, %ymm2
-
-// CHECK: vmovupd %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfd,0x11,0x08]
- vmovupd %ymm1, (%eax)
-
-// CHECK: vunpckhps %ymm1, %ymm2, %ymm4
-// CHECK: encoding: [0xc5,0xec,0x15,0xe1]
- vunpckhps %ymm1, %ymm2, %ymm4
-
-// CHECK: vunpckhpd %ymm1, %ymm2, %ymm4
-// CHECK: encoding: [0xc5,0xed,0x15,0xe1]
- vunpckhpd %ymm1, %ymm2, %ymm4
-
-// CHECK: vunpcklps %ymm1, %ymm2, %ymm4
-// CHECK: encoding: [0xc5,0xec,0x14,0xe1]
- vunpcklps %ymm1, %ymm2, %ymm4
-
-// CHECK: vunpcklpd %ymm1, %ymm2, %ymm4
-// CHECK: encoding: [0xc5,0xed,0x14,0xe1]
- vunpcklpd %ymm1, %ymm2, %ymm4
-
-// CHECK: vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x15,0x6c,0xcb,0xfc]
- vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x15,0x6c,0xcb,0xfc]
- vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x14,0x6c,0xcb,0xfc]
- vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x14,0x6c,0xcb,0xfc]
- vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vmovntdq %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfd,0xe7,0x08]
- vmovntdq %ymm1, (%eax)
-
-// CHECK: vmovntpd %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfd,0x2b,0x08]
- vmovntpd %ymm1, (%eax)
-
-// CHECK: vmovntps %ymm1, (%eax)
-// CHECK: encoding: [0xc5,0xfc,0x2b,0x08]
- vmovntps %ymm1, (%eax)
-
-// CHECK: vmovmskps %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf8,0x50,0xc2]
- vmovmskps %xmm2, %eax
-
-// CHECK: vmovmskpd %xmm2, %eax
-// CHECK: encoding: [0xc5,0xf9,0x50,0xc2]
- vmovmskpd %xmm2, %eax
-
-// CHECK: vmaxps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5f,0xf2]
- vmaxps %ymm2, %ymm4, %ymm6
-
-// CHECK: vmaxpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5f,0xf2]
- vmaxpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vminps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5d,0xf2]
- vminps %ymm2, %ymm4, %ymm6
-
-// CHECK: vminpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5d,0xf2]
- vminpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vsubps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5c,0xf2]
- vsubps %ymm2, %ymm4, %ymm6
-
-// CHECK: vsubpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5c,0xf2]
- vsubpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vdivps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5e,0xf2]
- vdivps %ymm2, %ymm4, %ymm6
-
-// CHECK: vdivpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5e,0xf2]
- vdivpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vaddps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x58,0xf2]
- vaddps %ymm2, %ymm4, %ymm6
-
-// CHECK: vaddpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x58,0xf2]
- vaddpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vmulps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x59,0xf2]
- vmulps %ymm2, %ymm4, %ymm6
-
-// CHECK: vmulpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x59,0xf2]
- vmulpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vmaxps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5f,0x30]
- vmaxps (%eax), %ymm4, %ymm6
-
-// CHECK: vmaxpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5f,0x30]
- vmaxpd (%eax), %ymm4, %ymm6
-
-// CHECK: vminps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5d,0x30]
- vminps (%eax), %ymm4, %ymm6
-
-// CHECK: vminpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5d,0x30]
- vminpd (%eax), %ymm4, %ymm6
-
-// CHECK: vsubps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5c,0x30]
- vsubps (%eax), %ymm4, %ymm6
-
-// CHECK: vsubpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5c,0x30]
- vsubpd (%eax), %ymm4, %ymm6
-
-// CHECK: vdivps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5e,0x30]
- vdivps (%eax), %ymm4, %ymm6
-
-// CHECK: vdivpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5e,0x30]
- vdivpd (%eax), %ymm4, %ymm6
-
-// CHECK: vaddps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x58,0x30]
- vaddps (%eax), %ymm4, %ymm6
-
-// CHECK: vaddpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x58,0x30]
- vaddpd (%eax), %ymm4, %ymm6
-
-// CHECK: vmulps (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x59,0x30]
- vmulps (%eax), %ymm4, %ymm6
-
-// CHECK: vmulpd (%eax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x59,0x30]
- vmulpd (%eax), %ymm4, %ymm6
-
-// CHECK: vsqrtpd %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x51,0xd1]
- vsqrtpd %ymm1, %ymm2
-
-// CHECK: vsqrtpd (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfd,0x51,0x10]
- vsqrtpd (%eax), %ymm2
-
-// CHECK: vsqrtps %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x51,0xd1]
- vsqrtps %ymm1, %ymm2
-
-// CHECK: vsqrtps (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x51,0x10]
- vsqrtps (%eax), %ymm2
-
-// CHECK: vrsqrtps %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x52,0xd1]
- vrsqrtps %ymm1, %ymm2
-
-// CHECK: vrsqrtps (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x52,0x10]
- vrsqrtps (%eax), %ymm2
-
-// CHECK: vrcpps %ymm1, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x53,0xd1]
- vrcpps %ymm1, %ymm2
-
-// CHECK: vrcpps (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x53,0x10]
- vrcpps (%eax), %ymm2
-
-// CHECK: vandps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x54,0xf2]
- vandps %ymm2, %ymm4, %ymm6
-
-// CHECK: vandpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x54,0xf2]
- vandpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vandps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x54,0x6c,0xcb,0xfc]
- vandps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x54,0x6c,0xcb,0xfc]
- vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vorps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x56,0xf2]
- vorps %ymm2, %ymm4, %ymm6
-
-// CHECK: vorpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x56,0xf2]
- vorpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vorps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x56,0x6c,0xcb,0xfc]
- vorps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x56,0x6c,0xcb,0xfc]
- vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vxorps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x57,0xf2]
- vxorps %ymm2, %ymm4, %ymm6
-
-// CHECK: vxorpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x57,0xf2]
- vxorpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x57,0x6c,0xcb,0xfc]
- vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x57,0x6c,0xcb,0xfc]
- vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vandnps %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x55,0xf2]
- vandnps %ymm2, %ymm4, %ymm6
-
-// CHECK: vandnpd %ymm2, %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x55,0xf2]
- vandnpd %ymm2, %ymm4, %ymm6
-
-// CHECK: vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xec,0x55,0x6c,0xcb,0xfc]
- vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xed,0x55,0x6c,0xcb,0xfc]
- vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5
-
-// CHECK: vcvtps2pd %xmm3, %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x5a,0xd3]
- vcvtps2pd %xmm3, %ymm2
-
-// CHECK: vcvtps2pd (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x5a,0x10]
- vcvtps2pd (%eax), %ymm2
-
-// CHECK: vcvtdq2pd %xmm3, %ymm2
-// CHECK: encoding: [0xc5,0xfe,0xe6,0xd3]
- vcvtdq2pd %xmm3, %ymm2
-
-// CHECK: vcvtdq2pd (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfe,0xe6,0x10]
- vcvtdq2pd (%eax), %ymm2
-
-// CHECK: vcvtdq2ps %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xfc,0x5b,0xea]
- vcvtdq2ps %ymm2, %ymm5
-
-// CHECK: vcvtdq2ps (%eax), %ymm2
-// CHECK: encoding: [0xc5,0xfc,0x5b,0x10]
- vcvtdq2ps (%eax), %ymm2
-
-// CHECK: vcvtps2dq %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xfd,0x5b,0xea]
- vcvtps2dq %ymm2, %ymm5
-
-// CHECK: vcvtps2dq (%eax), %ymm5
-// CHECK: encoding: [0xc5,0xfd,0x5b,0x28]
- vcvtps2dq (%eax), %ymm5
-
-// CHECK: vcvttps2dq %ymm2, %ymm5
-// CHECK: encoding: [0xc5,0xfe,0x5b,0xea]
- vcvttps2dq %ymm2, %ymm5
-
-// CHECK: vcvttps2dq (%eax), %ymm5
-// CHECK: encoding: [0xc5,0xfe,0x5b,0x28]
- vcvttps2dq (%eax), %ymm5
-
-// CHECK: vcvttpd2dq %xmm1, %xmm5
-// CHECK: encoding: [0xc5,0xf9,0xe6,0xe9]
- vcvttpd2dq %xmm1, %xmm5
-
-// CHECK: vcvttpd2dq %ymm2, %xmm5
-// CHECK: encoding: [0xc5,0xfd,0xe6,0xea]
- vcvttpd2dq %ymm2, %xmm5
-
-// CHECK: vcvttpd2dqx %xmm1, %xmm5
-// CHECK: encoding: [0xc5,0xf9,0xe6,0xe9]
- vcvttpd2dqx %xmm1, %xmm5
-
-// CHECK: vcvttpd2dqx (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xf9,0xe6,0x08]
- vcvttpd2dqx (%eax), %xmm1
-
-// CHECK: vcvttpd2dqy %ymm2, %xmm1
-// CHECK: encoding: [0xc5,0xfd,0xe6,0xca]
- vcvttpd2dqy %ymm2, %xmm1
-
-// CHECK: vcvttpd2dqy (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xfd,0xe6,0x08]
- vcvttpd2dqy (%eax), %xmm1
-
-// CHECK: vcvtpd2ps %ymm2, %xmm5
-// CHECK: encoding: [0xc5,0xfd,0x5a,0xea]
- vcvtpd2ps %ymm2, %xmm5
-
-// CHECK: vcvtpd2psx %xmm1, %xmm5
-// CHECK: encoding: [0xc5,0xf9,0x5a,0xe9]
- vcvtpd2psx %xmm1, %xmm5
-
-// CHECK: vcvtpd2psx (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xf9,0x5a,0x08]
- vcvtpd2psx (%eax), %xmm1
-
-// CHECK: vcvtpd2psy %ymm2, %xmm1
-// CHECK: encoding: [0xc5,0xfd,0x5a,0xca]
- vcvtpd2psy %ymm2, %xmm1
-
-// CHECK: vcvtpd2psy (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xfd,0x5a,0x08]
- vcvtpd2psy (%eax), %xmm1
-
-// CHECK: vcvtpd2dq %ymm2, %xmm5
-// CHECK: encoding: [0xc5,0xff,0xe6,0xea]
- vcvtpd2dq %ymm2, %xmm5
-
-// CHECK: vcvtpd2dqy %ymm2, %xmm1
-// CHECK: encoding: [0xc5,0xff,0xe6,0xca]
- vcvtpd2dqy %ymm2, %xmm1
-
-// CHECK: vcvtpd2dqy (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xff,0xe6,0x08]
- vcvtpd2dqy (%eax), %xmm1
-
-// CHECK: vcvtpd2dqx %xmm1, %xmm5
-// CHECK: encoding: [0xc5,0xfb,0xe6,0xe9]
- vcvtpd2dqx %xmm1, %xmm5
-
-// CHECK: vcvtpd2dqx (%eax), %xmm1
-// CHECK: encoding: [0xc5,0xfb,0xe6,0x08]
- vcvtpd2dqx (%eax), %xmm1
-
-// CHECK: vcmpps $0, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x00]
- vcmpeqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $2, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x02]
- vcmpleps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $1, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x01]
- vcmpltps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $4, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x04]
- vcmpneqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $6, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x06]
- vcmpnleps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $5, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x05]
- vcmpnltps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $7, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x07]
- vcmpordps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $3, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x03]
- vcmpunordps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $0, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $2, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmpleps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $1, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $4, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $6, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnleps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $5, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $7, -4(%ebx,%ecx,8), %ymm6, %ymm2
-// CHECK: encoding: [0xc5,0xcc,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordps -4(%ebx,%ecx,8), %ymm6, %ymm2
-
-// CHECK: vcmpps $3, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordps -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $0, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x00]
- vcmpeqpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $2, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x02]
- vcmplepd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $1, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x01]
- vcmpltpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $4, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x04]
- vcmpneqpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $6, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x06]
- vcmpnlepd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $5, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x05]
- vcmpnltpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $7, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x07]
- vcmpordpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $3, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0xd9,0x03]
- vcmpunordpd %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmppd $0, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x00]
- vcmpeqpd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $2, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x02]
- vcmplepd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $1, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x01]
- vcmpltpd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $4, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x04]
- vcmpneqpd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $6, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x06]
- vcmpnlepd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $5, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x05]
- vcmpnltpd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmppd $7, -4(%ebx,%ecx,8), %ymm6, %ymm2
-// CHECK: encoding: [0xc5,0xcd,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordpd -4(%ebx,%ecx,8), %ymm6, %ymm2
-
-// CHECK: vcmppd $3, -4(%ebx,%ecx,8), %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xed,0xc2,0x5c,0xcb,0xfc,0x03]
- vcmpunordpd -4(%ebx,%ecx,8), %ymm2, %ymm3
-
-// CHECK: vcmpps $8, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x08]
- vcmpeq_uqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $9, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x09]
- vcmpngeps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $10, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0a]
- vcmpngtps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $11, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0b]
- vcmpfalseps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $12, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0c]
- vcmpneq_oqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $13, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0d]
- vcmpgeps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $14, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0e]
- vcmpgtps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $15, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x0f]
- vcmptrueps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $16, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x10]
- vcmpeq_osps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $17, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x11]
- vcmplt_oqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $18, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x12]
- vcmple_oqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $19, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x13]
- vcmpunord_sps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $20, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x14]
- vcmpneq_usps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $21, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x15]
- vcmpnlt_uqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $22, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x16]
- vcmpnle_uqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $23, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x17]
- vcmpord_sps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $24, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x18]
- vcmpeq_usps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $25, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x19]
- vcmpnge_uqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $26, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1a]
- vcmpngt_uqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $27, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1b]
- vcmpfalse_osps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $28, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1c]
- vcmpneq_osps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $29, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1d]
- vcmpge_oqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $30, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1e]
- vcmpgt_oqps %ymm1, %ymm2, %ymm3
-
-// CHECK: vcmpps $31, %ymm1, %ymm2, %ymm3
-// CHECK: encoding: [0xc5,0xec,0xc2,0xd9,0x1f]
- vcmptrue_usps %ymm1, %ymm2, %ymm3
+// CHECK: movl 57005(,%eiz), %ebx
+// CHECK: encoding: [0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
+ movl 57005(,%eiz), %ebx
+
+// CHECK: movl 48879(,%eiz), %eax
+// CHECK: encoding: [0x8b,0x04,0x25,0xef,0xbe,0x00,0x00]
+ movl 48879(,%eiz), %eax
+
+// CHECK: movl -4(,%eiz,8), %eax
+// CHECK: encoding: [0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff]
+ movl -4(,%eiz,8), %eax
+
+// CHECK: movl (%ecx,%eiz), %eax
+// CHECK: encoding: [0x8b,0x04,0x21]
+ movl (%ecx,%eiz), %eax
+
+// CHECK: movl (%ecx,%eiz,8), %eax
+// CHECK: encoding: [0x8b,0x04,0xe1]
+ movl (%ecx,%eiz,8), %eax
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-new-encoder.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_32-new-encoder.s Sat Jul 31 19:59:02 2010
@@ -415,3 +415,6 @@
// CHECK: encoding: [0x61]
popal
+// CHECK: jmpl *8(%eax)
+// CHECK: encoding: [0xff,0x60,0x08]
+ jmp *8(%eax)
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-encoding.s Sat Jul 31 19:59:02 2010
@@ -4,7 +4,7 @@
// CHECK: callw 42
// CHECK: encoding: [0x66,0xe8,A,A]
callw 42
-
+
// rdar://8127102
// CHECK: movq %gs:(%rdi), %rax
// CHECK: encoding: [0x65,0x48,0x8b,0x07]
@@ -114,2889 +114,29 @@
// CHECK: encoding: [0x0f,0x7e,0xca]
movd %mm1, %edx
-// CHECK: vaddss %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x32,0x58,0xd0]
-vaddss %xmm8, %xmm9, %xmm10
-
-// CHECK: vmulss %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x32,0x59,0xd0]
-vmulss %xmm8, %xmm9, %xmm10
-
-// CHECK: vsubss %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x32,0x5c,0xd0]
-vsubss %xmm8, %xmm9, %xmm10
-
-// CHECK: vdivss %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x32,0x5e,0xd0]
-vdivss %xmm8, %xmm9, %xmm10
-
-// CHECK: vaddsd %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x33,0x58,0xd0]
-vaddsd %xmm8, %xmm9, %xmm10
-
-// CHECK: vmulsd %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x33,0x59,0xd0]
-vmulsd %xmm8, %xmm9, %xmm10
-
-// CHECK: vsubsd %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x33,0x5c,0xd0]
-vsubsd %xmm8, %xmm9, %xmm10
-
-// CHECK: vdivsd %xmm8, %xmm9, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x33,0x5e,0xd0]
-vdivsd %xmm8, %xmm9, %xmm10
-
-// CHECK: vaddss -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2a,0x58,0x5c,0xd9,0xfc]
-vaddss -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vsubss -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2a,0x5c,0x5c,0xd9,0xfc]
-vsubss -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vmulss -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2a,0x59,0x5c,0xd9,0xfc]
-vmulss -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vdivss -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2a,0x5e,0x5c,0xd9,0xfc]
-vdivss -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vaddsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2b,0x58,0x5c,0xd9,0xfc]
-vaddsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vsubsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2b,0x5c,0x5c,0xd9,0xfc]
-vsubsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vmulsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2b,0x59,0x5c,0xd9,0xfc]
-vmulsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vdivsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x2b,0x5e,0x5c,0xd9,0xfc]
-vdivsd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vaddps %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x20,0x58,0xfa]
-vaddps %xmm10, %xmm11, %xmm15
-
-// CHECK: vsubps %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x20,0x5c,0xfa]
-vsubps %xmm10, %xmm11, %xmm15
-
-// CHECK: vmulps %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x20,0x59,0xfa]
-vmulps %xmm10, %xmm11, %xmm15
-
-// CHECK: vdivps %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x20,0x5e,0xfa]
-vdivps %xmm10, %xmm11, %xmm15
-
-// CHECK: vaddpd %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x21,0x58,0xfa]
-vaddpd %xmm10, %xmm11, %xmm15
-
-// CHECK: vsubpd %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x21,0x5c,0xfa]
-vsubpd %xmm10, %xmm11, %xmm15
-
-// CHECK: vmulpd %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x21,0x59,0xfa]
-vmulpd %xmm10, %xmm11, %xmm15
-
-// CHECK: vdivpd %xmm10, %xmm11, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x21,0x5e,0xfa]
-vdivpd %xmm10, %xmm11, %xmm15
-
-// CHECK: vaddps -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x28,0x58,0x5c,0xd9,0xfc]
-vaddps -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vsubps -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x28,0x5c,0x5c,0xd9,0xfc]
-vsubps -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vmulps -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x28,0x59,0x5c,0xd9,0xfc]
-vmulps -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vdivps -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x28,0x5e,0x5c,0xd9,0xfc]
-vdivps -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vaddpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x29,0x58,0x5c,0xd9,0xfc]
-vaddpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vsubpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x29,0x5c,0x5c,0xd9,0xfc]
-vsubpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vmulpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x29,0x59,0x5c,0xd9,0xfc]
-vmulpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-// CHECK: encoding: [0xc5,0x29,0x5e,0x5c,0xd9,0xfc]
-vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
-
-// CHECK: vmaxss %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x0a,0x5f,0xe2]
- vmaxss %xmm10, %xmm14, %xmm12
-
-// CHECK: vmaxsd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x0b,0x5f,0xe2]
- vmaxsd %xmm10, %xmm14, %xmm12
-
-// CHECK: vminss %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x0a,0x5d,0xe2]
- vminss %xmm10, %xmm14, %xmm12
-
-// CHECK: vminsd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x0b,0x5d,0xe2]
- vminsd %xmm10, %xmm14, %xmm12
-
-// CHECK: vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1a,0x5f,0x54,0xcb,0xfc]
- vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1b,0x5f,0x54,0xcb,0xfc]
- vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vminss -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1a,0x5d,0x54,0xcb,0xfc]
- vminss -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1b,0x5d,0x54,0xcb,0xfc]
- vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vmaxps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x5f,0xe2]
- vmaxps %xmm10, %xmm14, %xmm12
-
-// CHECK: vmaxpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x5f,0xe2]
- vmaxpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vminps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x5d,0xe2]
- vminps %xmm10, %xmm14, %xmm12
-
-// CHECK: vminpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x5d,0xe2]
- vminpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x5f,0x54,0xcb,0xfc]
- vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x5f,0x54,0xcb,0xfc]
- vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vminps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x5d,0x54,0xcb,0xfc]
- vminps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x5d,0x54,0xcb,0xfc]
- vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vandps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x54,0xe2]
- vandps %xmm10, %xmm14, %xmm12
-
-// CHECK: vandpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x54,0xe2]
- vandpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vandps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x54,0x54,0xcb,0xfc]
- vandps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x54,0x54,0xcb,0xfc]
- vandpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vorps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x56,0xe2]
- vorps %xmm10, %xmm14, %xmm12
-
-// CHECK: vorpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x56,0xe2]
- vorpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vorps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x56,0x54,0xcb,0xfc]
- vorps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x56,0x54,0xcb,0xfc]
- vorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vxorps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x57,0xe2]
- vxorps %xmm10, %xmm14, %xmm12
-
-// CHECK: vxorpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x57,0xe2]
- vxorpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x57,0x54,0xcb,0xfc]
- vxorps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x57,0x54,0xcb,0xfc]
- vxorpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vandnps %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x08,0x55,0xe2]
- vandnps %xmm10, %xmm14, %xmm12
-
-// CHECK: vandnpd %xmm10, %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x09,0x55,0xe2]
- vandnpd %xmm10, %xmm14, %xmm12
-
-// CHECK: vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x18,0x55,0x54,0xcb,0xfc]
- vandnps -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0x55,0x54,0xcb,0xfc]
- vandnpd -4(%rbx,%rcx,8), %xmm12, %xmm10
-
-// CHECK: vmovss -4(%rbx,%rcx,8), %xmm10
-// CHECK: encoding: [0xc5,0x7a,0x10,0x54,0xcb,0xfc]
- vmovss -4(%rbx,%rcx,8), %xmm10
-
-// CHECK: vmovss %xmm14, %xmm10, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x2a,0x10,0xfe]
- vmovss %xmm14, %xmm10, %xmm15
-
-// CHECK: vmovsd -4(%rbx,%rcx,8), %xmm10
-// CHECK: encoding: [0xc5,0x7b,0x10,0x54,0xcb,0xfc]
- vmovsd -4(%rbx,%rcx,8), %xmm10
-
-// CHECK: vmovsd %xmm14, %xmm10, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x2b,0x10,0xfe]
- vmovsd %xmm14, %xmm10, %xmm15
-
// rdar://7840289
// CHECK: pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A]
// CHECK: fixup A - offset: 5, value: CPI1_0-4
pshufb CPI1_0(%rip), %xmm1
-// CHECK: vunpckhps %xmm15, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0x15,0xef]
- vunpckhps %xmm15, %xmm12, %xmm13
-
-// CHECK: vunpckhpd %xmm15, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x15,0xef]
- vunpckhpd %xmm15, %xmm12, %xmm13
-
-// CHECK: vunpcklps %xmm15, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0x14,0xef]
- vunpcklps %xmm15, %xmm12, %xmm13
-
-// CHECK: vunpcklpd %xmm15, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x14,0xef]
- vunpcklpd %xmm15, %xmm12, %xmm13
-
-// CHECK: vunpckhps -4(%rbx,%rcx,8), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x18,0x15,0x7c,0xcb,0xfc]
- vunpckhps -4(%rbx,%rcx,8), %xmm12, %xmm15
-
-// CHECK: vunpckhpd -4(%rbx,%rcx,8), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x19,0x15,0x7c,0xcb,0xfc]
- vunpckhpd -4(%rbx,%rcx,8), %xmm12, %xmm15
-
-// CHECK: vunpcklps -4(%rbx,%rcx,8), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x18,0x14,0x7c,0xcb,0xfc]
- vunpcklps -4(%rbx,%rcx,8), %xmm12, %xmm15
-
-// CHECK: vunpcklpd -4(%rbx,%rcx,8), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x19,0x14,0x7c,0xcb,0xfc]
- vunpcklpd -4(%rbx,%rcx,8), %xmm12, %xmm15
-
-// CHECK: vcmpps $0, %xmm10, %xmm12, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xfa,0x00]
- vcmpps $0, %xmm10, %xmm12, %xmm15
-
-// CHECK: vcmpps $0, (%rax), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x18,0xc2,0x38,0x00]
- vcmpps $0, (%rax), %xmm12, %xmm15
-
-// CHECK: vcmpps $7, %xmm10, %xmm12, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xfa,0x07]
- vcmpps $7, %xmm10, %xmm12, %xmm15
-
-// CHECK: vcmppd $0, %xmm10, %xmm12, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xfa,0x00]
- vcmppd $0, %xmm10, %xmm12, %xmm15
-
-// CHECK: vcmppd $0, (%rax), %xmm12, %xmm15
-// CHECK: encoding: [0xc5,0x19,0xc2,0x38,0x00]
- vcmppd $0, (%rax), %xmm12, %xmm15
-
-// CHECK: vcmppd $7, %xmm10, %xmm12, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xfa,0x07]
- vcmppd $7, %xmm10, %xmm12, %xmm15
-
-// CHECK: vshufps $8, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc6,0xeb,0x08]
- vshufps $8, %xmm11, %xmm12, %xmm13
-
-// CHECK: vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc6,0x6c,0xcb,0xfc,0x08]
- vshufps $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vshufpd $8, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc6,0xeb,0x08]
- vshufpd $8, %xmm11, %xmm12, %xmm13
-
-// CHECK: vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc6,0x6c,0xcb,0xfc,0x08]
- vshufpd $8, -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $0, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x00]
- vcmpeqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $2, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x02]
- vcmpleps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $1, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x01]
- vcmpltps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $4, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x04]
- vcmpneqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $6, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x06]
- vcmpnleps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $5, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x05]
- vcmpnltps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x07]
- vcmpordps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $3, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x03]
- vcmpunordps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmpleps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnleps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpps $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc8,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordps -4(%rbx,%rcx,8), %xmm6, %xmm2
-
-// CHECK: vcmpps $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordps -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $0, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x00]
- vcmpeqpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $2, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x02]
- vcmplepd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $1, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x01]
- vcmpltpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $4, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x04]
- vcmpneqpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $6, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x06]
- vcmpnlepd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $5, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x05]
- vcmpnltpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x07]
- vcmpordpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $3, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xc2,0xeb,0x03]
- vcmpunordpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmppd $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqpd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmplepd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltpd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqpd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnlepd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltpd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmppd $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xc9,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordpd -4(%rbx,%rcx,8), %xmm6, %xmm2
-
-// CHECK: vcmppd $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordpd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $0, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x00]
- vcmpeqss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $2, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x02]
- vcmpless %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $1, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x01]
- vcmpltss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $4, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x04]
- vcmpneqss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $6, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x06]
- vcmpnless %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $5, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x05]
- vcmpnltss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x07]
- vcmpordss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $3, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1a,0xc2,0xeb,0x03]
- vcmpunordss %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpss $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqss -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmpless -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltss -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqss -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnless -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltss -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpss $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xca,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordss -4(%rbx,%rcx,8), %xmm6, %xmm2
-
-// CHECK: vcmpss $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1a,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordss -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $0, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x00]
- vcmpeqsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $2, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x02]
- vcmplesd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $1, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x01]
- vcmpltsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $4, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x04]
- vcmpneqsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $6, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x06]
- vcmpnlesd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $5, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x05]
- vcmpnltsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x07]
- vcmpordsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $3, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xc2,0xeb,0x03]
- vcmpunordsd %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpsd $0, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqsd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $2, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmplesd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $1, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltsd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $4, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqsd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $6, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnlesd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $5, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltsd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vcmpsd $7, -4(%rbx,%rcx,8), %xmm6, %xmm2
-// CHECK: encoding: [0xc5,0xcb,0xc2,0x54,0xcb,0xfc,0x07]
- vcmpordsd -4(%rbx,%rcx,8), %xmm6, %xmm2
-
-// CHECK: vcmpsd $3, -4(%rbx,%rcx,8), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordsd -4(%rbx,%rcx,8), %xmm12, %xmm13
-
-// CHECK: vucomiss %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x2e,0xe3]
- vucomiss %xmm11, %xmm12
-
-// CHECK: vucomiss (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x2e,0x20]
- vucomiss (%rax), %xmm12
-
-// CHECK: vcomiss %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x2f,0xe3]
- vcomiss %xmm11, %xmm12
-
-// CHECK: vcomiss (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x2f,0x20]
- vcomiss (%rax), %xmm12
-
-// CHECK: vucomisd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x79,0x2e,0xe3]
- vucomisd %xmm11, %xmm12
-
-// CHECK: vucomisd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x79,0x2e,0x20]
- vucomisd (%rax), %xmm12
-
-// CHECK: vcomisd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x79,0x2f,0xe3]
- vcomisd %xmm11, %xmm12
-
-// CHECK: vcomisd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x79,0x2f,0x20]
- vcomisd (%rax), %xmm12
-
-// CHECK: vcvttss2si (%rcx), %eax
-// CHECK: encoding: [0xc5,0xfa,0x2c,0x01]
- vcvttss2si (%rcx), %eax
-
-// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x22,0x2a,0x20]
- vcvtsi2ss (%rax), %xmm11, %xmm12
-
-// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x22,0x2a,0x20]
- vcvtsi2ss (%rax), %xmm11, %xmm12
-
-// CHECK: vcvttsd2si (%rcx), %eax
-// CHECK: encoding: [0xc5,0xfb,0x2c,0x01]
- vcvttsd2si (%rcx), %eax
-
-// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x23,0x2a,0x20]
- vcvtsi2sd (%rax), %xmm11, %xmm12
-
-// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x23,0x2a,0x20]
- vcvtsi2sd (%rax), %xmm11, %xmm12
-
-// CHECK: vmovaps (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x28,0x20]
- vmovaps (%rax), %xmm12
-
-// CHECK: vmovaps %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x28,0xe3]
- vmovaps %xmm11, %xmm12
-
-// CHECK: vmovaps %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x78,0x29,0x18]
- vmovaps %xmm11, (%rax)
-
-// CHECK: vmovapd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x79,0x28,0x20]
- vmovapd (%rax), %xmm12
-
-// CHECK: vmovapd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x79,0x28,0xe3]
- vmovapd %xmm11, %xmm12
-
-// CHECK: vmovapd %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x29,0x18]
- vmovapd %xmm11, (%rax)
-
-// CHECK: vmovups (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x10,0x20]
- vmovups (%rax), %xmm12
-
-// CHECK: vmovups %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x10,0xe3]
- vmovups %xmm11, %xmm12
-
-// CHECK: vmovups %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x78,0x11,0x18]
- vmovups %xmm11, (%rax)
-
-// CHECK: vmovupd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x79,0x10,0x20]
- vmovupd (%rax), %xmm12
-
-// CHECK: vmovupd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x79,0x10,0xe3]
- vmovupd %xmm11, %xmm12
-
-// CHECK: vmovupd %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x11,0x18]
- vmovupd %xmm11, (%rax)
-
-// CHECK: vmovlps %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x78,0x13,0x18]
- vmovlps %xmm11, (%rax)
-
-// CHECK: vmovlps (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0x12,0x28]
- vmovlps (%rax), %xmm12, %xmm13
-
-// CHECK: vmovlpd %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x13,0x18]
- vmovlpd %xmm11, (%rax)
-
-// CHECK: vmovlpd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x12,0x28]
- vmovlpd (%rax), %xmm12, %xmm13
-
-// CHECK: vmovhps %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x78,0x17,0x18]
- vmovhps %xmm11, (%rax)
-
-// CHECK: vmovhps (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x18,0x16,0x28]
- vmovhps (%rax), %xmm12, %xmm13
-
-// CHECK: vmovhpd %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x17,0x18]
- vmovhpd %xmm11, (%rax)
-
-// CHECK: vmovhpd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x16,0x28]
- vmovhpd (%rax), %xmm12, %xmm13
-
-// CHECK: vmovlhps %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0x16,0xeb]
- vmovlhps %xmm11, %xmm12, %xmm13
-
-// CHECK: vmovhlps %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0x12,0xeb]
- vmovhlps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcvtss2sil %xmm11, %eax
-// CHECK: encoding: [0xc4,0xc1,0x7a,0x2d,0xc3]
- vcvtss2si %xmm11, %eax
-
-// CHECK: vcvtss2sil (%rax), %ebx
-// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
- vcvtss2si (%rax), %ebx
-
-// CHECK: vcvtdq2ps %xmm10, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xe2]
- vcvtdq2ps %xmm10, %xmm12
-
-// CHECK: vcvtdq2ps (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x5b,0x20]
- vcvtdq2ps (%rax), %xmm12
-
-// CHECK: vcvtsd2ss %xmm12, %xmm13, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x13,0x5a,0xd4]
- vcvtsd2ss %xmm12, %xmm13, %xmm10
-
-// CHECK: vcvtsd2ss (%rax), %xmm13, %xmm10
-// CHECK: encoding: [0xc5,0x13,0x5a,0x10]
- vcvtsd2ss (%rax), %xmm13, %xmm10
-
-// CHECK: vcvtps2dq %xmm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x79,0x5b,0xdc]
- vcvtps2dq %xmm12, %xmm11
-
-// CHECK: vcvtps2dq (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x79,0x5b,0x18]
- vcvtps2dq (%rax), %xmm11
-
-// CHECK: vcvtss2sd %xmm12, %xmm13, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x12,0x5a,0xd4]
- vcvtss2sd %xmm12, %xmm13, %xmm10
-
-// CHECK: vcvtss2sd (%rax), %xmm13, %xmm10
-// CHECK: encoding: [0xc5,0x12,0x5a,0x10]
- vcvtss2sd (%rax), %xmm13, %xmm10
-
-// CHECK: vcvtdq2ps %xmm13, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xd5]
- vcvtdq2ps %xmm13, %xmm10
-
-// CHECK: vcvtdq2ps (%ecx), %xmm13
-// CHECK: encoding: [0xc5,0x78,0x5b,0x29]
- vcvtdq2ps (%ecx), %xmm13
-
-// CHECK: vcvttps2dq %xmm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x7a,0x5b,0xdc]
- vcvttps2dq %xmm12, %xmm11
-
-// CHECK: vcvttps2dq (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x7a,0x5b,0x18]
- vcvttps2dq (%rax), %xmm11
-
-// CHECK: vcvtps2pd %xmm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x78,0x5a,0xdc]
- vcvtps2pd %xmm12, %xmm11
-
-// CHECK: vcvtps2pd (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x78,0x5a,0x18]
- vcvtps2pd (%rax), %xmm11
-
-// CHECK: vcvtpd2ps %xmm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc]
- vcvtpd2ps %xmm12, %xmm11
-
-// CHECK: vsqrtpd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x79,0x51,0xe3]
- vsqrtpd %xmm11, %xmm12
-
-// CHECK: vsqrtpd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x79,0x51,0x20]
- vsqrtpd (%rax), %xmm12
-
-// CHECK: vsqrtps %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x51,0xe3]
- vsqrtps %xmm11, %xmm12
-
-// CHECK: vsqrtps (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x51,0x20]
- vsqrtps (%rax), %xmm12
-
-// CHECK: vsqrtsd %xmm11, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x1b,0x51,0xd3]
- vsqrtsd %xmm11, %xmm12, %xmm10
-
-// CHECK: vsqrtsd (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1b,0x51,0x10]
- vsqrtsd (%rax), %xmm12, %xmm10
-
-// CHECK: vsqrtss %xmm11, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x1a,0x51,0xd3]
- vsqrtss %xmm11, %xmm12, %xmm10
-
-// CHECK: vsqrtss (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1a,0x51,0x10]
- vsqrtss (%rax), %xmm12, %xmm10
-
-// CHECK: vrsqrtps %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x52,0xe3]
- vrsqrtps %xmm11, %xmm12
-
-// CHECK: vrsqrtps (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x52,0x20]
- vrsqrtps (%rax), %xmm12
-
-// CHECK: vrsqrtss %xmm11, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x1a,0x52,0xd3]
- vrsqrtss %xmm11, %xmm12, %xmm10
-
-// CHECK: vrsqrtss (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1a,0x52,0x10]
- vrsqrtss (%rax), %xmm12, %xmm10
-
-// CHECK: vrcpps %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x78,0x53,0xe3]
- vrcpps %xmm11, %xmm12
-
-// CHECK: vrcpps (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x78,0x53,0x20]
- vrcpps (%rax), %xmm12
-
-// CHECK: vrcpss %xmm11, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x1a,0x53,0xd3]
- vrcpss %xmm11, %xmm12, %xmm10
-
-// CHECK: vrcpss (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x1a,0x53,0x10]
- vrcpss (%rax), %xmm12, %xmm10
-
-// CHECK: vmovntdq %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0xe7,0x18]
- vmovntdq %xmm11, (%rax)
-
-// CHECK: vmovntpd %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x2b,0x18]
- vmovntpd %xmm11, (%rax)
-
-// CHECK: vmovntps %xmm11, (%rax)
-// CHECK: encoding: [0xc5,0x78,0x2b,0x18]
- vmovntps %xmm11, (%rax)
-
-// CHECK: vldmxcsr -4(%rip)
-// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff]
- vldmxcsr -4(%rip)
-
-// CHECK: vstmxcsr -4(%rsp)
-// CHECK: encoding: [0xc5,0xf8,0xae,0x5c,0x24,0xfc]
- vstmxcsr -4(%rsp)
-
-// CHECK: vpsubb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf8,0xeb]
- vpsubb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf8,0x28]
- vpsubb (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf9,0xeb]
- vpsubw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf9,0x28]
- vpsubw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xfa,0xeb]
- vpsubd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xfa,0x28]
- vpsubd (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xfb,0xeb]
- vpsubq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xfb,0x28]
- vpsubq (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubsb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe8,0xeb]
- vpsubsb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubsb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe8,0x28]
- vpsubsb (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe9,0xeb]
- vpsubsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe9,0x28]
- vpsubsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubusb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd8,0xeb]
- vpsubusb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubusb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd8,0x28]
- vpsubusb (%rax), %xmm12, %xmm13
-
-// CHECK: vpsubusw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd9,0xeb]
- vpsubusw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsubusw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd9,0x28]
- vpsubusw (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xfc,0xeb]
- vpaddb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xfc,0x28]
- vpaddb (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xfd,0xeb]
- vpaddw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xfd,0x28]
- vpaddw (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xfe,0xeb]
- vpaddd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xfe,0x28]
- vpaddd (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd4,0xeb]
- vpaddq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd4,0x28]
- vpaddq (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddsb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xec,0xeb]
- vpaddsb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddsb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xec,0x28]
- vpaddsb (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xed,0xeb]
- vpaddsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xed,0x28]
- vpaddsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddusb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xdc,0xeb]
- vpaddusb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddusb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xdc,0x28]
- vpaddusb (%rax), %xmm12, %xmm13
-
-// CHECK: vpaddusw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xdd,0xeb]
- vpaddusw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpaddusw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xdd,0x28]
- vpaddusw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmulhuw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe4,0xeb]
- vpmulhuw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmulhuw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe4,0x28]
- vpmulhuw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmulhw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe5,0xeb]
- vpmulhw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmulhw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe5,0x28]
- vpmulhw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmullw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd5,0xeb]
- vpmullw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmullw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd5,0x28]
- vpmullw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmuludq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf4,0xeb]
- vpmuludq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmuludq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf4,0x28]
- vpmuludq (%rax), %xmm12, %xmm13
-
-// CHECK: vpavgb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe0,0xeb]
- vpavgb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpavgb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe0,0x28]
- vpavgb (%rax), %xmm12, %xmm13
-
-// CHECK: vpavgw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe3,0xeb]
- vpavgw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpavgw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe3,0x28]
- vpavgw (%rax), %xmm12, %xmm13
-
-// CHECK: vpminsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xea,0xeb]
- vpminsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpminsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xea,0x28]
- vpminsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpminub %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xda,0xeb]
- vpminub %xmm11, %xmm12, %xmm13
-
-// CHECK: vpminub (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xda,0x28]
- vpminub (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xee,0xeb]
- vpmaxsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmaxsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xee,0x28]
- vpmaxsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxub %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xde,0xeb]
- vpmaxub %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmaxub (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xde,0x28]
- vpmaxub (%rax), %xmm12, %xmm13
-
-// CHECK: vpsadbw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf6,0xeb]
- vpsadbw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsadbw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf6,0x28]
- vpsadbw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsllw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf1,0xeb]
- vpsllw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsllw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf1,0x28]
- vpsllw (%rax), %xmm12, %xmm13
-
-// CHECK: vpslld %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf2,0xeb]
- vpslld %xmm11, %xmm12, %xmm13
-
-// CHECK: vpslld (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf2,0x28]
- vpslld (%rax), %xmm12, %xmm13
-
-// CHECK: vpsllq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xf3,0xeb]
- vpsllq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsllq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xf3,0x28]
- vpsllq (%rax), %xmm12, %xmm13
-
-// CHECK: vpsraw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe1,0xeb]
- vpsraw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsraw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe1,0x28]
- vpsraw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsrad %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xe2,0xeb]
- vpsrad %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsrad (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xe2,0x28]
- vpsrad (%rax), %xmm12, %xmm13
-
-// CHECK: vpsrlw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd1,0xeb]
- vpsrlw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsrlw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd1,0x28]
- vpsrlw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsrld %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd2,0xeb]
- vpsrld %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsrld (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd2,0x28]
- vpsrld (%rax), %xmm12, %xmm13
-
-// CHECK: vpsrlq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd3,0xeb]
- vpsrlq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsrlq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xd3,0x28]
- vpsrlq (%rax), %xmm12, %xmm13
-
-// CHECK: vpslld $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
- vpslld $10, %xmm12, %xmm13
-
-// CHECK: vpslldq $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xfc,0x0a]
- vpslldq $10, %xmm12, %xmm13
-
-// CHECK: vpsllq $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xf4,0x0a]
- vpsllq $10, %xmm12, %xmm13
-
-// CHECK: vpsllw $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xf4,0x0a]
- vpsllw $10, %xmm12, %xmm13
-
-// CHECK: vpsrad $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xe4,0x0a]
- vpsrad $10, %xmm12, %xmm13
-
-// CHECK: vpsraw $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xe4,0x0a]
- vpsraw $10, %xmm12, %xmm13
-
-// CHECK: vpsrld $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xd4,0x0a]
- vpsrld $10, %xmm12, %xmm13
-
-// CHECK: vpsrldq $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xdc,0x0a]
- vpsrldq $10, %xmm12, %xmm13
-
-// CHECK: vpsrlq $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xd4,0x0a]
- vpsrlq $10, %xmm12, %xmm13
-
-// CHECK: vpsrlw $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xd4,0x0a]
- vpsrlw $10, %xmm12, %xmm13
-
-// CHECK: vpslld $10, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
- vpslld $10, %xmm12, %xmm13
-
-// CHECK: vpand %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xdb,0xeb]
- vpand %xmm11, %xmm12, %xmm13
-
-// CHECK: vpand (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xdb,0x28]
- vpand (%rax), %xmm12, %xmm13
-
-// CHECK: vpor %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xeb,0xeb]
- vpor %xmm11, %xmm12, %xmm13
-
-// CHECK: vpor (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xeb,0x28]
- vpor (%rax), %xmm12, %xmm13
-
-// CHECK: vpxor %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xef,0xeb]
- vpxor %xmm11, %xmm12, %xmm13
-
-// CHECK: vpxor (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xef,0x28]
- vpxor (%rax), %xmm12, %xmm13
-
-// CHECK: vpandn %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xdf,0xeb]
- vpandn %xmm11, %xmm12, %xmm13
-
-// CHECK: vpandn (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xdf,0x28]
- vpandn (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpeqb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x74,0xeb]
- vpcmpeqb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpeqb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x74,0x28]
- vpcmpeqb (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpeqw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x75,0xeb]
- vpcmpeqw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpeqw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x75,0x28]
- vpcmpeqw (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpeqd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x76,0xeb]
- vpcmpeqd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpeqd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x76,0x28]
- vpcmpeqd (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpgtb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x64,0xeb]
- vpcmpgtb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpgtb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x64,0x28]
- vpcmpgtb (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpgtw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x65,0xeb]
- vpcmpgtw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpgtw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x65,0x28]
- vpcmpgtw (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpgtd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x66,0xeb]
- vpcmpgtd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpcmpgtd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x66,0x28]
- vpcmpgtd (%rax), %xmm12, %xmm13
-
-// CHECK: vpacksswb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x63,0xeb]
- vpacksswb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpacksswb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x63,0x28]
- vpacksswb (%rax), %xmm12, %xmm13
-
-// CHECK: vpackssdw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x6b,0xeb]
- vpackssdw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpackssdw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x6b,0x28]
- vpackssdw (%rax), %xmm12, %xmm13
-
-// CHECK: vpackuswb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x67,0xeb]
- vpackuswb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpackuswb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x67,0x28]
- vpackuswb (%rax), %xmm12, %xmm13
-
-// CHECK: vpshufd $4, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x79,0x70,0xec,0x04]
- vpshufd $4, %xmm12, %xmm13
-
-// CHECK: vpshufd $4, (%rax), %xmm13
-// CHECK: encoding: [0xc5,0x79,0x70,0x28,0x04]
- vpshufd $4, (%rax), %xmm13
-
-// CHECK: vpshufhw $4, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x7a,0x70,0xec,0x04]
- vpshufhw $4, %xmm12, %xmm13
-
-// CHECK: vpshufhw $4, (%rax), %xmm13
-// CHECK: encoding: [0xc5,0x7a,0x70,0x28,0x04]
- vpshufhw $4, (%rax), %xmm13
-
-// CHECK: vpshuflw $4, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x7b,0x70,0xec,0x04]
- vpshuflw $4, %xmm12, %xmm13
-
-// CHECK: vpshuflw $4, (%rax), %xmm13
-// CHECK: encoding: [0xc5,0x7b,0x70,0x28,0x04]
- vpshuflw $4, (%rax), %xmm13
-
-// CHECK: vpunpcklbw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x60,0xeb]
- vpunpcklbw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpcklbw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x60,0x28]
- vpunpcklbw (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpcklwd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x61,0xeb]
- vpunpcklwd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpcklwd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x61,0x28]
- vpunpcklwd (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpckldq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x62,0xeb]
- vpunpckldq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpckldq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x62,0x28]
- vpunpckldq (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpcklqdq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x6c,0xeb]
- vpunpcklqdq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpcklqdq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x6c,0x28]
- vpunpcklqdq (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpckhbw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x68,0xeb]
- vpunpckhbw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpckhbw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x68,0x28]
- vpunpckhbw (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpckhwd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x69,0xeb]
- vpunpckhwd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpckhwd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x69,0x28]
- vpunpckhwd (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpckhdq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x6a,0xeb]
- vpunpckhdq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpckhdq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x6a,0x28]
- vpunpckhdq (%rax), %xmm12, %xmm13
-
-// CHECK: vpunpckhqdq %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x6d,0xeb]
- vpunpckhqdq %xmm11, %xmm12, %xmm13
-
-// CHECK: vpunpckhqdq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x6d,0x28]
- vpunpckhqdq (%rax), %xmm12, %xmm13
-
-// CHECK: vpinsrw $7, %eax, %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc4,0xe8,0x07]
- vpinsrw $7, %eax, %xmm12, %xmm13
-
-// CHECK: vpinsrw $7, (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0xc4,0x28,0x07]
- vpinsrw $7, (%rax), %xmm12, %xmm13
-
-// CHECK: vpextrw $7, %xmm12, %eax
-// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
- vpextrw $7, %xmm12, %eax
-
-// CHECK: vpmovmskb %xmm12, %eax
-// CHECK: encoding: [0xc4,0xc1,0x79,0xd7,0xc4]
- vpmovmskb %xmm12, %eax
-
-// CHECK: vmaskmovdqu %xmm14, %xmm15
-// CHECK: encoding: [0xc4,0x41,0x79,0xf7,0xfe]
- vmaskmovdqu %xmm14, %xmm15
-
-// CHECK: vmovd %eax, %xmm14
-// CHECK: encoding: [0xc5,0x79,0x6e,0xf0]
- vmovd %eax, %xmm14
-
-// CHECK: vmovd (%rax), %xmm14
-// CHECK: encoding: [0xc5,0x79,0x6e,0x30]
- vmovd (%rax), %xmm14
-
-// CHECK: vmovd %xmm14, (%rax)
-// CHECK: encoding: [0xc5,0x79,0x7e,0x30]
- vmovd %xmm14, (%rax)
-
-// CHECK: vmovd %rax, %xmm14
-// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
- vmovd %rax, %xmm14
-
-// CHECK: vmovq %xmm14, (%rax)
-// CHECK: encoding: [0xc5,0x79,0xd6,0x30]
- vmovq %xmm14, (%rax)
-
-// CHECK: vmovq %xmm14, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7a,0x7e,0xe6]
- vmovq %xmm14, %xmm12
-
-// CHECK: vmovq (%rax), %xmm14
-// CHECK: encoding: [0xc5,0x7a,0x7e,0x30]
- vmovq (%rax), %xmm14
-
-// CHECK: vmovq %rax, %xmm14
-// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
- vmovq %rax, %xmm14
-
-// CHECK: vmovq %xmm14, %rax
-// CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0]
- vmovq %xmm14, %rax
-
-// CHECK: vcvtpd2dq %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xe3]
- vcvtpd2dq %xmm11, %xmm12
-
-// CHECK: vcvtdq2pd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7a,0xe6,0xe3]
- vcvtdq2pd %xmm11, %xmm12
-
-// CHECK: vcvtdq2pd (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x7a,0xe6,0x20]
- vcvtdq2pd (%rax), %xmm12
-
-// CHECK: vmovshdup %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7a,0x16,0xe3]
- vmovshdup %xmm11, %xmm12
-
-// CHECK: vmovshdup (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x7a,0x16,0x20]
- vmovshdup (%rax), %xmm12
-
-// CHECK: vmovsldup %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7a,0x12,0xe3]
- vmovsldup %xmm11, %xmm12
-
-// CHECK: vmovsldup (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x7a,0x12,0x20]
- vmovsldup (%rax), %xmm12
-
-// CHECK: vmovddup %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x41,0x7b,0x12,0xe3]
- vmovddup %xmm11, %xmm12
-
-// CHECK: vmovddup (%rax), %xmm12
-// CHECK: encoding: [0xc5,0x7b,0x12,0x20]
- vmovddup (%rax), %xmm12
-
-// CHECK: vaddsubps %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0xd0,0xeb]
- vaddsubps %xmm11, %xmm12, %xmm13
-
-// CHECK: vaddsubps (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x23,0xd0,0x20]
- vaddsubps (%rax), %xmm11, %xmm12
-
-// CHECK: vaddsubpd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0xd0,0xeb]
- vaddsubpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vaddsubpd (%rax), %xmm11, %xmm12
-// CHECK: encoding: [0xc5,0x21,0xd0,0x20]
- vaddsubpd (%rax), %xmm11, %xmm12
-
-// CHECK: vhaddps %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0x7c,0xeb]
- vhaddps %xmm11, %xmm12, %xmm13
-
-// CHECK: vhaddps (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0x7c,0x28]
- vhaddps (%rax), %xmm12, %xmm13
-
-// CHECK: vhaddpd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x7c,0xeb]
- vhaddpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vhaddpd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x7c,0x28]
- vhaddpd (%rax), %xmm12, %xmm13
-
-// CHECK: vhsubps %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x1b,0x7d,0xeb]
- vhsubps %xmm11, %xmm12, %xmm13
-
-// CHECK: vhsubps (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x1b,0x7d,0x28]
- vhsubps (%rax), %xmm12, %xmm13
-
-// CHECK: vhsubpd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x19,0x7d,0xeb]
- vhsubpd %xmm11, %xmm12, %xmm13
-
-// CHECK: vhsubpd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc5,0x19,0x7d,0x28]
- vhsubpd (%rax), %xmm12, %xmm13
-
-// CHECK: vpabsb %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x42,0x79,0x1c,0xe3]
- vpabsb %xmm11, %xmm12
-
-// CHECK: vpabsb (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x1c,0x20]
- vpabsb (%rax), %xmm12
-
-// CHECK: vpabsw %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x42,0x79,0x1d,0xe3]
- vpabsw %xmm11, %xmm12
-
-// CHECK: vpabsw (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x1d,0x20]
- vpabsw (%rax), %xmm12
-
-// CHECK: vpabsd %xmm11, %xmm12
-// CHECK: encoding: [0xc4,0x42,0x79,0x1e,0xe3]
- vpabsd %xmm11, %xmm12
-
-// CHECK: vpabsd (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x1e,0x20]
- vpabsd (%rax), %xmm12
-
-// CHECK: vphaddw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x01,0xeb]
- vphaddw %xmm11, %xmm12, %xmm13
-
-// CHECK: vphaddw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x01,0x28]
- vphaddw (%rax), %xmm12, %xmm13
-
-// CHECK: vphaddd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x02,0xeb]
- vphaddd %xmm11, %xmm12, %xmm13
-
-// CHECK: vphaddd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x02,0x28]
- vphaddd (%rax), %xmm12, %xmm13
-
-// CHECK: vphaddsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x03,0xeb]
- vphaddsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vphaddsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x03,0x28]
- vphaddsw (%rax), %xmm12, %xmm13
-
-// CHECK: vphsubw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x05,0xeb]
- vphsubw %xmm11, %xmm12, %xmm13
-
-// CHECK: vphsubw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x05,0x28]
- vphsubw (%rax), %xmm12, %xmm13
-
-// CHECK: vphsubd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x06,0xeb]
- vphsubd %xmm11, %xmm12, %xmm13
-
-// CHECK: vphsubd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x06,0x28]
- vphsubd (%rax), %xmm12, %xmm13
-
-// CHECK: vphsubsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x07,0xeb]
- vphsubsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vphsubsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x07,0x28]
- vphsubsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaddubsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x04,0xeb]
- vpmaddubsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmaddubsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x04,0x28]
- vpmaddubsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpshufb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x00,0xeb]
- vpshufb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpshufb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x00,0x28]
- vpshufb (%rax), %xmm12, %xmm13
-
-// CHECK: vpsignb %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x08,0xeb]
- vpsignb %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsignb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x08,0x28]
- vpsignb (%rax), %xmm12, %xmm13
-
-// CHECK: vpsignw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x09,0xeb]
- vpsignw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsignw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x09,0x28]
- vpsignw (%rax), %xmm12, %xmm13
-
-// CHECK: vpsignd %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x0a,0xeb]
- vpsignd %xmm11, %xmm12, %xmm13
-
-// CHECK: vpsignd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x0a,0x28]
- vpsignd (%rax), %xmm12, %xmm13
-
-// CHECK: vpmulhrsw %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x19,0x0b,0xeb]
- vpmulhrsw %xmm11, %xmm12, %xmm13
-
-// CHECK: vpmulhrsw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x0b,0x28]
- vpmulhrsw (%rax), %xmm12, %xmm13
-
-// CHECK: vpalignr $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x43,0x19,0x0f,0xeb,0x07]
- vpalignr $7, %xmm11, %xmm12, %xmm13
-
-// CHECK: vpalignr $7, (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
- vpalignr $7, (%rax), %xmm12, %xmm13
-
-// CHECK: vroundsd $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07]
- vroundsd $7, %xmm11, %xmm12, %xmm13
-
-// CHECK: vroundsd $7, (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07]
- vroundsd $7, (%rax), %xmm12, %xmm13
-
-// CHECK: vroundss $7, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07]
- vroundss $7, %xmm11, %xmm12, %xmm13
-
-// CHECK: vroundss $7, (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07]
- vroundss $7, (%rax), %xmm12, %xmm13
-
-// CHECK: vroundpd $7, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07]
- vroundpd $7, %xmm12, %xmm13
-
-// CHECK: vroundpd $7, (%rax), %xmm13
-// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07]
- vroundpd $7, (%rax), %xmm13
-
-// CHECK: vroundps $7, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07]
- vroundps $7, %xmm12, %xmm13
-
-// CHECK: vroundps $7, (%rax), %xmm13
-// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
- vroundps $7, (%rax), %xmm13
-
-// CHECK: vphminposuw %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x42,0x79,0x41,0xec]
- vphminposuw %xmm12, %xmm13
-
-// CHECK: vphminposuw (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x41,0x20]
- vphminposuw (%rax), %xmm12
-
-// CHECK: vpackusdw %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x2b,0xdc]
- vpackusdw %xmm12, %xmm13, %xmm11
-
-// CHECK: vpackusdw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x2b,0x28]
- vpackusdw (%rax), %xmm12, %xmm13
-
-// CHECK: vpcmpeqq %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x29,0xdc]
- vpcmpeqq %xmm12, %xmm13, %xmm11
-
-// CHECK: vpcmpeqq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x29,0x28]
- vpcmpeqq (%rax), %xmm12, %xmm13
-
-// CHECK: vpminsb %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x38,0xdc]
- vpminsb %xmm12, %xmm13, %xmm11
-
-// CHECK: vpminsb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x38,0x28]
- vpminsb (%rax), %xmm12, %xmm13
-
-// CHECK: vpminsd %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x39,0xdc]
- vpminsd %xmm12, %xmm13, %xmm11
-
-// CHECK: vpminsd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x39,0x28]
- vpminsd (%rax), %xmm12, %xmm13
-
-// CHECK: vpminud %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3b,0xdc]
- vpminud %xmm12, %xmm13, %xmm11
-
-// CHECK: vpminud (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3b,0x28]
- vpminud (%rax), %xmm12, %xmm13
-
-// CHECK: vpminuw %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3a,0xdc]
- vpminuw %xmm12, %xmm13, %xmm11
-
-// CHECK: vpminuw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3a,0x28]
- vpminuw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxsb %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3c,0xdc]
- vpmaxsb %xmm12, %xmm13, %xmm11
-
-// CHECK: vpmaxsb (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3c,0x28]
- vpmaxsb (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxsd %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3d,0xdc]
- vpmaxsd %xmm12, %xmm13, %xmm11
-
-// CHECK: vpmaxsd (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3d,0x28]
- vpmaxsd (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxud %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3f,0xdc]
- vpmaxud %xmm12, %xmm13, %xmm11
-
-// CHECK: vpmaxud (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3f,0x28]
- vpmaxud (%rax), %xmm12, %xmm13
-
-// CHECK: vpmaxuw %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x3e,0xdc]
- vpmaxuw %xmm12, %xmm13, %xmm11
-
-// CHECK: vpmaxuw (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x3e,0x28]
- vpmaxuw (%rax), %xmm12, %xmm13
-
-// CHECK: vpmuldq %xmm12, %xmm13, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x11,0x28,0xdc]
- vpmuldq %xmm12, %xmm13, %xmm11
-
-// CHECK: vpmuldq (%rax), %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x19,0x28,0x28]
- vpmuldq (%rax), %xmm12, %xmm13
-
-// CHECK: vpmulld %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x51,0x40,0xdc]
- vpmulld %xmm12, %xmm5, %xmm11
-
-// CHECK: vpmulld (%rax), %xmm5, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x51,0x40,0x28]
- vpmulld (%rax), %xmm5, %xmm13
-
-// CHECK: vblendps $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x0c,0xdc,0x03]
- vblendps $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vblendps $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x0c,0x18,0x03]
- vblendps $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vblendpd $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x0d,0xdc,0x03]
- vblendpd $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vblendpd $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x0d,0x18,0x03]
- vblendpd $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vpblendw $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x0e,0xdc,0x03]
- vpblendw $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vpblendw $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x0e,0x18,0x03]
- vpblendw $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vmpsadbw $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x42,0xdc,0x03]
- vmpsadbw $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vmpsadbw $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x42,0x18,0x03]
- vmpsadbw $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vdpps $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x40,0xdc,0x03]
- vdpps $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vdpps $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x40,0x18,0x03]
- vdpps $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vdppd $3, %xmm12, %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x51,0x41,0xdc,0x03]
- vdppd $3, %xmm12, %xmm5, %xmm11
-
-// CHECK: vdppd $3, (%rax), %xmm5, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x51,0x41,0x18,0x03]
- vdppd $3, (%rax), %xmm5, %xmm11
-
-// CHECK: vblendvpd %xmm12, %xmm5, %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4b,0xed,0xc0]
- vblendvpd %xmm12, %xmm5, %xmm11, %xmm13
-
-// CHECK: vblendvpd %xmm12, (%rax), %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4b,0x28,0xc0]
- vblendvpd %xmm12, (%rax), %xmm11, %xmm13
-
-// CHECK: vblendvps %xmm12, %xmm5, %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4a,0xed,0xc0]
- vblendvps %xmm12, %xmm5, %xmm11, %xmm13
-
-// CHECK: vblendvps %xmm12, (%rax), %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4a,0x28,0xc0]
- vblendvps %xmm12, (%rax), %xmm11, %xmm13
-
-// CHECK: vpblendvb %xmm12, %xmm5, %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4c,0xed,0xc0]
- vpblendvb %xmm12, %xmm5, %xmm11, %xmm13
-
-// CHECK: vpblendvb %xmm12, (%rax), %xmm11, %xmm13
-// CHECK: encoding: [0xc4,0x63,0x21,0x4c,0x28,0xc0]
- vpblendvb %xmm12, (%rax), %xmm11, %xmm13
-
-// CHECK: vpmovsxbw %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x20,0xd4]
- vpmovsxbw %xmm12, %xmm10
-
-// CHECK: vpmovsxbw (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x20,0x20]
- vpmovsxbw (%rax), %xmm12
-
-// CHECK: vpmovsxwd %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x23,0xd4]
- vpmovsxwd %xmm12, %xmm10
-
-// CHECK: vpmovsxwd (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x23,0x20]
- vpmovsxwd (%rax), %xmm12
-
-// CHECK: vpmovsxdq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x25,0xd4]
- vpmovsxdq %xmm12, %xmm10
-
-// CHECK: vpmovsxdq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x25,0x20]
- vpmovsxdq (%rax), %xmm12
-
-// CHECK: vpmovzxbw %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x30,0xd4]
- vpmovzxbw %xmm12, %xmm10
-
-// CHECK: vpmovzxbw (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x30,0x20]
- vpmovzxbw (%rax), %xmm12
-
-// CHECK: vpmovzxwd %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x33,0xd4]
- vpmovzxwd %xmm12, %xmm10
-
-// CHECK: vpmovzxwd (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x33,0x20]
- vpmovzxwd (%rax), %xmm12
-
-// CHECK: vpmovzxdq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x35,0xd4]
- vpmovzxdq %xmm12, %xmm10
-
-// CHECK: vpmovzxdq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x35,0x20]
- vpmovzxdq (%rax), %xmm12
-
-// CHECK: vpmovsxbq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x22,0xd4]
- vpmovsxbq %xmm12, %xmm10
-
-// CHECK: vpmovsxbq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x22,0x20]
- vpmovsxbq (%rax), %xmm12
-
-// CHECK: vpmovzxbq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x32,0xd4]
- vpmovzxbq %xmm12, %xmm10
-
-// CHECK: vpmovzxbq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x32,0x20]
- vpmovzxbq (%rax), %xmm12
-
-// CHECK: vpmovsxbd %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x21,0xd4]
- vpmovsxbd %xmm12, %xmm10
-
-// CHECK: vpmovsxbd (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x21,0x20]
- vpmovsxbd (%rax), %xmm12
-
-// CHECK: vpmovsxwq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x24,0xd4]
- vpmovsxwq %xmm12, %xmm10
-
-// CHECK: vpmovsxwq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x24,0x20]
- vpmovsxwq (%rax), %xmm12
-
-// CHECK: vpmovzxbd %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x31,0xd4]
- vpmovzxbd %xmm12, %xmm10
-
-// CHECK: vpmovzxbd (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x31,0x20]
- vpmovzxbd (%rax), %xmm12
-
-// CHECK: vpmovzxwq %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x34,0xd4]
- vpmovzxwq %xmm12, %xmm10
-
-// CHECK: vpmovzxwq (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x34,0x20]
- vpmovzxwq (%rax), %xmm12
-
-// CHECK: vpextrw $7, %xmm12, %eax
-// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
- vpextrw $7, %xmm12, %eax
-
-// CHECK: vpextrw $7, %xmm12, (%rax)
-// CHECK: encoding: [0xc4,0x63,0x79,0x15,0x20,0x07]
- vpextrw $7, %xmm12, (%rax)
-
-// CHECK: vpextrd $7, %xmm12, %eax
-// CHECK: encoding: [0xc4,0x63,0x79,0x16,0xe0,0x07]
- vpextrd $7, %xmm12, %eax
-
-// CHECK: vpextrd $7, %xmm12, (%rax)
-// CHECK: encoding: [0xc4,0x63,0x79,0x16,0x20,0x07]
- vpextrd $7, %xmm12, (%rax)
-
-// CHECK: vpextrb $7, %xmm12, %eax
-// CHECK: encoding: [0xc4,0x63,0x79,0x14,0xe0,0x07]
- vpextrb $7, %xmm12, %eax
-
-// CHECK: vpextrb $7, %xmm12, (%rax)
-// CHECK: encoding: [0xc4,0x63,0x79,0x14,0x20,0x07]
- vpextrb $7, %xmm12, (%rax)
-
-// CHECK: vpextrq $7, %xmm12, %rcx
-// CHECK: encoding: [0xc4,0x63,0xf9,0x16,0xe1,0x07]
- vpextrq $7, %xmm12, %rcx
-
-// CHECK: vpextrq $7, %xmm12, (%rcx)
-// CHECK: encoding: [0xc4,0x63,0xf9,0x16,0x21,0x07]
- vpextrq $7, %xmm12, (%rcx)
-
-// CHECK: vextractps $7, %xmm12, (%rax)
-// CHECK: encoding: [0xc4,0x63,0x79,0x17,0x20,0x07]
- vextractps $7, %xmm12, (%rax)
-
-// CHECK: vextractps $7, %xmm12, %eax
-// CHECK: encoding: [0xc4,0x63,0x79,0x17,0xe0,0x07]
- vextractps $7, %xmm12, %eax
-
-// CHECK: vpinsrw $7, %eax, %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0xc4,0xd0,0x07]
- vpinsrw $7, %eax, %xmm12, %xmm10
-
-// CHECK: vpinsrw $7, (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc5,0x19,0xc4,0x10,0x07]
- vpinsrw $7, (%rax), %xmm12, %xmm10
-
-// CHECK: vpinsrb $7, %eax, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x19,0x20,0xd0,0x07]
- vpinsrb $7, %eax, %xmm12, %xmm10
-
-// CHECK: vpinsrb $7, (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x19,0x20,0x10,0x07]
- vpinsrb $7, (%rax), %xmm12, %xmm10
-
-// CHECK: vpinsrd $7, %eax, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x19,0x22,0xd0,0x07]
- vpinsrd $7, %eax, %xmm12, %xmm10
-
-// CHECK: vpinsrd $7, (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x19,0x22,0x10,0x07]
- vpinsrd $7, (%rax), %xmm12, %xmm10
-
-// CHECK: vpinsrq $7, %rax, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x99,0x22,0xd0,0x07]
- vpinsrq $7, %rax, %xmm12, %xmm10
-
-// CHECK: vpinsrq $7, (%rax), %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x63,0x99,0x22,0x10,0x07]
- vpinsrq $7, (%rax), %xmm12, %xmm10
-
-// CHECK: vinsertps $7, %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x43,0x29,0x21,0xdc,0x07]
- vinsertps $7, %xmm12, %xmm10, %xmm11
-
-// CHECK: vinsertps $7, (%rax), %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x63,0x29,0x21,0x18,0x07]
- vinsertps $7, (%rax), %xmm10, %xmm11
-
-// CHECK: vptest %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0x17,0xd4]
- vptest %xmm12, %xmm10
-
-// CHECK: vptest (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x17,0x20]
- vptest (%rax), %xmm12
-
-// CHECK: vmovntdqa (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0x2a,0x20]
- vmovntdqa (%rax), %xmm12
-
-// CHECK: vpcmpgtq %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x29,0x37,0xdc]
- vpcmpgtq %xmm12, %xmm10, %xmm11
-
-// CHECK: vpcmpgtq (%rax), %xmm10, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x29,0x37,0x28]
- vpcmpgtq (%rax), %xmm10, %xmm13
-
-// CHECK: vpcmpistrm $7, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x43,0x79,0x62,0xd4,0x07]
- vpcmpistrm $7, %xmm12, %xmm10
-
-// CHECK: vpcmpistrm $7, (%rax), %xmm10
-// CHECK: encoding: [0xc4,0x63,0x79,0x62,0x10,0x07]
- vpcmpistrm $7, (%rax), %xmm10
-
-// CHECK: vpcmpestrm $7, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x43,0x79,0x60,0xd4,0x07]
- vpcmpestrm $7, %xmm12, %xmm10
-
-// CHECK: vpcmpestrm $7, (%rax), %xmm10
-// CHECK: encoding: [0xc4,0x63,0x79,0x60,0x10,0x07]
- vpcmpestrm $7, (%rax), %xmm10
-
-// CHECK: vpcmpistri $7, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x43,0x79,0x63,0xd4,0x07]
- vpcmpistri $7, %xmm12, %xmm10
-
-// CHECK: vpcmpistri $7, (%rax), %xmm10
-// CHECK: encoding: [0xc4,0x63,0x79,0x63,0x10,0x07]
- vpcmpistri $7, (%rax), %xmm10
-
-// CHECK: vpcmpestri $7, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x43,0x79,0x61,0xd4,0x07]
- vpcmpestri $7, %xmm12, %xmm10
-
-// CHECK: vpcmpestri $7, (%rax), %xmm10
-// CHECK: encoding: [0xc4,0x63,0x79,0x61,0x10,0x07]
- vpcmpestri $7, (%rax), %xmm10
-
-// CHECK: vaesimc %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x42,0x79,0xdb,0xd4]
- vaesimc %xmm12, %xmm10
-
-// CHECK: vaesimc (%rax), %xmm12
-// CHECK: encoding: [0xc4,0x62,0x79,0xdb,0x20]
- vaesimc (%rax), %xmm12
-
-// CHECK: vaesenc %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x29,0xdc,0xdc]
- vaesenc %xmm12, %xmm10, %xmm11
-
-// CHECK: vaesenc (%rax), %xmm10, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x29,0xdc,0x28]
- vaesenc (%rax), %xmm10, %xmm13
-
-// CHECK: vaesenclast %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x29,0xdd,0xdc]
- vaesenclast %xmm12, %xmm10, %xmm11
-
-// CHECK: vaesenclast (%rax), %xmm10, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x29,0xdd,0x28]
- vaesenclast (%rax), %xmm10, %xmm13
-
-// CHECK: vaesdec %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x29,0xde,0xdc]
- vaesdec %xmm12, %xmm10, %xmm11
-
-// CHECK: vaesdec (%rax), %xmm10, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x29,0xde,0x28]
- vaesdec (%rax), %xmm10, %xmm13
-
-// CHECK: vaesdeclast %xmm12, %xmm10, %xmm11
-// CHECK: encoding: [0xc4,0x42,0x29,0xdf,0xdc]
- vaesdeclast %xmm12, %xmm10, %xmm11
-
-// CHECK: vaesdeclast (%rax), %xmm10, %xmm13
-// CHECK: encoding: [0xc4,0x62,0x29,0xdf,0x28]
- vaesdeclast (%rax), %xmm10, %xmm13
-
-// CHECK: vaeskeygenassist $7, %xmm12, %xmm10
-// CHECK: encoding: [0xc4,0x43,0x79,0xdf,0xd4,0x07]
- vaeskeygenassist $7, %xmm12, %xmm10
-
-// CHECK: vaeskeygenassist $7, (%rax), %xmm10
-// CHECK: encoding: [0xc4,0x63,0x79,0xdf,0x10,0x07]
- vaeskeygenassist $7, (%rax), %xmm10
-
-// CHECK: vcmpps $8, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x08]
- vcmpeq_uqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $9, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x09]
- vcmpngeps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $10, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0a]
- vcmpngtps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $11, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0b]
- vcmpfalseps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $12, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0c]
- vcmpneq_oqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $13, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0d]
- vcmpgeps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $14, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0e]
- vcmpgtps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $15, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x0f]
- vcmptrueps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $16, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x10]
- vcmpeq_osps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $17, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x11]
- vcmplt_oqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $18, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x12]
- vcmple_oqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $19, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x13]
- vcmpunord_sps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $20, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x14]
- vcmpneq_usps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $21, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x15]
- vcmpnlt_uqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $22, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x16]
- vcmpnle_uqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $23, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x17]
- vcmpord_sps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $24, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x18]
- vcmpeq_usps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $25, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x19]
- vcmpnge_uqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $26, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1a]
- vcmpngt_uqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $27, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1b]
- vcmpfalse_osps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $28, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1c]
- vcmpneq_osps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $29, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1d]
- vcmpge_oqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $30, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1e]
- vcmpgt_oqps %xmm11, %xmm12, %xmm13
-
-// CHECK: vcmpps $31, %xmm11, %xmm12, %xmm13
-// CHECK: encoding: [0xc4,0x41,0x18,0xc2,0xeb,0x1f]
- vcmptrue_usps %xmm11, %xmm12, %xmm13
-
-// CHECK: vmovaps (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x28,0x20]
- vmovaps (%rax), %ymm12
-
-// CHECK: vmovaps %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x28,0xe3]
- vmovaps %ymm11, %ymm12
-
-// CHECK: vmovaps %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7c,0x29,0x18]
- vmovaps %ymm11, (%rax)
-
-// CHECK: vmovapd (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7d,0x28,0x20]
- vmovapd (%rax), %ymm12
-
-// CHECK: vmovapd %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7d,0x28,0xe3]
- vmovapd %ymm11, %ymm12
-
-// CHECK: vmovapd %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7d,0x29,0x18]
- vmovapd %ymm11, (%rax)
-
-// CHECK: vmovups (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x10,0x20]
- vmovups (%rax), %ymm12
-
-// CHECK: vmovups %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x10,0xe3]
- vmovups %ymm11, %ymm12
-
-// CHECK: vmovups %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7c,0x11,0x18]
- vmovups %ymm11, (%rax)
-
-// CHECK: vmovupd (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7d,0x10,0x20]
- vmovupd (%rax), %ymm12
-
-// CHECK: vmovupd %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7d,0x10,0xe3]
- vmovupd %ymm11, %ymm12
-
-// CHECK: vmovupd %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7d,0x11,0x18]
- vmovupd %ymm11, (%rax)
-
-// CHECK: vunpckhps %ymm11, %ymm12, %ymm4
-// CHECK: encoding: [0xc4,0xc1,0x1c,0x15,0xe3]
- vunpckhps %ymm11, %ymm12, %ymm4
-
-// CHECK: vunpckhpd %ymm11, %ymm12, %ymm4
-// CHECK: encoding: [0xc4,0xc1,0x1d,0x15,0xe3]
- vunpckhpd %ymm11, %ymm12, %ymm4
-
-// CHECK: vunpcklps %ymm11, %ymm12, %ymm4
-// CHECK: encoding: [0xc4,0xc1,0x1c,0x14,0xe3]
- vunpcklps %ymm11, %ymm12, %ymm4
-
-// CHECK: vunpcklpd %ymm11, %ymm12, %ymm4
-// CHECK: encoding: [0xc4,0xc1,0x1d,0x14,0xe3]
- vunpcklpd %ymm11, %ymm12, %ymm4
-
-// CHECK: vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x15,0x54,0xcb,0xfc]
- vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x15,0x54,0xcb,0xfc]
- vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x14,0x54,0xcb,0xfc]
- vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x14,0x54,0xcb,0xfc]
- vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vmovntdq %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7d,0xe7,0x18]
- vmovntdq %ymm11, (%rax)
-
-// CHECK: vmovntpd %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7d,0x2b,0x18]
- vmovntpd %ymm11, (%rax)
-
-// CHECK: vmovntps %ymm11, (%rax)
-// CHECK: encoding: [0xc5,0x7c,0x2b,0x18]
- vmovntps %ymm11, (%rax)
-
-// CHECK: vmovmskps %xmm12, %eax
-// CHECK: encoding: [0xc4,0xc1,0x78,0x50,0xc4]
- vmovmskps %xmm12, %eax
-
-// CHECK: vmovmskpd %xmm12, %eax
-// CHECK: encoding: [0xc4,0xc1,0x79,0x50,0xc4]
- vmovmskpd %xmm12, %eax
-
-// CHECK: vmaxps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x5f,0xf4]
- vmaxps %ymm12, %ymm4, %ymm6
-
-// CHECK: vmaxpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x5f,0xf4]
- vmaxpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vminps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x5d,0xf4]
- vminps %ymm12, %ymm4, %ymm6
-
-// CHECK: vminpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x5d,0xf4]
- vminpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vsubps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x5c,0xf4]
- vsubps %ymm12, %ymm4, %ymm6
-
-// CHECK: vsubpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x5c,0xf4]
- vsubpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vdivps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x5e,0xf4]
- vdivps %ymm12, %ymm4, %ymm6
-
-// CHECK: vdivpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x5e,0xf4]
- vdivpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vaddps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x58,0xf4]
- vaddps %ymm12, %ymm4, %ymm6
-
-// CHECK: vaddpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x58,0xf4]
- vaddpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vmulps %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5c,0x59,0xf4]
- vmulps %ymm12, %ymm4, %ymm6
-
-// CHECK: vmulpd %ymm12, %ymm4, %ymm6
-// CHECK: encoding: [0xc4,0xc1,0x5d,0x59,0xf4]
- vmulpd %ymm12, %ymm4, %ymm6
-
-// CHECK: vmaxps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5f,0x30]
- vmaxps (%rax), %ymm4, %ymm6
-
-// CHECK: vmaxpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5f,0x30]
- vmaxpd (%rax), %ymm4, %ymm6
-
-// CHECK: vminps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5d,0x30]
- vminps (%rax), %ymm4, %ymm6
-
-// CHECK: vminpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5d,0x30]
- vminpd (%rax), %ymm4, %ymm6
-
-// CHECK: vsubps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5c,0x30]
- vsubps (%rax), %ymm4, %ymm6
-
-// CHECK: vsubpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5c,0x30]
- vsubpd (%rax), %ymm4, %ymm6
-
-// CHECK: vdivps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x5e,0x30]
- vdivps (%rax), %ymm4, %ymm6
-
-// CHECK: vdivpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x5e,0x30]
- vdivpd (%rax), %ymm4, %ymm6
-
-// CHECK: vaddps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x58,0x30]
- vaddps (%rax), %ymm4, %ymm6
-
-// CHECK: vaddpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x58,0x30]
- vaddpd (%rax), %ymm4, %ymm6
-
-// CHECK: vmulps (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdc,0x59,0x30]
- vmulps (%rax), %ymm4, %ymm6
-
-// CHECK: vmulpd (%rax), %ymm4, %ymm6
-// CHECK: encoding: [0xc5,0xdd,0x59,0x30]
- vmulpd (%rax), %ymm4, %ymm6
-
-// CHECK: vsqrtpd %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7d,0x51,0xe3]
- vsqrtpd %ymm11, %ymm12
-
-// CHECK: vsqrtpd (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7d,0x51,0x20]
- vsqrtpd (%rax), %ymm12
-
-// CHECK: vsqrtps %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x51,0xe3]
- vsqrtps %ymm11, %ymm12
-
-// CHECK: vsqrtps (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x51,0x20]
- vsqrtps (%rax), %ymm12
-
-// CHECK: vrsqrtps %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x52,0xe3]
- vrsqrtps %ymm11, %ymm12
-
-// CHECK: vrsqrtps (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x52,0x20]
- vrsqrtps (%rax), %ymm12
-
-// CHECK: vrcpps %ymm11, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x53,0xe3]
- vrcpps %ymm11, %ymm12
-
-// CHECK: vrcpps (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x53,0x20]
- vrcpps (%rax), %ymm12
-
-// CHECK: vandps %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0c,0x54,0xdc]
- vandps %ymm12, %ymm14, %ymm11
-
-// CHECK: vandpd %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0d,0x54,0xdc]
- vandpd %ymm12, %ymm14, %ymm11
-
-// CHECK: vandps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x54,0x54,0xcb,0xfc]
- vandps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x54,0x54,0xcb,0xfc]
- vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vorps %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0c,0x56,0xdc]
- vorps %ymm12, %ymm14, %ymm11
-
-// CHECK: vorpd %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0d,0x56,0xdc]
- vorpd %ymm12, %ymm14, %ymm11
-
-// CHECK: vorps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x56,0x54,0xcb,0xfc]
- vorps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x56,0x54,0xcb,0xfc]
- vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vxorps %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0c,0x57,0xdc]
- vxorps %ymm12, %ymm14, %ymm11
-
-// CHECK: vxorpd %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0d,0x57,0xdc]
- vxorpd %ymm12, %ymm14, %ymm11
-
-// CHECK: vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x57,0x54,0xcb,0xfc]
- vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x57,0x54,0xcb,0xfc]
- vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vandnps %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0c,0x55,0xdc]
- vandnps %ymm12, %ymm14, %ymm11
-
-// CHECK: vandnpd %ymm12, %ymm14, %ymm11
-// CHECK: encoding: [0xc4,0x41,0x0d,0x55,0xdc]
- vandnpd %ymm12, %ymm14, %ymm11
-
-// CHECK: vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1c,0x55,0x54,0xcb,0xfc]
- vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-// CHECK: encoding: [0xc5,0x1d,0x55,0x54,0xcb,0xfc]
- vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10
-
-// CHECK: vcvtps2pd %xmm13, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7c,0x5a,0xe5]
- vcvtps2pd %xmm13, %ymm12
-
-// CHECK: vcvtps2pd (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x5a,0x20]
- vcvtps2pd (%rax), %ymm12
-
-// CHECK: vcvtdq2pd %xmm13, %ymm12
-// CHECK: encoding: [0xc4,0x41,0x7e,0xe6,0xe5]
- vcvtdq2pd %xmm13, %ymm12
-
-// CHECK: vcvtdq2pd (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7e,0xe6,0x20]
- vcvtdq2pd (%rax), %ymm12
-
-// CHECK: vcvtdq2ps %ymm12, %ymm10
-// CHECK: encoding: [0xc4,0x41,0x7c,0x5b,0xd4]
- vcvtdq2ps %ymm12, %ymm10
-
-// CHECK: vcvtdq2ps (%rax), %ymm12
-// CHECK: encoding: [0xc5,0x7c,0x5b,0x20]
- vcvtdq2ps (%rax), %ymm12
-
-// CHECK: vcvtps2dq %ymm12, %ymm10
-// CHECK: encoding: [0xc4,0x41,0x7d,0x5b,0xd4]
- vcvtps2dq %ymm12, %ymm10
-
-// CHECK: vcvtps2dq (%rax), %ymm10
-// CHECK: encoding: [0xc5,0x7d,0x5b,0x10]
- vcvtps2dq (%rax), %ymm10
-
-// CHECK: vcvttps2dq %ymm12, %ymm10
-// CHECK: encoding: [0xc4,0x41,0x7e,0x5b,0xd4]
- vcvttps2dq %ymm12, %ymm10
-
-// CHECK: vcvttps2dq (%rax), %ymm10
-// CHECK: encoding: [0xc5,0x7e,0x5b,0x10]
- vcvttps2dq (%rax), %ymm10
-
-// CHECK: vcvttpd2dq %xmm11, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3]
- vcvttpd2dq %xmm11, %xmm10
-
-// CHECK: vcvttpd2dq %ymm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xd4]
- vcvttpd2dq %ymm12, %xmm10
-
-// CHECK: vcvttpd2dqx %xmm11, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3]
- vcvttpd2dqx %xmm11, %xmm10
-
-// CHECK: vcvttpd2dqx (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x79,0xe6,0x18]
- vcvttpd2dqx (%rax), %xmm11
-
-// CHECK: vcvttpd2dqy %ymm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xdc]
- vcvttpd2dqy %ymm12, %xmm11
-
-// CHECK: vcvttpd2dqy (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x7d,0xe6,0x18]
- vcvttpd2dqy (%rax), %xmm11
-
-// CHECK: vcvtpd2ps %ymm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xd4]
- vcvtpd2ps %ymm12, %xmm10
-
-// CHECK: vcvtpd2psx %xmm11, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xd3]
- vcvtpd2psx %xmm11, %xmm10
-
-// CHECK: vcvtpd2psx (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x79,0x5a,0x18]
- vcvtpd2psx (%rax), %xmm11
-
-// CHECK: vcvtpd2psy %ymm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xdc]
- vcvtpd2psy %ymm12, %xmm11
-
-// CHECK: vcvtpd2psy (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x7d,0x5a,0x18]
- vcvtpd2psy (%rax), %xmm11
-
-// CHECK: vcvtpd2dq %ymm12, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xd4]
- vcvtpd2dq %ymm12, %xmm10
-
-// CHECK: vcvtpd2dqy %ymm12, %xmm11
-// CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xdc]
- vcvtpd2dqy %ymm12, %xmm11
-
-// CHECK: vcvtpd2dqy (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x7f,0xe6,0x18]
- vcvtpd2dqy (%rax), %xmm11
-
-// CHECK: vcvtpd2dqx %xmm11, %xmm10
-// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xd3]
- vcvtpd2dqx %xmm11, %xmm10
-
-// CHECK: vcvtpd2dqx (%rax), %xmm11
-// CHECK: encoding: [0xc5,0x7b,0xe6,0x18]
- vcvtpd2dqx (%rax), %xmm11
-
-// CHECK: vcmpps $0, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x00]
- vcmpeqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $2, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x02]
- vcmpleps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $1, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x01]
- vcmpltps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $4, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x04]
- vcmpneqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $6, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x06]
- vcmpnleps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $5, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x05]
- vcmpnltps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $7, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x07]
- vcmpordps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $3, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x03]
- vcmpunordps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $0, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $2, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmpleps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $1, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $4, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $6, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnleps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $5, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $7, -4(%rbx,%rcx,8), %ymm6, %ymm12
-// CHECK: encoding: [0xc5,0x4c,0xc2,0x64,0xcb,0xfc,0x07]
- vcmpordps -4(%rbx,%rcx,8), %ymm6, %ymm12
-
-// CHECK: vcmpps $3, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1c,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordps -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $0, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x00]
- vcmpeqpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $2, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x02]
- vcmplepd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $1, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x01]
- vcmpltpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $4, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x04]
- vcmpneqpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $6, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x06]
- vcmpnlepd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $5, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x05]
- vcmpnltpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $7, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x07]
- vcmpordpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $3, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1d,0xc2,0xeb,0x03]
- vcmpunordpd %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmppd $0, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x00]
- vcmpeqpd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $2, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x02]
- vcmplepd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $1, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x01]
- vcmpltpd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $4, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x04]
- vcmpneqpd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $6, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x06]
- vcmpnlepd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $5, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x05]
- vcmpnltpd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmppd $7, -4(%rbx,%rcx,8), %ymm6, %ymm12
-// CHECK: encoding: [0xc5,0x4d,0xc2,0x64,0xcb,0xfc,0x07]
- vcmpordpd -4(%rbx,%rcx,8), %ymm6, %ymm12
-
-// CHECK: vcmppd $3, -4(%rbx,%rcx,8), %ymm12, %ymm13
-// CHECK: encoding: [0xc5,0x1d,0xc2,0x6c,0xcb,0xfc,0x03]
- vcmpunordpd -4(%rbx,%rcx,8), %ymm12, %ymm13
-
-// CHECK: vcmpps $8, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x08]
- vcmpeq_uqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $9, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x09]
- vcmpngeps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $10, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0a]
- vcmpngtps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $11, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0b]
- vcmpfalseps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $12, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0c]
- vcmpneq_oqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $13, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0d]
- vcmpgeps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $14, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0e]
- vcmpgtps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $15, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x0f]
- vcmptrueps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $16, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x10]
- vcmpeq_osps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $17, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x11]
- vcmplt_oqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $18, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x12]
- vcmple_oqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $19, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x13]
- vcmpunord_sps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $20, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x14]
- vcmpneq_usps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $21, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x15]
- vcmpnlt_uqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $22, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x16]
- vcmpnle_uqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $23, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x17]
- vcmpord_sps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $24, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x18]
- vcmpeq_usps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $25, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x19]
- vcmpnge_uqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $26, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1a]
- vcmpngt_uqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $27, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1b]
- vcmpfalse_osps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $28, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1c]
- vcmpneq_osps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $29, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1d]
- vcmpge_oqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $30, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1e]
- vcmpgt_oqps %ymm11, %ymm12, %ymm13
-
-// CHECK: vcmpps $31, %ymm11, %ymm12, %ymm13
-// CHECK: encoding: [0xc4,0x41,0x1c,0xc2,0xeb,0x1f]
- vcmptrue_usps %ymm11, %ymm12, %ymm13
+// CHECK: movq 57005(,%riz), %rbx
+// CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
+ movq 57005(,%riz), %rbx
+
+// CHECK: movq 48879(,%riz), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0x25,0xef,0xbe,0x00,0x00]
+ movq 48879(,%riz), %rax
+
+// CHECK: movq -4(,%riz,8), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff]
+ movq -4(,%riz,8), %rax
+
+// CHECK: movq (%rcx,%riz), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0x21]
+ movq (%rcx,%riz), %rax
+
+// CHECK: movq (%rcx,%riz,8), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0xe1]
+ movq (%rcx,%riz,8), %rax
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-new-encoder.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-new-encoder.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_64-new-encoder.s Sat Jul 31 19:59:02 2010
@@ -72,9 +72,9 @@
// Not moffset forms of moves, they are x86-32 only! rdar://7947184
-movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,A,A,A,A]
-movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,A,A,A,A]
-movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,A,A,A,A]
+movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,0x00,0x00,0x00,0x00]
+movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
+movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
// CHECK: pushfq # encoding: [0x9c]
pushf
@@ -150,3 +150,6 @@
// CHECK: [0x65,0x8b,0x04,0x25,0x7c,0x00,0x00,0x00]
movl %gs:124, %eax
+// CHECK: jmpq *8(%rax)
+// CHECK: encoding: [0xff,0x60,0x08]
+ jmp *8(%rax)
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_instructions.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_instructions.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/X86/x86_instructions.s Sat Jul 31 19:59:02 2010
@@ -56,7 +56,7 @@
subl %eax, %ebx
// FIXME: Check that this matches the correct instruction.
-// CHECK: call *%rax
+// CHECK: callq *%rax
call *%rax
// FIXME: Check that this matches the correct instruction.
Modified: llvm/branches/wendling/eh/test/MC/AsmParser/directive_abort.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/AsmParser/directive_abort.s?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/AsmParser/directive_abort.s (original)
+++ llvm/branches/wendling/eh/test/MC/AsmParser/directive_abort.s Sat Jul 31 19:59:02 2010
@@ -1,6 +1,6 @@
# RUN: llvm-mc -triple i386-unknown-unknown %s 2> %t
# RUN: FileCheck -input-file %t %s
-# CHECK: .abort "please stop assembing"
-TEST0:
- .abort "please stop assembing"
+# CHECK: error: .abort 'please stop assembing'
+TEST0:
+ .abort please stop assembing
Modified: llvm/branches/wendling/eh/test/MC/Disassembler/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/MC/Disassembler/neon-tests.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/MC/Disassembler/neon-tests.txt (original)
+++ llvm/branches/wendling/eh/test/MC/Disassembler/neon-tests.txt Sat Jul 31 19:59:02 2010
@@ -25,6 +25,9 @@
# CHECK: vmov.i64 q6, #0xFF00FF00FF
0x75 0xce 0x81 0xf2
+# CHECK: vmvn.i32 d0, #0x0
+0x30 0x00 0x80 0xf2
+
# CHECK: vmul.f32 d0, d0, d6
0x16 0x0d 0x00 0xf3
Modified: llvm/branches/wendling/eh/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Makefile (original)
+++ llvm/branches/wendling/eh/test/Makefile Sat Jul 31 19:59:02 2010
@@ -202,3 +202,4 @@
-e "s#@ENABLE_SHARED@#$(ENABLE_SHARED)#g" \
-e "s#@SHLIBPATH_VAR@#$(SHLIBPATH_VAR)#g" \
$(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@
+
Modified: llvm/branches/wendling/eh/test/Other/inline-asm-newline-terminator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Other/inline-asm-newline-terminator.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Other/inline-asm-newline-terminator.ll (original)
+++ llvm/branches/wendling/eh/test/Other/inline-asm-newline-terminator.ll Sat Jul 31 19:59:02 2010
@@ -1,5 +1,4 @@
; RUN: llc -filetype=obj -o - < %s
-; XFAIL: vg_leak
; ModuleID = 't.c'
target triple = "x86_64-apple-darwin10.0.0"
Modified: llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/crash.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/crash.ll (original)
+++ llvm/branches/wendling/eh/test/Transforms/IndVarSimplify/crash.ll Sat Jul 31 19:59:02 2010
@@ -1,4 +1,5 @@
; RUN: opt -indvars %s -disable-output
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
declare i32 @putchar(i8) nounwind
@@ -17,3 +18,38 @@
; <label>:6 ; preds = %1
ret void
}
+
+; PR7562
+define void @fannkuch() nounwind {
+entry: ; preds = %entry
+ br label %bb12
+
+bb12: ; preds = %bb29, %entry
+ %i.1 = phi i32 [ undef, %entry ], [ %i.0, %bb29 ] ; <i32> [#uses=2]
+ %r.1 = phi i32 [ undef, %entry ], [ %r.0, %bb29 ] ; <i32> [#uses=2]
+ br i1 undef, label %bb13, label %bb24
+
+bb13: ; preds = %bb12
+ br label %bb24
+
+bb24: ; preds = %bb30, %bb13, %bb12
+ %i.2 = phi i32 [ %i.1, %bb13 ], [ %i.0, %bb30 ], [ %i.1, %bb12 ] ; <i32> [#uses=1]
+ %r.0 = phi i32 [ %r.1, %bb13 ], [ %2, %bb30 ], [ %r.1, %bb12 ] ; <i32> [#uses=3]
+ br label %bb28
+
+bb27: ; preds = %bb28
+ %0 = add nsw i32 %i.0, 1 ; <i32> [#uses=1]
+ br label %bb28
+
+bb28: ; preds = %bb27, %bb26
+ %i.0 = phi i32 [ %i.2, %bb24 ], [ %0, %bb27 ] ; <i32> [#uses=4]
+ %1 = icmp slt i32 %i.0, %r.0 ; <i1> [#uses=1]
+ br i1 %1, label %bb27, label %bb29
+
+bb29: ; preds = %bb28
+ br i1 undef, label %bb12, label %bb30
+
+bb30: ; preds = %bb29
+ %2 = add nsw i32 %r.0, 1 ; <i32> [#uses=1]
+ br label %bb24
+}
Modified: llvm/branches/wendling/eh/test/Transforms/JumpThreading/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Transforms/JumpThreading/crash.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Transforms/JumpThreading/crash.ll (original)
+++ llvm/branches/wendling/eh/test/Transforms/JumpThreading/crash.ll Sat Jul 31 19:59:02 2010
@@ -216,6 +216,9 @@
; PR5698
define void @test7(i32 %x) {
+entry:
+ br label %tailrecurse
+
tailrecurse:
switch i32 %x, label %return [
i32 2, label %bb2
@@ -387,3 +390,50 @@
ret void
}
+; PR7647
+define void @test15() nounwind {
+entry:
+ ret void
+
+if.then237:
+ br label %lbl_664
+
+lbl_596: ; preds = %lbl_664, %for.end37
+ volatile store i64 undef, i64* undef, align 4
+ br label %for.cond111
+
+for.cond111: ; preds = %safe_sub_func_int64_t_s_s.exit, %lbl_596
+ %storemerge = phi i8 [ undef, %cond.true.i100 ], [ 22, %lbl_596 ] ; <i8> [#uses=1]
+ %l_678.5 = phi i64 [ %l_678.3, %cond.true.i100 ], [ undef, %lbl_596 ] ; <i64> [#uses=2]
+ %cmp114 = icmp slt i8 %storemerge, -2 ; <i1> [#uses=1]
+ br i1 %cmp114, label %lbl_664, label %if.end949
+
+lbl_664: ; preds = %for.end1058, %if.then237, %for.cond111
+ %l_678.3 = phi i64 [ %l_678.5, %for.cond111 ], [ %l_678.2, %for.cond1035 ], [ 5, %if.then237 ] ; <i64> [#uses=1]
+ %tobool118 = icmp eq i32 undef, 0 ; <i1> [#uses=1]
+ br i1 %tobool118, label %cond.true.i100, label %lbl_596
+
+cond.true.i100: ; preds = %for.inc120
+ br label %for.cond111
+
+lbl_709:
+ br label %if.end949
+
+for.cond603: ; preds = %for.body607, %if.end336
+ br i1 undef, label %for.cond603, label %if.end949
+
+if.end949: ; preds = %for.cond603, %lbl_709, %for.cond111
+ %l_678.2 = phi i64 [ %l_678.5, %for.cond111 ], [ undef, %lbl_709 ], [ 5, %for.cond603 ] ; <i64> [#uses=1]
+ br label %for.body1016
+
+for.body1016: ; preds = %for.cond1012
+ br label %for.body1016
+
+for.cond1035: ; preds = %for.inc1055, %if.then1026
+ br i1 undef, label %for.cond1040, label %lbl_664
+
+for.cond1040: ; preds = %for.body1044, %for.cond1035
+ ret void
+}
+
+
Modified: llvm/branches/wendling/eh/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll (original)
+++ llvm/branches/wendling/eh/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll Sat Jul 31 19:59:02 2010
@@ -1,6 +1,6 @@
-; RUN: opt < %s -lcssa -S | \
+; RUN: opt < %s -loopsimplify -lcssa -S | \
; RUN: grep {%%SJE.0.0.lcssa = phi .struct.SetJmpMapEntry}
-; RUN: opt < %s -lcssa -S | \
+; RUN: opt < %s -loopsimplify -lcssa -S | \
; RUN: grep {%%SJE.0.0.lcssa1 = phi .struct.SetJmpMapEntry}
%struct.SetJmpMapEntry = type { i8*, i32, %struct.SetJmpMapEntry* }
Modified: llvm/branches/wendling/eh/tools/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/Makefile (original)
+++ llvm/branches/wendling/eh/tools/Makefile Sat Jul 31 19:59:02 2010
@@ -15,14 +15,11 @@
# NOTE: The tools are organized into five groups of four consisting of one
# large and three small executables. This is done to minimize memory load
# in parallel builds. Please retain this ordering.
-
-# libEnhancedDisassembly must be built ahead of llvm-mc
-# because llvm-mc links against libEnhancedDisassembly
-DIRS := llvm-config edis llvm-mc
+DIRS := llvm-config
PARALLEL_DIRS := opt llvm-as llvm-dis \
llc llvm-ranlib llvm-ar llvm-nm \
llvm-ld llvm-prof llvm-link \
- lli llvm-extract \
+ lli llvm-extract llvm-mc \
bugpoint llvm-bcanalyzer llvm-stub \
llvmc
@@ -34,6 +31,7 @@
include $(LEVEL)/Makefile.config
+
# These libraries build as dynamic libraries (.dylib /.so), they can only be
# built if ENABLE_PIC is set.
ifeq ($(ENABLE_PIC),1)
@@ -46,6 +44,14 @@
else
PARALLEL_DIRS += lto
endif
+
+ # The edis library is only supported if ARM and/or X86 are enabled, and if
+ # LLVM is being built PIC on platforms that support dylibs.
+ ifneq ($(DISABLE_EDIS),1)
+ ifneq ($(filter $(TARGETS_TO_BUILD), X86 ARM),)
+ PARALLEL_DIRS += edis
+ endif
+ endif
endif
endif
Modified: llvm/branches/wendling/eh/tools/bugpoint/BugDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/BugDriver.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/BugDriver.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/BugDriver.cpp Sat Jul 31 19:59:02 2010
@@ -211,7 +211,7 @@
// matches, then we assume there is a miscompilation bug and try to
// diagnose it.
outs() << "*** Checking the code generator...\n";
- bool Diff = diffProgram("", "", false, &Error);
+ bool Diff = diffProgram(Program, "", "", false, &Error);
if (!Error.empty()) {
errs() << Error;
return debugCodeGeneratorCrash(ErrMsg);
Modified: llvm/branches/wendling/eh/tools/bugpoint/BugDriver.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/BugDriver.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/BugDriver.h (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/BugDriver.h Sat Jul 31 19:59:02 2010
@@ -174,18 +174,21 @@
/// executeProgram - This method runs "Program", capturing the output of the
/// program to a file. A recommended filename may be optionally specified.
///
- std::string executeProgram(std::string OutputFilename,
+ std::string executeProgram(const Module *Program,
+ std::string OutputFilename,
std::string Bitcode,
const std::string &SharedObjects,
AbstractInterpreter *AI,
- std::string *Error);
+ std::string *Error) const;
/// executeProgramSafely - Used to create reference output with the "safe"
/// backend, if reference output is not provided. If there is a problem with
/// the code generator (e.g., llc crashes), this will return false and set
/// Error.
///
- std::string executeProgramSafely(std::string OutputFile, std::string *Error);
+ std::string executeProgramSafely(const Module *Program,
+ std::string OutputFile,
+ std::string *Error) const;
/// createReferenceFile - calls compileProgram and then records the output
/// into ReferenceOutputFile. Returns true if reference file created, false
@@ -200,15 +203,17 @@
/// is different, 1 is returned. If there is a problem with the code
/// generator (e.g., llc crashes), this will return -1 and set Error.
///
- bool diffProgram(const std::string &BitcodeFile = "",
+ bool diffProgram(const Module *Program,
+ const std::string &BitcodeFile = "",
const std::string &SharedObj = "",
bool RemoveBitcode = false,
- std::string *Error = 0);
+ std::string *Error = 0) const;
- /// EmitProgressBitcode - This function is used to output the current Program
- /// to a file named "bugpoint-ID.bc".
+ /// EmitProgressBitcode - This function is used to output M to a file named
+ /// "bugpoint-ID.bc".
///
- void EmitProgressBitcode(const std::string &ID, bool NoFlyer = false);
+ void EmitProgressBitcode(const Module *M, const std::string &ID,
+ bool NoFlyer = false);
/// deleteInstructionFromProgram - This method clones the current Program and
/// deletes the specified instruction from the cloned module. It then runs a
@@ -274,7 +279,7 @@
/// writeProgramToFile - This writes the current "Program" to the named
/// bitcode file. If an error occurs, true is returned.
///
- bool writeProgramToFile(const std::string &Filename, Module *M = 0) const;
+ bool writeProgramToFile(const std::string &Filename, const Module *M) const;
private:
/// runPasses - Just like the method above, but this just returns true or
Modified: llvm/branches/wendling/eh/tools/bugpoint/CrashDebugger.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/CrashDebugger.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/CrashDebugger.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/CrashDebugger.cpp Sat Jul 31 19:59:02 2010
@@ -471,7 +471,7 @@
return true;
if (GVs.size() < OldSize)
- BD.EmitProgressBitcode("reduced-global-variables");
+ BD.EmitProgressBitcode(BD.getProgram(), "reduced-global-variables");
}
}
}
@@ -492,7 +492,7 @@
ReduceCrashingFunctions(BD, TestFn).reduceList(Functions, Error);
if (Functions.size() < OldSize)
- BD.EmitProgressBitcode("reduced-function");
+ BD.EmitProgressBitcode(BD.getProgram(), "reduced-function");
}
// Attempt to delete entire basic blocks at a time to speed up
@@ -509,7 +509,7 @@
unsigned OldSize = Blocks.size();
ReduceCrashingBlocks(BD, TestFn).reduceList(Blocks, Error);
if (Blocks.size() < OldSize)
- BD.EmitProgressBitcode("reduced-blocks");
+ BD.EmitProgressBitcode(BD.getProgram(), "reduced-blocks");
}
// Attempt to delete instructions using bisection. This should help out nasty
@@ -602,7 +602,7 @@
}
}
- BD.EmitProgressBitcode("reduced-simplified");
+ BD.EmitProgressBitcode(BD.getProgram(), "reduced-simplified");
return false;
}
@@ -628,7 +628,7 @@
<< (PassesToRun.size() == 1 ? ": " : "es: ")
<< getPassesString(PassesToRun) << '\n';
- EmitProgressBitcode(ID);
+ EmitProgressBitcode(Program, ID);
bool Success = DebugACrash(*this, TestForOptimizerCrash, Error);
assert(Error.empty());
Modified: llvm/branches/wendling/eh/tools/bugpoint/ExecutionDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/ExecutionDriver.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/ExecutionDriver.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/ExecutionDriver.cpp Sat Jul 31 19:59:02 2010
@@ -320,11 +320,12 @@
/// program to a file, returning the filename of the file. A recommended
/// filename may be optionally specified.
///
-std::string BugDriver::executeProgram(std::string OutputFile,
+std::string BugDriver::executeProgram(const Module *Program,
+ std::string OutputFile,
std::string BitcodeFile,
const std::string &SharedObj,
AbstractInterpreter *AI,
- std::string *Error) {
+ std::string *Error) const {
if (AI == 0) AI = Interpreter;
assert(AI && "Interpreter should have been created already!");
bool CreatedBitcode = false;
@@ -399,9 +400,10 @@
/// executeProgramSafely - Used to create reference output with the "safe"
/// backend, if reference output is not provided.
///
-std::string BugDriver::executeProgramSafely(std::string OutputFile,
- std::string *Error) {
- return executeProgram(OutputFile, "", "", SafeInterpreter, Error);
+std::string BugDriver::executeProgramSafely(const Module *Program,
+ std::string OutputFile,
+ std::string *Error) const {
+ return executeProgram(Program, OutputFile, "", "", SafeInterpreter, Error);
}
std::string BugDriver::compileSharedObject(const std::string &BitcodeFile,
@@ -440,7 +442,7 @@
if (!Error.empty())
return false;
- ReferenceOutputFile = executeProgramSafely(Filename, &Error);
+ ReferenceOutputFile = executeProgramSafely(Program, Filename, &Error);
if (!Error.empty()) {
errs() << Error;
if (Interpreter != SafeInterpreter) {
@@ -460,12 +462,14 @@
/// is different, 1 is returned. If there is a problem with the code
/// generator (e.g., llc crashes), this will return -1 and set Error.
///
-bool BugDriver::diffProgram(const std::string &BitcodeFile,
+bool BugDriver::diffProgram(const Module *Program,
+ const std::string &BitcodeFile,
const std::string &SharedObject,
bool RemoveBitcode,
- std::string *ErrMsg) {
+ std::string *ErrMsg) const {
// Execute the program, generating an output file...
- sys::Path Output(executeProgram("", BitcodeFile, SharedObject, 0, ErrMsg));
+ sys::Path Output(executeProgram(Program, "", BitcodeFile, SharedObject, 0,
+ ErrMsg));
if (!ErrMsg->empty())
return false;
Modified: llvm/branches/wendling/eh/tools/bugpoint/ExtractFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/ExtractFunction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/ExtractFunction.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/ExtractFunction.cpp Sat Jul 31 19:59:02 2010
@@ -143,11 +143,9 @@
Module *NewM = runPassesOn(M, LoopExtractPasses);
if (NewM == 0) {
- Module *Old = swapProgramIn(M);
outs() << "*** Loop extraction failed: ";
- EmitProgressBitcode("loopextraction", true);
+ EmitProgressBitcode(M, "loopextraction", true);
outs() << "*** Sorry. :( Please report a bug!\n";
- swapProgramIn(Old);
return 0;
}
@@ -201,7 +199,7 @@
/// static ctors/dtors, we need to add an llvm.global_[cd]tors global to M2, and
/// prune appropriate entries out of M1s list.
static void SplitStaticCtorDtor(const char *GlobalName, Module *M1, Module *M2,
- ValueMap<const Value*, Value*> VMap) {
+ ValueMap<const Value*, Value*> &VMap) {
GlobalVariable *GV = M1->getNamedGlobal(GlobalName);
if (!GV || GV->isDeclaration() || GV->hasLocalLinkage() ||
!GV->use_empty()) return;
@@ -327,9 +325,7 @@
if (uniqueFilename.createTemporaryFileOnDisk(true, &ErrMsg)) {
outs() << "*** Basic Block extraction failed!\n";
errs() << "Error creating temporary file: " << ErrMsg << "\n";
- M = swapProgramIn(M);
- EmitProgressBitcode("basicblockextractfail", true);
- swapProgramIn(M);
+ EmitProgressBitcode(M, "basicblockextractfail", true);
return 0;
}
sys::RemoveFileOnSignal(uniqueFilename);
@@ -340,9 +336,7 @@
outs() << "*** Basic Block extraction failed!\n";
errs() << "Error writing list of blocks to not extract: " << ErrorInfo
<< "\n";
- M = swapProgramIn(M);
- EmitProgressBitcode("basicblockextractfail", true);
- swapProgramIn(M);
+ EmitProgressBitcode(M, "basicblockextractfail", true);
return 0;
}
for (std::vector<BasicBlock*>::const_iterator I = BBs.begin(), E = BBs.end();
@@ -360,17 +354,14 @@
const char *ExtraArg = uniqueFN.c_str();
std::vector<const PassInfo*> PI;
- std::vector<BasicBlock *> EmptyBBs; // This parameter is ignored.
- PI.push_back(getPI(createBlockExtractorPass(EmptyBBs)));
+ PI.push_back(getPI(createBlockExtractorPass()));
Module *Ret = runPassesOn(M, PI, false, 1, &ExtraArg);
uniqueFilename.eraseFromDisk(); // Free disk space
if (Ret == 0) {
outs() << "*** Basic Block extraction failed, please report a bug!\n";
- M = swapProgramIn(M);
- EmitProgressBitcode("basicblockextractfail", true);
- swapProgramIn(M);
+ EmitProgressBitcode(M, "basicblockextractfail", true);
}
return Ret;
}
Modified: llvm/branches/wendling/eh/tools/bugpoint/FindBugs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/FindBugs.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/FindBugs.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/FindBugs.cpp Sat Jul 31 19:59:02 2010
@@ -89,7 +89,7 @@
// output (created above).
//
outs() << "*** Checking if passes caused miscompliation:\n";
- bool Diff = diffProgram(Filename, "", false, &Error);
+ bool Diff = diffProgram(Program, Filename, "", false, &Error);
if (Error.empty() && Diff) {
outs() << "\n*** diffProgram returned true!\n";
debugMiscompilation(&Error);
Modified: llvm/branches/wendling/eh/tools/bugpoint/Miscompilation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/Miscompilation.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/Miscompilation.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/Miscompilation.cpp Sat Jul 31 19:59:02 2010
@@ -71,13 +71,13 @@
errs() << " Error running this sequence of passes"
<< " on the input program!\n";
BD.setPassesToRun(Suffix);
- BD.EmitProgressBitcode("pass-error", false);
+ BD.EmitProgressBitcode(BD.getProgram(), "pass-error", false);
exit(BD.debugOptimizerCrash());
}
// Check to see if the finished program matches the reference output...
- bool Diff = BD.diffProgram(BitcodeResult, "", true /*delete bitcode*/,
- &Error);
+ bool Diff = BD.diffProgram(BD.getProgram(), BitcodeResult, "",
+ true /*delete bitcode*/, &Error);
if (!Error.empty())
return InternalError;
if (Diff) {
@@ -108,12 +108,12 @@
errs() << " Error running this sequence of passes"
<< " on the input program!\n";
BD.setPassesToRun(Prefix);
- BD.EmitProgressBitcode("pass-error", false);
+ BD.EmitProgressBitcode(BD.getProgram(), "pass-error", false);
exit(BD.debugOptimizerCrash());
}
// If the prefix maintains the predicate by itself, only keep the prefix!
- Diff = BD.diffProgram(BitcodeResult, "", false, &Error);
+ Diff = BD.diffProgram(BD.getProgram(), BitcodeResult, "", false, &Error);
if (!Error.empty())
return InternalError;
if (Diff) {
@@ -148,12 +148,13 @@
errs() << " Error running this sequence of passes"
<< " on the input program!\n";
BD.setPassesToRun(Suffix);
- BD.EmitProgressBitcode("pass-error", false);
+ BD.EmitProgressBitcode(BD.getProgram(), "pass-error", false);
exit(BD.debugOptimizerCrash());
}
// Run the result...
- Diff = BD.diffProgram(BitcodeResult, "", true /*delete bitcode*/, &Error);
+ Diff = BD.diffProgram(BD.getProgram(), BitcodeResult, "",
+ true /*delete bitcode*/, &Error);
if (!Error.empty())
return InternalError;
if (Diff) {
@@ -198,18 +199,20 @@
return NoFailure;
}
- int TestFuncs(const std::vector<Function*> &Prefix, std::string &Error);
+ bool TestFuncs(const std::vector<Function*> &Prefix, std::string &Error);
};
}
/// TestMergedProgram - Given two modules, link them together and run the
-/// program, checking to see if the program matches the diff. If the diff
-/// matches, return false, otherwise return true. If the DeleteInputs argument
-/// is set to true then this function deletes both input modules before it
-/// returns.
-///
-static bool TestMergedProgram(BugDriver &BD, Module *M1, Module *M2,
- bool DeleteInputs, std::string &Error) {
+/// program, checking to see if the program matches the diff. If there is
+/// an error, return NULL. If not, return the merged module. The Broken argument
+/// will be set to true if the output is different. If the DeleteInputs
+/// argument is set to true then this function deletes both input
+/// modules before it returns.
+///
+static Module *TestMergedProgram(const BugDriver &BD, Module *M1, Module *M2,
+ bool DeleteInputs, std::string &Error,
+ bool &Broken) {
// Link the two portions of the program back to together.
std::string ErrorMsg;
if (!DeleteInputs) {
@@ -223,24 +226,22 @@
}
delete M2; // We are done with this module.
- OwningPtr<Module> OldProgram(BD.swapProgramIn(M1));
-
- // Execute the program. If it does not match the expected output, we must
- // return true.
- bool Broken = BD.diffProgram("", "", false, &Error);
+ // Execute the program.
+ Broken = BD.diffProgram(M1, "", "", false, &Error);
if (!Error.empty()) {
- // Delete the linked module & restore the original
- delete BD.swapProgramIn(OldProgram.take());
+ // Delete the linked module
+ delete M1;
+ return NULL;
}
- return Broken;
+ return M1;
}
/// TestFuncs - split functions in a Module into two groups: those that are
/// under consideration for miscompilation vs. those that are not, and test
/// accordingly. Each group of functions becomes a separate Module.
///
-int ReduceMiscompilingFunctions::TestFuncs(const std::vector<Function*> &Funcs,
- std::string &Error) {
+bool ReduceMiscompilingFunctions::TestFuncs(const std::vector<Function*> &Funcs,
+ std::string &Error) {
// Test to see if the function is misoptimized if we ONLY run it on the
// functions listed in Funcs.
outs() << "Checking to see if the program is misoptimized when "
@@ -250,14 +251,35 @@
PrintFunctionList(Funcs);
outs() << '\n';
- // Split the module into the two halves of the program we want.
+ // Create a clone for two reasons:
+ // * If the optimization passes delete any function, the deleted function
+ // will be in the clone and Funcs will still point to valid memory
+ // * If the optimization passes use interprocedural information to break
+ // a function, we want to continue with the original function. Otherwise
+ // we can conclude that a function triggers the bug when in fact one
+ // needs a larger set of original functions to do so.
ValueMap<const Value*, Value*> VMap;
+ Module *Clone = CloneModule(BD.getProgram(), VMap);
+ Module *Orig = BD.swapProgramIn(Clone);
+
+ std::vector<Function*> FuncsOnClone;
+ for (unsigned i = 0, e = Funcs.size(); i != e; ++i) {
+ Function *F = cast<Function>(VMap[Funcs[i]]);
+ FuncsOnClone.push_back(F);
+ }
+
+ // Split the module into the two halves of the program we want.
+ VMap.clear();
Module *ToNotOptimize = CloneModule(BD.getProgram(), VMap);
- Module *ToOptimize = SplitFunctionsOutOfModule(ToNotOptimize, Funcs,
+ Module *ToOptimize = SplitFunctionsOutOfModule(ToNotOptimize, FuncsOnClone,
VMap);
// Run the predicate, note that the predicate will delete both input modules.
- return TestFn(BD, ToOptimize, ToNotOptimize, Error);
+ bool Broken = TestFn(BD, ToOptimize, ToNotOptimize, Error);
+
+ delete BD.swapProgramIn(Orig);
+
+ return Broken;
}
/// DisambiguateGlobalSymbols - Give anonymous global values names.
@@ -307,10 +329,13 @@
// has broken. If something broke, then we'll inform the user and stop
// extraction.
AbstractInterpreter *AI = BD.switchToSafeInterpreter();
- bool Failure = TestMergedProgram(BD, ToOptimizeLoopExtracted, ToNotOptimize,
- false, Error);
- if (!Error.empty())
+ bool Failure;
+ Module *New = TestMergedProgram(BD, ToOptimizeLoopExtracted, ToNotOptimize,
+ false, Error, Failure);
+ if (!New)
return false;
+ // Delete the original and set the new program.
+ delete BD.swapProgramIn(New);
if (Failure) {
BD.switchToInterpreter(AI);
@@ -449,18 +474,36 @@
// Split the module into the two halves of the program we want.
ValueMap<const Value*, Value*> VMap;
+ Module *Clone = CloneModule(BD.getProgram(), VMap);
+ Module *Orig = BD.swapProgramIn(Clone);
+ std::vector<Function*> FuncsOnClone;
+ std::vector<BasicBlock*> BBsOnClone;
+ for (unsigned i = 0, e = FunctionsBeingTested.size(); i != e; ++i) {
+ Function *F = cast<Function>(VMap[FunctionsBeingTested[i]]);
+ FuncsOnClone.push_back(F);
+ }
+ for (unsigned i = 0, e = BBs.size(); i != e; ++i) {
+ BasicBlock *BB = cast<BasicBlock>(VMap[BBs[i]]);
+ BBsOnClone.push_back(BB);
+ }
+ VMap.clear();
+
Module *ToNotOptimize = CloneModule(BD.getProgram(), VMap);
Module *ToOptimize = SplitFunctionsOutOfModule(ToNotOptimize,
- FunctionsBeingTested,
+ FuncsOnClone,
VMap);
// Try the extraction. If it doesn't work, then the block extractor crashed
// or something, in which case bugpoint can't chase down this possibility.
- if (Module *New = BD.ExtractMappedBlocksFromModule(BBs, ToOptimize)) {
+ if (Module *New = BD.ExtractMappedBlocksFromModule(BBsOnClone, ToOptimize)) {
delete ToOptimize;
- // Run the predicate, not that the predicate will delete both input modules.
- return TestFn(BD, New, ToNotOptimize, Error);
+ // Run the predicate,
+ // note that the predicate will delete both input modules.
+ bool Ret = TestFn(BD, New, ToNotOptimize, Error);
+ delete BD.swapProgramIn(Orig);
+ return Ret;
}
+ delete BD.swapProgramIn(Orig);
delete ToOptimize;
delete ToNotOptimize;
return false;
@@ -655,8 +698,13 @@
delete Test;
outs() << " Checking to see if the merged program executes correctly: ";
- bool Broken = TestMergedProgram(BD, Optimized, Safe, true, Error);
- if (Error.empty()) outs() << (Broken ? " nope.\n" : " yup.\n");
+ bool Broken;
+ Module *New = TestMergedProgram(BD, Optimized, Safe, true, Error, Broken);
+ if (New) {
+ outs() << (Broken ? " nope.\n" : " yup.\n");
+ // Delete the original and set the new program.
+ delete BD.swapProgramIn(New);
+ }
return Broken;
}
@@ -678,7 +726,7 @@
outs() << "\n*** Found miscompiling pass"
<< (getPassesToRun().size() == 1 ? "" : "es") << ": "
<< getPassesString(getPassesToRun()) << '\n';
- EmitProgressBitcode("passinput");
+ EmitProgressBitcode(Program, "passinput");
std::vector<Function *> MiscompiledFunctions =
DebugAMiscompilation(*this, TestOptimizer, *Error);
@@ -694,14 +742,12 @@
VMap);
outs() << " Non-optimized portion: ";
- ToNotOptimize = swapProgramIn(ToNotOptimize);
- EmitProgressBitcode("tonotoptimize", true);
- setNewProgram(ToNotOptimize); // Delete hacked module.
+ EmitProgressBitcode(ToNotOptimize, "tonotoptimize", true);
+ delete ToNotOptimize; // Delete hacked module.
outs() << " Portion that is input to optimizer: ";
- ToOptimize = swapProgramIn(ToOptimize);
- EmitProgressBitcode("tooptimize");
- setNewProgram(ToOptimize); // Delete hacked module.
+ EmitProgressBitcode(ToOptimize, "tooptimize");
+ delete ToOptimize; // Delete hacked module.
return;
}
@@ -921,7 +967,8 @@
// Run the code generator on the `Test' code, loading the shared library.
// The function returns whether or not the new output differs from reference.
- bool Result = BD.diffProgram(TestModuleBC.str(), SharedObject, false, &Error);
+ bool Result = BD.diffProgram(BD.getProgram(), TestModuleBC.str(),
+ SharedObject, false, &Error);
if (!Error.empty())
return false;
@@ -938,7 +985,8 @@
///
bool BugDriver::debugCodeGenerator(std::string *Error) {
if ((void*)SafeInterpreter == (void*)Interpreter) {
- std::string Result = executeProgramSafely("bugpoint.safe.out", Error);
+ std::string Result = executeProgramSafely(Program, "bugpoint.safe.out",
+ Error);
if (Error->empty()) {
outs() << "\n*** The \"safe\" i.e. 'known good' backend cannot match "
<< "the reference diff. This may be due to a\n front-end "
Modified: llvm/branches/wendling/eh/tools/bugpoint/OptimizerDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/OptimizerDriver.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/OptimizerDriver.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/OptimizerDriver.cpp Sat Jul 31 19:59:02 2010
@@ -51,13 +51,13 @@
/// file. If an error occurs, true is returned.
///
bool BugDriver::writeProgramToFile(const std::string &Filename,
- Module *M) const {
+ const Module *M) const {
std::string ErrInfo;
raw_fd_ostream Out(Filename.c_str(), ErrInfo,
raw_fd_ostream::F_Binary);
if (!ErrInfo.empty()) return true;
- WriteBitcodeToFile(M ? M : Program, Out);
+ WriteBitcodeToFile(M, Out);
return false;
}
@@ -65,12 +65,13 @@
/// EmitProgressBitcode - This function is used to output the current Program
/// to a file named "bugpoint-ID.bc".
///
-void BugDriver::EmitProgressBitcode(const std::string &ID, bool NoFlyer) {
+void BugDriver::EmitProgressBitcode(const Module *M,
+ const std::string &ID, bool NoFlyer) {
// Output the input to the current pass to a bitcode file, emit a message
// telling the user how to reproduce it: opt -foo blah.bc
//
std::string Filename = OutputPrefix + "-" + ID + ".bc";
- if (writeProgramToFile(Filename)) {
+ if (writeProgramToFile(Filename, M)) {
errs() << "Error opening file '" << Filename << "' for writing!\n";
return;
}
@@ -246,7 +247,7 @@
errs() << " Error running this sequence of passes"
<< " on the input program!\n";
delete OldProgram;
- EmitProgressBitcode("pass-error", false);
+ EmitProgressBitcode(Program, "pass-error", false);
exit(debugOptimizerCrash());
}
swapProgramIn(OldProgram);
Modified: llvm/branches/wendling/eh/tools/bugpoint/ToolRunner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/bugpoint/ToolRunner.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/bugpoint/ToolRunner.cpp (original)
+++ llvm/branches/wendling/eh/tools/bugpoint/ToolRunner.cpp Sat Jul 31 19:59:02 2010
@@ -627,8 +627,8 @@
// GCC abstraction
//
-static bool IsARMArchitecture(std::vector<std::string> Args) {
- for (std::vector<std::string>::const_iterator
+static bool IsARMArchitecture(std::vector<const char*> Args) {
+ for (std::vector<const char*>::const_iterator
I = Args.begin(), E = Args.end(); I != E; ++I) {
if (StringRef(*I).equals_lower("-arch")) {
++I;
@@ -673,7 +673,7 @@
// explicitly told what architecture it is working on, so we get
// it from gcc flags
if ((TargetTriple.getOS() == Triple::Darwin) &&
- !IsARMArchitecture(ArgsForGCC))
+ !IsARMArchitecture(GCCArgs))
GCCArgs.push_back("-force_cpusubtype_ALL");
}
}
@@ -721,6 +721,10 @@
std::vector<const char*> ProgramArgs;
+ // Declared here so that the destructor only runs after
+ // ProgramArgs is used.
+ std::string Exec;
+
if (RemoteClientPath.isEmpty())
ProgramArgs.push_back(OutputBinary.c_str());
else {
@@ -741,7 +745,7 @@
// Full path to the binary. We need to cd to the exec directory because
// there is a dylib there that the exec expects to find in the CWD
char* env_pwd = getenv("PWD");
- std::string Exec = "cd ";
+ Exec = "cd ";
Exec += env_pwd;
Exec += "; ./";
Exec += OutputBinary.c_str();
Modified: llvm/branches/wendling/eh/tools/edis/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/tools/edis/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -1,22 +1,10 @@
set(LLVM_NO_RTTI 1)
-add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/EDInfo.inc
- COMMAND ${LLVM_TABLEGEN_EXE} -o ${CMAKE_CURRENT_BINARY_DIR}/EDInfo.inc
- -gen-enhanced-disassembly-header ${CMAKE_CURRENT_SOURCE_DIR}/EDInfo.td
- DEPENDS tblgen
- COMMENT "Building enhanced disassembly semantic information header (EDInfo.inc)")
-set_source_files_properties(${CMAKE_CURRENT_BINARY_DIR}/EDInfo.inc PROPERTIES GENERATED 1)
-
include_directories(${CMAKE_CURRENT_BINARY_DIR})
add_llvm_library(EnhancedDisassembly
- EDDisassembler.cpp
- EDInst.cpp
- EDMain.cpp
- EDOperand.cpp
- EDToken.cpp
../../include/llvm-c/EnhancedDisassembly.h
- ${CMAKE_CURRENT_BINARY_DIR}/EDInfo.inc
+ EDMain.cpp
)
set_target_properties(EnhancedDisassembly
Removed: llvm/branches/wendling/eh/tools/edis/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDDisassembler.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDDisassembler.cpp (original)
+++ llvm/branches/wendling/eh/tools/edis/EDDisassembler.cpp (removed)
@@ -1,407 +0,0 @@
-//===-EDDisassembler.cpp - LLVM Enhanced Disassembler ---------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the Enhanced Disassembly library's disassembler class.
-// The disassembler is responsible for vending individual instructions according
-// to a given architecture and disassembly syntax.
-//
-//===----------------------------------------------------------------------===//
-
-#include "EDDisassembler.h"
-#include "EDInst.h"
-
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/MC/EDInstInfo.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCDisassembler.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCInstPrinter.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCParser/AsmLexer.h"
-#include "llvm/MC/MCParser/AsmParser.h"
-#include "llvm/MC/MCParser/MCAsmParser.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/Support/MemoryBuffer.h"
-#include "llvm/Support/MemoryObject.h"
-#include "llvm/Support/SourceMgr.h"
-#include "llvm/Target/TargetAsmLexer.h"
-#include "llvm/Target/TargetAsmParser.h"
-#include "llvm/Target/TargetRegistry.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSelect.h"
-
-using namespace llvm;
-
-bool EDDisassembler::sInitialized = false;
-EDDisassembler::DisassemblerMap_t EDDisassembler::sDisassemblers;
-
-struct TripleMap {
- Triple::ArchType Arch;
- const char *String;
-};
-
-static struct TripleMap triplemap[] = {
- { Triple::x86, "i386-unknown-unknown" },
- { Triple::x86_64, "x86_64-unknown-unknown" },
- { Triple::arm, "arm-unknown-unknown" },
- { Triple::thumb, "thumb-unknown-unknown" },
- { Triple::InvalidArch, NULL, }
-};
-
-/// infoFromArch - Returns the TripleMap corresponding to a given architecture,
-/// or NULL if there is an error
-///
-/// @arg arch - The Triple::ArchType for the desired architecture
-static const char *tripleFromArch(Triple::ArchType arch) {
- unsigned int infoIndex;
-
- for (infoIndex = 0; triplemap[infoIndex].String != NULL; ++infoIndex) {
- if (arch == triplemap[infoIndex].Arch)
- return triplemap[infoIndex].String;
- }
-
- return NULL;
-}
-
-/// getLLVMSyntaxVariant - gets the constant to use to get an assembly printer
-/// for the desired assembly syntax, suitable for passing to
-/// Target::createMCInstPrinter()
-///
-/// @arg arch - The target architecture
-/// @arg syntax - The assembly syntax in sd form
-static int getLLVMSyntaxVariant(Triple::ArchType arch,
- EDAssemblySyntax_t syntax) {
- switch (syntax) {
- default:
- return -1;
- // Mappings below from X86AsmPrinter.cpp
- case kEDAssemblySyntaxX86ATT:
- if (arch == Triple::x86 || arch == Triple::x86_64)
- return 0;
- else
- return -1;
- case kEDAssemblySyntaxX86Intel:
- if (arch == Triple::x86 || arch == Triple::x86_64)
- return 1;
- else
- return -1;
- case kEDAssemblySyntaxARMUAL:
- if (arch == Triple::arm || arch == Triple::thumb)
- return 0;
- else
- return -1;
- }
-}
-
-void EDDisassembler::initialize() {
- if (sInitialized)
- return;
-
- sInitialized = true;
-
- InitializeAllTargetInfos();
- InitializeAllTargets();
- InitializeAllAsmPrinters();
- InitializeAllAsmParsers();
- InitializeAllDisassemblers();
-}
-
-#undef BRINGUP_TARGET
-
-EDDisassembler *EDDisassembler::getDisassembler(Triple::ArchType arch,
- EDAssemblySyntax_t syntax) {
- CPUKey key;
- key.Arch = arch;
- key.Syntax = syntax;
-
- EDDisassembler::DisassemblerMap_t::iterator i = sDisassemblers.find(key);
-
- if (i != sDisassemblers.end()) {
- return i->second;
- } else {
- EDDisassembler* sdd = new EDDisassembler(key);
- if (!sdd->valid()) {
- delete sdd;
- return NULL;
- }
-
- sDisassemblers[key] = sdd;
-
- return sdd;
- }
-
- return NULL;
-}
-
-EDDisassembler *EDDisassembler::getDisassembler(StringRef str,
- EDAssemblySyntax_t syntax) {
- Triple triple(str);
-
- return getDisassembler(triple.getArch(), syntax);
-}
-
-EDDisassembler::EDDisassembler(CPUKey &key) :
- Valid(false),
- HasSemantics(false),
- ErrorStream(nulls()),
- Key(key) {
- const char *triple = tripleFromArch(key.Arch);
-
- if (!triple)
- return;
-
- LLVMSyntaxVariant = getLLVMSyntaxVariant(key.Arch, key.Syntax);
-
- if (LLVMSyntaxVariant < 0)
- return;
-
- std::string tripleString(triple);
- std::string errorString;
-
- Tgt = TargetRegistry::lookupTarget(tripleString,
- errorString);
-
- if (!Tgt)
- return;
-
- std::string featureString;
-
- OwningPtr<const TargetMachine>
- targetMachine(Tgt->createTargetMachine(tripleString,
- featureString));
-
- const TargetRegisterInfo *registerInfo = targetMachine->getRegisterInfo();
-
- if (!registerInfo)
- return;
-
- initMaps(*registerInfo);
-
- AsmInfo.reset(Tgt->createAsmInfo(tripleString));
-
- if (!AsmInfo)
- return;
-
- Disassembler.reset(Tgt->createMCDisassembler());
-
- if (!Disassembler)
- return;
-
- InstInfos = Disassembler->getEDInfo();
-
- InstString.reset(new std::string);
- InstStream.reset(new raw_string_ostream(*InstString));
- InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo));
-
- if (!InstPrinter)
- return;
-
- GenericAsmLexer.reset(new AsmLexer(*AsmInfo));
- SpecificAsmLexer.reset(Tgt->createAsmLexer(*AsmInfo));
- SpecificAsmLexer->InstallLexer(*GenericAsmLexer);
-
- initMaps(*targetMachine->getRegisterInfo());
-
- Valid = true;
-}
-
-EDDisassembler::~EDDisassembler() {
- if (!valid())
- return;
-}
-
-namespace {
- /// EDMemoryObject - a subclass of MemoryObject that allows use of a callback
- /// as provided by the sd interface. See MemoryObject.
- class EDMemoryObject : public llvm::MemoryObject {
- private:
- EDByteReaderCallback Callback;
- void *Arg;
- public:
- EDMemoryObject(EDByteReaderCallback callback,
- void *arg) : Callback(callback), Arg(arg) { }
- ~EDMemoryObject() { }
- uint64_t getBase() const { return 0x0; }
- uint64_t getExtent() const { return (uint64_t)-1; }
- int readByte(uint64_t address, uint8_t *ptr) const {
- if (!Callback)
- return -1;
-
- if (Callback(ptr, address, Arg))
- return -1;
-
- return 0;
- }
- };
-}
-
-EDInst *EDDisassembler::createInst(EDByteReaderCallback byteReader,
- uint64_t address,
- void *arg) {
- EDMemoryObject memoryObject(byteReader, arg);
-
- MCInst* inst = new MCInst;
- uint64_t byteSize;
-
- if (!Disassembler->getInstruction(*inst,
- byteSize,
- memoryObject,
- address,
- ErrorStream)) {
- delete inst;
- return NULL;
- } else {
- const llvm::EDInstInfo *thisInstInfo;
-
- thisInstInfo = &InstInfos[inst->getOpcode()];
-
- EDInst* sdInst = new EDInst(inst, byteSize, *this, thisInstInfo);
- return sdInst;
- }
-}
-
-void EDDisassembler::initMaps(const TargetRegisterInfo ®isterInfo) {
- unsigned numRegisters = registerInfo.getNumRegs();
- unsigned registerIndex;
-
- for (registerIndex = 0; registerIndex < numRegisters; ++registerIndex) {
- const char* registerName = registerInfo.get(registerIndex).Name;
-
- RegVec.push_back(registerName);
- RegRMap[registerName] = registerIndex;
- }
-
- switch (Key.Arch) {
- default:
- break;
- case Triple::x86:
- case Triple::x86_64:
- stackPointers.insert(registerIDWithName("SP"));
- stackPointers.insert(registerIDWithName("ESP"));
- stackPointers.insert(registerIDWithName("RSP"));
-
- programCounters.insert(registerIDWithName("IP"));
- programCounters.insert(registerIDWithName("EIP"));
- programCounters.insert(registerIDWithName("RIP"));
- break;
- case Triple::arm:
- case Triple::thumb:
- stackPointers.insert(registerIDWithName("SP"));
-
- programCounters.insert(registerIDWithName("PC"));
- break;
- }
-}
-
-const char *EDDisassembler::nameWithRegisterID(unsigned registerID) const {
- if (registerID >= RegVec.size())
- return NULL;
- else
- return RegVec[registerID].c_str();
-}
-
-unsigned EDDisassembler::registerIDWithName(const char *name) const {
- regrmap_t::const_iterator iter = RegRMap.find(std::string(name));
- if (iter == RegRMap.end())
- return 0;
- else
- return (*iter).second;
-}
-
-bool EDDisassembler::registerIsStackPointer(unsigned registerID) {
- return (stackPointers.find(registerID) != stackPointers.end());
-}
-
-bool EDDisassembler::registerIsProgramCounter(unsigned registerID) {
- return (programCounters.find(registerID) != programCounters.end());
-}
-
-int EDDisassembler::printInst(std::string &str, MCInst &inst) {
- PrinterMutex.acquire();
-
- InstPrinter->printInst(&inst, *InstStream);
- InstStream->flush();
- str = *InstString;
- InstString->clear();
-
- PrinterMutex.release();
-
- return 0;
-}
-
-int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands,
- SmallVectorImpl<AsmToken> &tokens,
- const std::string &str) {
- int ret = 0;
-
- switch (Key.Arch) {
- default:
- return -1;
- case Triple::x86:
- case Triple::x86_64:
- case Triple::arm:
- case Triple::thumb:
- break;
- }
-
- const char *cStr = str.c_str();
- MemoryBuffer *buf = MemoryBuffer::getMemBuffer(cStr, cStr + strlen(cStr));
-
- StringRef instName;
- SMLoc instLoc;
-
- SourceMgr sourceMgr;
- sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
- MCContext context(*AsmInfo);
- OwningPtr<MCStreamer> streamer(createNullStreamer(context));
- AsmParser genericParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo);
- OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(genericParser));
-
- AsmToken OpcodeToken = genericParser.Lex();
- AsmToken NextToken = genericParser.Lex(); // consume next token, because specificParser expects us to
-
- if (OpcodeToken.is(AsmToken::Identifier)) {
- instName = OpcodeToken.getString();
- instLoc = OpcodeToken.getLoc();
-
- if (NextToken.isNot(AsmToken::Eof) &&
- TargetParser->ParseInstruction(instName, instLoc, operands))
- ret = -1;
- } else {
- ret = -1;
- }
-
- ParserMutex.acquire();
-
- if (!ret) {
- GenericAsmLexer->setBuffer(buf);
-
- while (SpecificAsmLexer->Lex(),
- SpecificAsmLexer->isNot(AsmToken::Eof) &&
- SpecificAsmLexer->isNot(AsmToken::EndOfStatement)) {
- if (SpecificAsmLexer->is(AsmToken::Error)) {
- ret = -1;
- break;
- }
- tokens.push_back(SpecificAsmLexer->getTok());
- }
- }
-
- ParserMutex.release();
-
- return ret;
-}
-
-int EDDisassembler::llvmSyntaxVariant() const {
- return LLVMSyntaxVariant;
-}
Removed: llvm/branches/wendling/eh/tools/edis/EDDisassembler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDDisassembler.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDDisassembler.h (original)
+++ llvm/branches/wendling/eh/tools/edis/EDDisassembler.h (removed)
@@ -1,256 +0,0 @@
-//===-EDDisassembler.h - LLVM Enhanced Disassembler -------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interface for the Enhanced Disassembly library's
-// disassembler class. The disassembler is responsible for vending individual
-// instructions according to a given architecture and disassembly syntax.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef EDDisassembler_
-#define EDDisassembler_
-
-#include "EDInfo.inc"
-
-#include "llvm-c/EnhancedDisassembly.h"
-
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/System/Mutex.h"
-
-#include <map>
-#include <set>
-#include <string>
-#include <vector>
-
-namespace llvm {
-class AsmLexer;
-class AsmToken;
-class MCContext;
-class MCAsmInfo;
-class MCAsmLexer;
-class AsmParser;
-class TargetAsmLexer;
-class TargetAsmParser;
-class MCDisassembler;
-class MCInstPrinter;
-class MCInst;
-class MCParsedAsmOperand;
-class MCStreamer;
-template <typename T> class SmallVectorImpl;
-class SourceMgr;
-class Target;
-class TargetRegisterInfo;
-
-struct EDInstInfo;
-}
-
-/// EDDisassembler - Encapsulates a disassembler for a single architecture and
-/// disassembly syntax. Also manages the static disassembler registry.
-struct EDDisassembler {
- ////////////////////
- // Static members //
- ////////////////////
-
- /// CPUKey - Encapsulates the descriptor of an architecture/disassembly-syntax
- /// pair
- struct CPUKey {
- /// The architecture type
- llvm::Triple::ArchType Arch;
-
- /// The assembly syntax
- EDAssemblySyntax_t Syntax;
-
- /// operator== - Equality operator
- bool operator==(const CPUKey &key) const {
- return (Arch == key.Arch &&
- Syntax == key.Syntax);
- }
-
- /// operator< - Less-than operator
- bool operator<(const CPUKey &key) const {
- if(Arch > key.Arch)
- return false;
- if(Syntax >= key.Syntax)
- return false;
- return true;
- }
- };
-
- typedef std::map<CPUKey, EDDisassembler*> DisassemblerMap_t;
-
- /// True if the disassembler registry has been initialized; false if not
- static bool sInitialized;
- /// A map from disassembler specifications to disassemblers. Populated
- /// lazily.
- static DisassemblerMap_t sDisassemblers;
-
- /// getDisassembler - Returns the specified disassemble, or NULL on failure
- ///
- /// @arg arch - The desired architecture
- /// @arg syntax - The desired disassembly syntax
- static EDDisassembler *getDisassembler(llvm::Triple::ArchType arch,
- EDAssemblySyntax_t syntax);
-
- /// getDisassembler - Returns the disassembler for a given combination of
- /// CPU type, CPU subtype, and assembly syntax, or NULL on failure
- ///
- /// @arg str - The string representation of the architecture triple, e.g.,
- /// "x86_64-apple-darwin"
- /// @arg syntax - The disassembly syntax for the required disassembler
- static EDDisassembler *getDisassembler(llvm::StringRef str,
- EDAssemblySyntax_t syntax);
-
- /// initialize - Initializes the disassembler registry and the LLVM backend
- static void initialize();
-
- ////////////////////////
- // Per-object members //
- ////////////////////////
-
- /// True only if the object has been successfully initialized
- bool Valid;
- /// True if the disassembler can provide semantic information
- bool HasSemantics;
-
- /// The stream to write errors to
- llvm::raw_ostream &ErrorStream;
-
- /// The architecture/syntax pair for the current architecture
- CPUKey Key;
- /// The LLVM target corresponding to the disassembler
- const llvm::Target *Tgt;
- /// The assembly information for the target architecture
- llvm::OwningPtr<const llvm::MCAsmInfo> AsmInfo;
- /// The disassembler for the target architecture
- llvm::OwningPtr<const llvm::MCDisassembler> Disassembler;
- /// The output string for the instruction printer; must be guarded with
- /// PrinterMutex
- llvm::OwningPtr<std::string> InstString;
- /// The output stream for the disassembler; must be guarded with
- /// PrinterMutex
- llvm::OwningPtr<llvm::raw_string_ostream> InstStream;
- /// The instruction printer for the target architecture; must be guarded with
- /// PrinterMutex when printing
- llvm::OwningPtr<llvm::MCInstPrinter> InstPrinter;
- /// The mutex that guards the instruction printer's printing functions, which
- /// use a shared stream
- llvm::sys::Mutex PrinterMutex;
- /// The array of instruction information provided by the TableGen backend for
- /// the target architecture
- const llvm::EDInstInfo *InstInfos;
- /// The target-specific lexer for use in tokenizing strings, in
- /// target-independent and target-specific portions
- llvm::OwningPtr<llvm::AsmLexer> GenericAsmLexer;
- llvm::OwningPtr<llvm::TargetAsmLexer> SpecificAsmLexer;
- /// The guard for the above
- llvm::sys::Mutex ParserMutex;
- /// The LLVM number used for the target disassembly syntax variant
- int LLVMSyntaxVariant;
-
- typedef std::vector<std::string> regvec_t;
- typedef std::map<std::string, unsigned> regrmap_t;
-
- /// A vector of registers for quick mapping from LLVM register IDs to names
- regvec_t RegVec;
- /// A map of registers for quick mapping from register names to LLVM IDs
- regrmap_t RegRMap;
-
- /// A set of register IDs for aliases of the stack pointer for the current
- /// architecture
- std::set<unsigned> stackPointers;
- /// A set of register IDs for aliases of the program counter for the current
- /// architecture
- std::set<unsigned> programCounters;
-
- /// Constructor - initializes a disassembler with all the necessary objects,
- /// which come pre-allocated from the registry accessor function
- ///
- /// @arg key - the architecture and disassembly syntax for the
- /// disassembler
- EDDisassembler(CPUKey& key);
-
- /// valid - reports whether there was a failure in the constructor.
- bool valid() {
- return Valid;
- }
-
- /// hasSemantics - reports whether the disassembler can provide operands and
- /// tokens.
- bool hasSemantics() {
- return HasSemantics;
- }
-
- ~EDDisassembler();
-
- /// createInst - creates and returns an instruction given a callback and
- /// memory address, or NULL on failure
- ///
- /// @arg byteReader - A callback function that provides machine code bytes
- /// @arg address - The address of the first byte of the instruction,
- /// suitable for passing to byteReader
- /// @arg arg - An opaque argument for byteReader
- EDInst *createInst(EDByteReaderCallback byteReader,
- uint64_t address,
- void *arg);
-
- /// initMaps - initializes regVec and regRMap using the provided register
- /// info
- ///
- /// @arg registerInfo - the register information to use as a source
- void initMaps(const llvm::TargetRegisterInfo ®isterInfo);
- /// nameWithRegisterID - Returns the name (owned by the EDDisassembler) of a
- /// register for a given register ID, or NULL on failure
- ///
- /// @arg registerID - the ID of the register to be queried
- const char *nameWithRegisterID(unsigned registerID) const;
- /// registerIDWithName - Returns the ID of a register for a given register
- /// name, or (unsigned)-1 on failure
- ///
- /// @arg name - The name of the register
- unsigned registerIDWithName(const char *name) const;
-
- /// registerIsStackPointer - reports whether a register ID is an alias for the
- /// stack pointer register
- ///
- /// @arg registerID - The LLVM register ID
- bool registerIsStackPointer(unsigned registerID);
- /// registerIsStackPointer - reports whether a register ID is an alias for the
- /// stack pointer register
- ///
- /// @arg registerID - The LLVM register ID
- bool registerIsProgramCounter(unsigned registerID);
-
- /// printInst - prints an MCInst to a string, returning 0 on success, or -1
- /// otherwise
- ///
- /// @arg str - A reference to a string which is filled in with the string
- /// representation of the instruction
- /// @arg inst - A reference to the MCInst to be printed
- int printInst(std::string& str,
- llvm::MCInst& inst);
-
- /// parseInst - extracts operands and tokens from a string for use in
- /// tokenizing the string. Returns 0 on success, or -1 otherwise.
- ///
- /// @arg operands - A reference to a vector that will be filled in with the
- /// parsed operands
- /// @arg tokens - A reference to a vector that will be filled in with the
- /// tokens
- /// @arg str - The string representation of the instruction
- int parseInst(llvm::SmallVectorImpl<llvm::MCParsedAsmOperand*> &operands,
- llvm::SmallVectorImpl<llvm::AsmToken> &tokens,
- const std::string &str);
-
- /// llvmSyntaxVariant - returns the LLVM syntax variant for this disassembler
- int llvmSyntaxVariant() const;
-};
-
-#endif
Removed: llvm/branches/wendling/eh/tools/edis/EDInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDInfo.td?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDInfo.td (original)
+++ llvm/branches/wendling/eh/tools/edis/EDInfo.td (removed)
@@ -1 +0,0 @@
-// Intentionally empty.
Removed: llvm/branches/wendling/eh/tools/edis/EDInst.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDInst.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDInst.cpp (original)
+++ llvm/branches/wendling/eh/tools/edis/EDInst.cpp (removed)
@@ -1,207 +0,0 @@
-//===-EDInst.cpp - LLVM Enhanced Disassembler -----------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the Enhanced Disassembly library's instruction class.
-// The instruction is responsible for vending the string representation,
-// individual tokens, and operands for a single instruction.
-//
-//===----------------------------------------------------------------------===//
-
-#include "EDDisassembler.h"
-#include "EDInst.h"
-#include "EDOperand.h"
-#include "EDToken.h"
-
-#include "llvm/MC/EDInstInfo.h"
-#include "llvm/MC/MCInst.h"
-
-using namespace llvm;
-
-EDInst::EDInst(llvm::MCInst *inst,
- uint64_t byteSize,
- EDDisassembler &disassembler,
- const llvm::EDInstInfo *info) :
- Disassembler(disassembler),
- Inst(inst),
- ThisInstInfo(info),
- ByteSize(byteSize),
- BranchTarget(-1),
- MoveSource(-1),
- MoveTarget(-1) {
- OperandOrder = ThisInstInfo->operandOrders[Disassembler.llvmSyntaxVariant()];
-}
-
-EDInst::~EDInst() {
- unsigned int index;
- unsigned int numOperands = Operands.size();
-
- for (index = 0; index < numOperands; ++index)
- delete Operands[index];
-
- unsigned int numTokens = Tokens.size();
-
- for (index = 0; index < numTokens; ++index)
- delete Tokens[index];
-
- delete Inst;
-}
-
-uint64_t EDInst::byteSize() {
- return ByteSize;
-}
-
-int EDInst::stringify() {
- if (StringifyResult.valid())
- return StringifyResult.result();
-
- if (Disassembler.printInst(String, *Inst))
- return StringifyResult.setResult(-1);
-
- return StringifyResult.setResult(0);
-}
-
-int EDInst::getString(const char*& str) {
- if (stringify())
- return -1;
-
- str = String.c_str();
-
- return 0;
-}
-
-unsigned EDInst::instID() {
- return Inst->getOpcode();
-}
-
-bool EDInst::isBranch() {
- if (ThisInstInfo)
- return
- ThisInstInfo->instructionType == kInstructionTypeBranch ||
- ThisInstInfo->instructionType == kInstructionTypeCall;
- else
- return false;
-}
-
-bool EDInst::isMove() {
- if (ThisInstInfo)
- return ThisInstInfo->instructionType == kInstructionTypeMove;
- else
- return false;
-}
-
-int EDInst::parseOperands() {
- if (ParseResult.valid())
- return ParseResult.result();
-
- if (!ThisInstInfo)
- return ParseResult.setResult(-1);
-
- unsigned int opIndex;
- unsigned int mcOpIndex = 0;
-
- for (opIndex = 0; opIndex < ThisInstInfo->numOperands; ++opIndex) {
- if (isBranch() &&
- (ThisInstInfo->operandFlags[opIndex] & kOperandFlagTarget)) {
- BranchTarget = opIndex;
- }
- else if (isMove()) {
- if (ThisInstInfo->operandFlags[opIndex] & kOperandFlagSource)
- MoveSource = opIndex;
- else if (ThisInstInfo->operandFlags[opIndex] & kOperandFlagTarget)
- MoveTarget = opIndex;
- }
-
- EDOperand *operand = new EDOperand(Disassembler, *this, opIndex, mcOpIndex);
-
- Operands.push_back(operand);
- }
-
- return ParseResult.setResult(0);
-}
-
-int EDInst::branchTargetID() {
- if (parseOperands())
- return -1;
- return BranchTarget;
-}
-
-int EDInst::moveSourceID() {
- if (parseOperands())
- return -1;
- return MoveSource;
-}
-
-int EDInst::moveTargetID() {
- if (parseOperands())
- return -1;
- return MoveTarget;
-}
-
-int EDInst::numOperands() {
- if (parseOperands())
- return -1;
- return Operands.size();
-}
-
-int EDInst::getOperand(EDOperand *&operand, unsigned int index) {
- if (parseOperands())
- return -1;
-
- if (index >= Operands.size())
- return -1;
-
- operand = Operands[index];
- return 0;
-}
-
-int EDInst::tokenize() {
- if (TokenizeResult.valid())
- return TokenizeResult.result();
-
- if (stringify())
- return TokenizeResult.setResult(-1);
-
- return TokenizeResult.setResult(EDToken::tokenize(Tokens,
- String,
- OperandOrder,
- Disassembler));
-
-}
-
-int EDInst::numTokens() {
- if (tokenize())
- return -1;
- return Tokens.size();
-}
-
-int EDInst::getToken(EDToken *&token, unsigned int index) {
- if (tokenize())
- return -1;
- token = Tokens[index];
- return 0;
-}
-
-#ifdef __BLOCKS__
-int EDInst::visitTokens(EDTokenVisitor_t visitor) {
- if (tokenize())
- return -1;
-
- tokvec_t::iterator iter;
-
- for (iter = Tokens.begin(); iter != Tokens.end(); ++iter) {
- int ret = visitor(*iter);
- if (ret == 1)
- return 0;
- if (ret != 0)
- return -1;
- }
-
- return 0;
-}
-#endif
Removed: llvm/branches/wendling/eh/tools/edis/EDInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDInst.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDInst.h (original)
+++ llvm/branches/wendling/eh/tools/edis/EDInst.h (removed)
@@ -1,175 +0,0 @@
-//===-EDInst.h - LLVM Enhanced Disassembler ---------------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interface for the Enhanced Disassembly library's
-// instruction class. The instruction is responsible for vending the string
-// representation, individual tokens and operands for a single instruction.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef EDInst_
-#define EDInst_
-
-#include "llvm-c/EnhancedDisassembly.h"
-
-#include "llvm/ADT/SmallVector.h"
-
-#include <string>
-#include <vector>
-
-namespace llvm {
- struct EDInstInfo;
-}
-
-/// CachedResult - Encapsulates the result of a function along with the validity
-/// of that result, so that slow functions don't need to run twice
-struct CachedResult {
- /// True if the result has been obtained by executing the function
- bool Valid;
- /// The result last obtained from the function
- int Result;
-
- /// Constructor - Initializes an invalid result
- CachedResult() : Valid(false) { }
- /// valid - Returns true if the result has been obtained by executing the
- /// function and false otherwise
- bool valid() { return Valid; }
- /// result - Returns the result of the function or an undefined value if
- /// valid() is false
- int result() { return Result; }
- /// setResult - Sets the result of the function and declares it valid
- /// returning the result (so that setResult() can be called from inside a
- /// return statement)
- /// @arg result - The result of the function
- int setResult(int result) { Result = result; Valid = true; return result; }
-};
-
-/// EDInst - Encapsulates a single instruction, which can be queried for its
-/// string representation, as well as its operands and tokens
-struct EDInst {
- /// The parent disassembler
- EDDisassembler &Disassembler;
- /// The containing MCInst
- llvm::MCInst *Inst;
- /// The instruction information provided by TableGen for this instruction
- const llvm::EDInstInfo *ThisInstInfo;
- /// The number of bytes for the machine code representation of the instruction
- uint64_t ByteSize;
-
- /// The result of the stringify() function
- CachedResult StringifyResult;
- /// The string representation of the instruction
- std::string String;
- /// The order in which operands from the InstInfo's operand information appear
- /// in String
- const char* OperandOrder;
-
- /// The result of the parseOperands() function
- CachedResult ParseResult;
- typedef llvm::SmallVector<EDOperand*, 5> opvec_t;
- /// The instruction's operands
- opvec_t Operands;
- /// The operand corresponding to the target, if the instruction is a branch
- int BranchTarget;
- /// The operand corresponding to the source, if the instruction is a move
- int MoveSource;
- /// The operand corresponding to the target, if the instruction is a move
- int MoveTarget;
-
- /// The result of the tokenize() function
- CachedResult TokenizeResult;
- typedef std::vector<EDToken*> tokvec_t;
- /// The instruction's tokens
- tokvec_t Tokens;
-
- /// Constructor - initializes an instruction given the output of the LLVM
- /// C++ disassembler
- ///
- /// @arg inst - The MCInst, which will now be owned by this object
- /// @arg byteSize - The size of the consumed instruction, in bytes
- /// @arg disassembler - The parent disassembler
- /// @arg instInfo - The instruction information produced by the table
- /// generator for this instruction
- EDInst(llvm::MCInst *inst,
- uint64_t byteSize,
- EDDisassembler &disassembler,
- const llvm::EDInstInfo *instInfo);
- ~EDInst();
-
- /// byteSize - returns the number of bytes consumed by the machine code
- /// representation of the instruction
- uint64_t byteSize();
- /// instID - returns the LLVM instruction ID of the instruction
- unsigned instID();
-
- /// stringify - populates the String and AsmString members of the instruction,
- /// returning 0 on success or -1 otherwise
- int stringify();
- /// getString - retrieves a pointer to the string representation of the
- /// instructinon, returning 0 on success or -1 otherwise
- ///
- /// @arg str - A reference to a pointer that, on success, is set to point to
- /// the string representation of the instruction; this string is still owned
- /// by the instruction and will be deleted when it is
- int getString(const char *&str);
-
- /// isBranch - Returns true if the instruction is a branch
- bool isBranch();
- /// isMove - Returns true if the instruction is a move
- bool isMove();
-
- /// parseOperands - populates the Operands member of the instruction,
- /// returning 0 on success or -1 otherwise
- int parseOperands();
- /// branchTargetID - returns the ID (suitable for use with getOperand()) of
- /// the target operand if the instruction is a branch, or -1 otherwise
- int branchTargetID();
- /// moveSourceID - returns the ID of the source operand if the instruction
- /// is a move, or -1 otherwise
- int moveSourceID();
- /// moveTargetID - returns the ID of the target operand if the instruction
- /// is a move, or -1 otherwise
- int moveTargetID();
-
- /// numOperands - returns the number of operands available to retrieve, or -1
- /// on error
- int numOperands();
- /// getOperand - retrieves an operand from the instruction's operand list by
- /// index, returning 0 on success or -1 on error
- ///
- /// @arg operand - A reference whose target is pointed at the operand on
- /// success, although the operand is still owned by the EDInst
- /// @arg index - The index of the operand in the instruction
- int getOperand(EDOperand *&operand, unsigned int index);
-
- /// tokenize - populates the Tokens member of the instruction, returning 0 on
- /// success or -1 otherwise
- int tokenize();
- /// numTokens - returns the number of tokens in the instruction, or -1 on
- /// error
- int numTokens();
- /// getToken - retrieves a token from the instruction's token list by index,
- /// returning 0 on success or -1 on error
- ///
- /// @arg token - A reference whose target is pointed at the token on success,
- /// although the token is still owned by the EDInst
- /// @arg index - The index of the token in the instrcutino
- int getToken(EDToken *&token, unsigned int index);
-
-#ifdef __BLOCKS__
- /// visitTokens - Visits each token in turn and applies a block to it,
- /// returning 0 if all blocks are visited and/or the block signals
- /// termination by returning 1; returns -1 on error
- ///
- /// @arg visitor - The visitor block to apply to all tokens.
- int visitTokens(EDTokenVisitor_t visitor);
-#endif
-};
-
-#endif
Modified: llvm/branches/wendling/eh/tools/edis/EDMain.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDMain.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDMain.cpp (original)
+++ llvm/branches/wendling/eh/tools/edis/EDMain.cpp Sat Jul 31 19:59:02 2010
@@ -1,4 +1,4 @@
-//===-EDMain.cpp - LLVM Enhanced Disassembly C API ------------------------===//
+//===-- EDMain.cpp - LLVM Enhanced Disassembly C API ----------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,33 +11,46 @@
//
//===----------------------------------------------------------------------===//
-#include "EDDisassembler.h"
-#include "EDInst.h"
-#include "EDOperand.h"
-#include "EDToken.h"
-
+// FIXME: This code isn't layered right, the headers should be moved to
+// include llvm/MC/MCDisassembler or something.
+#include "../../lib/MC/MCDisassembler/EDDisassembler.h"
+#include "../../lib/MC/MCDisassembler/EDInst.h"
+#include "../../lib/MC/MCDisassembler/EDOperand.h"
+#include "../../lib/MC/MCDisassembler/EDToken.h"
#include "llvm-c/EnhancedDisassembly.h"
+using namespace llvm;
int EDGetDisassembler(EDDisassemblerRef *disassembler,
const char *triple,
EDAssemblySyntax_t syntax) {
EDDisassembler::initialize();
- EDDisassemblerRef ret = EDDisassembler::getDisassembler(triple,
- syntax);
+ EDDisassembler::AssemblySyntax Syntax;
+ switch (syntax) {
+ default: assert(0 && "Unknown assembly syntax!");
+ case kEDAssemblySyntaxX86Intel:
+ Syntax = EDDisassembler::kEDAssemblySyntaxX86Intel;
+ break;
+ case kEDAssemblySyntaxX86ATT:
+ Syntax = EDDisassembler::kEDAssemblySyntaxX86ATT;
+ break;
+ case kEDAssemblySyntaxARMUAL:
+ Syntax = EDDisassembler::kEDAssemblySyntaxARMUAL;
+ break;
+ }
+
+ EDDisassemblerRef ret = EDDisassembler::getDisassembler(triple, Syntax);
- if (ret) {
- *disassembler = ret;
- return 0;
- } else {
+ if (!ret)
return -1;
- }
+ *disassembler = ret;
+ return 0;
}
int EDGetRegisterName(const char** regName,
EDDisassemblerRef disassembler,
unsigned regID) {
- const char* name = disassembler->nameWithRegisterID(regID);
+ const char *name = ((EDDisassembler*)disassembler)->nameWithRegisterID(regID);
if (!name)
return -1;
*regName = name;
@@ -46,24 +59,25 @@
int EDRegisterIsStackPointer(EDDisassemblerRef disassembler,
unsigned regID) {
- return disassembler->registerIsStackPointer(regID) ? 1 : 0;
+ return ((EDDisassembler*)disassembler)->registerIsStackPointer(regID) ? 1 : 0;
}
int EDRegisterIsProgramCounter(EDDisassemblerRef disassembler,
unsigned regID) {
- return disassembler->registerIsProgramCounter(regID) ? 1 : 0;
+ return ((EDDisassembler*)disassembler)->registerIsProgramCounter(regID) ? 1:0;
}
unsigned int EDCreateInsts(EDInstRef *insts,
unsigned int count,
EDDisassemblerRef disassembler,
- EDByteReaderCallback byteReader,
+ ::EDByteReaderCallback byteReader,
uint64_t address,
void *arg) {
unsigned int index;
for (index = 0; index < count; ++index) {
- EDInst *inst = disassembler->createInst(byteReader, address, arg);
+ EDInst *inst = ((EDDisassembler*)disassembler)->createInst(byteReader,
+ address, arg);
if (!inst)
return index;
@@ -76,163 +90,143 @@
}
void EDReleaseInst(EDInstRef inst) {
- delete inst;
+ delete ((EDInst*)inst);
}
int EDInstByteSize(EDInstRef inst) {
- return inst->byteSize();
+ return ((EDInst*)inst)->byteSize();
}
int EDGetInstString(const char **buf,
EDInstRef inst) {
- return inst->getString(*buf);
+ return ((EDInst*)inst)->getString(*buf);
}
int EDInstID(unsigned *instID, EDInstRef inst) {
- *instID = inst->instID();
+ *instID = ((EDInst*)inst)->instID();
return 0;
}
int EDInstIsBranch(EDInstRef inst) {
- return inst->isBranch();
+ return ((EDInst*)inst)->isBranch();
}
int EDInstIsMove(EDInstRef inst) {
- return inst->isMove();
+ return ((EDInst*)inst)->isMove();
}
int EDBranchTargetID(EDInstRef inst) {
- return inst->branchTargetID();
+ return ((EDInst*)inst)->branchTargetID();
}
int EDMoveSourceID(EDInstRef inst) {
- return inst->moveSourceID();
+ return ((EDInst*)inst)->moveSourceID();
}
int EDMoveTargetID(EDInstRef inst) {
- return inst->moveTargetID();
+ return ((EDInst*)inst)->moveTargetID();
}
int EDNumTokens(EDInstRef inst) {
- return inst->numTokens();
+ return ((EDInst*)inst)->numTokens();
}
int EDGetToken(EDTokenRef *token,
EDInstRef inst,
int index) {
- return inst->getToken(*token, index);
+ return ((EDInst*)inst)->getToken(*(EDToken**)token, index);
}
int EDGetTokenString(const char **buf,
EDTokenRef token) {
- return token->getString(*buf);
+ return ((EDToken*)token)->getString(*buf);
}
int EDOperandIndexForToken(EDTokenRef token) {
- return token->operandID();
+ return ((EDToken*)token)->operandID();
}
int EDTokenIsWhitespace(EDTokenRef token) {
- if (token->type() == EDToken::kTokenWhitespace)
- return 1;
- else
- return 0;
+ return ((EDToken*)token)->type() == EDToken::kTokenWhitespace;
}
int EDTokenIsPunctuation(EDTokenRef token) {
- if (token->type() == EDToken::kTokenPunctuation)
- return 1;
- else
- return 0;
+ return ((EDToken*)token)->type() == EDToken::kTokenPunctuation;
}
int EDTokenIsOpcode(EDTokenRef token) {
- if (token->type() == EDToken::kTokenOpcode)
- return 1;
- else
- return 0;
+ return ((EDToken*)token)->type() == EDToken::kTokenOpcode;
}
int EDTokenIsLiteral(EDTokenRef token) {
- if (token->type() == EDToken::kTokenLiteral)
- return 1;
- else
- return 0;
+ return ((EDToken*)token)->type() == EDToken::kTokenLiteral;
}
int EDTokenIsRegister(EDTokenRef token) {
- if (token->type() == EDToken::kTokenRegister)
- return 1;
- else
- return 0;
+ return ((EDToken*)token)->type() == EDToken::kTokenRegister;
}
int EDTokenIsNegativeLiteral(EDTokenRef token) {
- if (token->type() != EDToken::kTokenLiteral)
+ if (((EDToken*)token)->type() != EDToken::kTokenLiteral)
return -1;
- return token->literalSign();
+ return ((EDToken*)token)->literalSign();
}
-int EDLiteralTokenAbsoluteValue(uint64_t *value,
- EDTokenRef token) {
- if (token->type() != EDToken::kTokenLiteral)
+int EDLiteralTokenAbsoluteValue(uint64_t *value, EDTokenRef token) {
+ if (((EDToken*)token)->type() != EDToken::kTokenLiteral)
return -1;
- return token->literalAbsoluteValue(*value);
+ return ((EDToken*)token)->literalAbsoluteValue(*value);
}
int EDRegisterTokenValue(unsigned *registerID,
EDTokenRef token) {
- if (token->type() != EDToken::kTokenRegister)
+ if (((EDToken*)token)->type() != EDToken::kTokenRegister)
return -1;
- return token->registerID(*registerID);
+ return ((EDToken*)token)->registerID(*registerID);
}
int EDNumOperands(EDInstRef inst) {
- return inst->numOperands();
+ return ((EDInst*)inst)->numOperands();
}
int EDGetOperand(EDOperandRef *operand,
EDInstRef inst,
int index) {
- return inst->getOperand(*operand, index);
+ return ((EDInst*)inst)->getOperand(*(EDOperand**)operand, index);
}
int EDOperandIsRegister(EDOperandRef operand) {
- return operand->isRegister();
+ return ((EDOperand*)operand)->isRegister();
}
int EDOperandIsImmediate(EDOperandRef operand) {
- return operand->isImmediate();
+ return ((EDOperand*)operand)->isImmediate();
}
int EDOperandIsMemory(EDOperandRef operand) {
- return operand->isMemory();
+ return ((EDOperand*)operand)->isMemory();
}
-int EDRegisterOperandValue(unsigned *value,
- EDOperandRef operand) {
- if (!operand->isRegister())
+int EDRegisterOperandValue(unsigned *value, EDOperandRef operand) {
+ if (!((EDOperand*)operand)->isRegister())
return -1;
- *value = operand->regVal();
+ *value = ((EDOperand*)operand)->regVal();
return 0;
}
-int EDImmediateOperandValue(uint64_t *value,
- EDOperandRef operand) {
- if (!operand->isImmediate())
+int EDImmediateOperandValue(uint64_t *value, EDOperandRef operand) {
+ if (!((EDOperand*)operand)->isImmediate())
return -1;
- *value = operand->immediateVal();
+ *value = ((EDOperand*)operand)->immediateVal();
return 0;
}
-int EDEvaluateOperand(uint64_t *result,
- EDOperandRef operand,
- EDRegisterReaderCallback regReader,
- void *arg) {
- return operand->evaluate(*result, regReader, arg);
+int EDEvaluateOperand(uint64_t *result, EDOperandRef operand,
+ ::EDRegisterReaderCallback regReader, void *arg) {
+ return ((EDOperand*)operand)->evaluate(*result, regReader, arg);
}
#ifdef __BLOCKS__
@@ -264,15 +258,13 @@
(void*)&wrapper);
}
-int EDBlockEvaluateOperand(uint64_t *result,
- EDOperandRef operand,
+int EDBlockEvaluateOperand(uint64_t *result, EDOperandRef operand,
EDRegisterBlock_t regBlock) {
- return operand->evaluate(*result, regBlock);
+ return ((EDOperand*)operand)->evaluate(*result, regBlock);
}
-int EDBlockVisitTokens(EDInstRef inst,
- EDTokenVisitor_t visitor) {
- return inst->visitTokens(visitor);
+int EDBlockVisitTokens(EDInstRef inst, ::EDTokenVisitor_t visitor) {
+ return ((EDInst*)inst)->visitTokens((llvm::EDTokenVisitor_t)visitor);
}
#else
Removed: llvm/branches/wendling/eh/tools/edis/EDOperand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDOperand.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDOperand.cpp (original)
+++ llvm/branches/wendling/eh/tools/edis/EDOperand.cpp (removed)
@@ -1,284 +0,0 @@
-//===-EDOperand.cpp - LLVM Enhanced Disassembler --------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the Enhanced Disassembly library's operand class. The
-// operand is responsible for allowing evaluation given a particular register
-// context.
-//
-//===----------------------------------------------------------------------===//
-
-#include "EDDisassembler.h"
-#include "EDInst.h"
-#include "EDOperand.h"
-
-#include "llvm/MC/EDInstInfo.h"
-#include "llvm/MC/MCInst.h"
-
-using namespace llvm;
-
-EDOperand::EDOperand(const EDDisassembler &disassembler,
- const EDInst &inst,
- unsigned int opIndex,
- unsigned int &mcOpIndex) :
- Disassembler(disassembler),
- Inst(inst),
- OpIndex(opIndex),
- MCOpIndex(mcOpIndex) {
- unsigned int numMCOperands = 0;
-
- if (Disassembler.Key.Arch == Triple::x86 ||
- Disassembler.Key.Arch == Triple::x86_64) {
- uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
-
- switch (operandType) {
- default:
- break;
- case kOperandTypeImmediate:
- numMCOperands = 1;
- break;
- case kOperandTypeRegister:
- numMCOperands = 1;
- break;
- case kOperandTypeX86Memory:
- numMCOperands = 5;
- break;
- case kOperandTypeX86EffectiveAddress:
- numMCOperands = 4;
- break;
- case kOperandTypeX86PCRelative:
- numMCOperands = 1;
- break;
- }
- }
- else if (Disassembler.Key.Arch == Triple::arm ||
- Disassembler.Key.Arch == Triple::thumb) {
- uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
-
- switch (operandType) {
- default:
- case kOperandTypeARMRegisterList:
- break;
- case kOperandTypeImmediate:
- case kOperandTypeRegister:
- case kOperandTypeARMBranchTarget:
- case kOperandTypeARMSoImm:
- case kOperandTypeThumb2SoImm:
- case kOperandTypeARMSoImm2Part:
- case kOperandTypeARMPredicate:
- case kOperandTypeThumbITMask:
- case kOperandTypeThumb2AddrModeImm8Offset:
- case kOperandTypeARMTBAddrMode:
- case kOperandTypeThumb2AddrModeImm8s4Offset:
- numMCOperands = 1;
- break;
- case kOperandTypeThumb2SoReg:
- case kOperandTypeARMAddrMode2Offset:
- case kOperandTypeARMAddrMode3Offset:
- case kOperandTypeARMAddrMode4:
- case kOperandTypeARMAddrMode5:
- case kOperandTypeARMAddrModePC:
- case kOperandTypeThumb2AddrModeImm8:
- case kOperandTypeThumb2AddrModeImm12:
- case kOperandTypeThumb2AddrModeImm8s4:
- case kOperandTypeThumbAddrModeRR:
- case kOperandTypeThumbAddrModeSP:
- numMCOperands = 2;
- break;
- case kOperandTypeARMSoReg:
- case kOperandTypeARMAddrMode2:
- case kOperandTypeARMAddrMode3:
- case kOperandTypeThumb2AddrModeSoReg:
- case kOperandTypeThumbAddrModeS1:
- case kOperandTypeThumbAddrModeS2:
- case kOperandTypeThumbAddrModeS4:
- case kOperandTypeARMAddrMode6Offset:
- numMCOperands = 3;
- break;
- case kOperandTypeARMAddrMode6:
- numMCOperands = 4;
- break;
- }
- }
-
- mcOpIndex += numMCOperands;
-}
-
-EDOperand::~EDOperand() {
-}
-
-int EDOperand::evaluate(uint64_t &result,
- EDRegisterReaderCallback callback,
- void *arg) {
- uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
-
- switch (Disassembler.Key.Arch) {
- default:
- return -1;
- case Triple::x86:
- case Triple::x86_64:
- switch (operandType) {
- default:
- return -1;
- case kOperandTypeImmediate:
- result = Inst.Inst->getOperand(MCOpIndex).getImm();
- return 0;
- case kOperandTypeRegister:
- {
- unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
- return callback(&result, reg, arg);
- }
- case kOperandTypeX86PCRelative:
- {
- int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
-
- uint64_t ripVal;
-
- // TODO fix how we do this
-
- if (callback(&ripVal, Disassembler.registerIDWithName("RIP"), arg))
- return -1;
-
- result = ripVal + displacement;
- return 0;
- }
- case kOperandTypeX86Memory:
- case kOperandTypeX86EffectiveAddress:
- {
- unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
- uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
- unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
- int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
- //unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
-
- uint64_t addr = 0;
-
- if (baseReg) {
- uint64_t baseVal;
- if (callback(&baseVal, baseReg, arg))
- return -1;
- addr += baseVal;
- }
-
- if (indexReg) {
- uint64_t indexVal;
- if (callback(&indexVal, indexReg, arg))
- return -1;
- addr += (scaleAmount * indexVal);
- }
-
- addr += displacement;
-
- result = addr;
- return 0;
- }
- }
- break;
- case Triple::arm:
- case Triple::thumb:
- switch (operandType) {
- default:
- return -1;
- case kOperandTypeImmediate:
- result = Inst.Inst->getOperand(MCOpIndex).getImm();
- return 0;
- case kOperandTypeRegister:
- {
- unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
- return callback(&result, reg, arg);
- }
- case kOperandTypeARMBranchTarget:
- {
- int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
-
- uint64_t pcVal;
-
- if (callback(&pcVal, Disassembler.registerIDWithName("PC"), arg))
- return -1;
-
- result = pcVal + displacement;
- return 0;
- }
- }
- }
-
- return -1;
-}
-
-int EDOperand::isRegister() {
- return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeRegister);
-}
-
-unsigned EDOperand::regVal() {
- return Inst.Inst->getOperand(MCOpIndex).getReg();
-}
-
-int EDOperand::isImmediate() {
- return(Inst.ThisInstInfo->operandFlags[OpIndex] == kOperandTypeImmediate);
-}
-
-uint64_t EDOperand::immediateVal() {
- return Inst.Inst->getOperand(MCOpIndex).getImm();
-}
-
-int EDOperand::isMemory() {
- uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
-
- switch (operandType) {
- default:
- return 0;
- case kOperandTypeX86Memory:
- case kOperandTypeX86PCRelative:
- case kOperandTypeX86EffectiveAddress:
- case kOperandTypeARMSoReg:
- case kOperandTypeARMSoImm:
- case kOperandTypeARMAddrMode2:
- case kOperandTypeARMAddrMode2Offset:
- case kOperandTypeARMAddrMode3:
- case kOperandTypeARMAddrMode3Offset:
- case kOperandTypeARMAddrMode4:
- case kOperandTypeARMAddrMode5:
- case kOperandTypeARMAddrMode6:
- case kOperandTypeARMAddrModePC:
- case kOperandTypeARMBranchTarget:
- case kOperandTypeThumbAddrModeS1:
- case kOperandTypeThumbAddrModeS2:
- case kOperandTypeThumbAddrModeS4:
- case kOperandTypeThumbAddrModeRR:
- case kOperandTypeThumbAddrModeSP:
- case kOperandTypeThumb2SoImm:
- case kOperandTypeThumb2AddrModeImm8:
- case kOperandTypeThumb2AddrModeImm8Offset:
- case kOperandTypeThumb2AddrModeImm12:
- case kOperandTypeThumb2AddrModeSoReg:
- case kOperandTypeThumb2AddrModeImm8s4:
- return 1;
- }
-}
-
-#ifdef __BLOCKS__
-struct RegisterReaderWrapper {
- EDRegisterBlock_t regBlock;
-};
-
-int readerWrapperCallback(uint64_t *value,
- unsigned regID,
- void *arg) {
- struct RegisterReaderWrapper *wrapper = (struct RegisterReaderWrapper *)arg;
- return wrapper->regBlock(value, regID);
-}
-
-int EDOperand::evaluate(uint64_t &result,
- EDRegisterBlock_t regBlock) {
- struct RegisterReaderWrapper wrapper;
- wrapper.regBlock = regBlock;
- return evaluate(result,
- readerWrapperCallback,
- (void*)&wrapper);
-}
-#endif
Removed: llvm/branches/wendling/eh/tools/edis/EDOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDOperand.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDOperand.h (original)
+++ llvm/branches/wendling/eh/tools/edis/EDOperand.h (removed)
@@ -1,78 +0,0 @@
-//===-EDOperand.h - LLVM Enhanced Disassembler ------------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interface for the Enhanced Disassembly library's
-// operand class. The operand is responsible for allowing evaluation given a
-// particular register context.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef EDOperand_
-#define EDOperand_
-
-#include "llvm-c/EnhancedDisassembly.h"
-
-/// EDOperand - Encapsulates a single operand, which can be evaluated by the
-/// client
-struct EDOperand {
- /// The parent disassembler
- const EDDisassembler &Disassembler;
- /// The parent instruction
- const EDInst &Inst;
-
- /// The index of the operand in the EDInst
- unsigned int OpIndex;
- /// The index of the first component of the operand in the MCInst
- unsigned int MCOpIndex;
-
- /// Constructor - Initializes an EDOperand
- ///
- /// @arg disassembler - The disassembler responsible for the operand
- /// @arg inst - The instruction containing this operand
- /// @arg opIndex - The index of the operand in inst
- /// @arg mcOpIndex - The index of the operand in the original MCInst
- EDOperand(const EDDisassembler &disassembler,
- const EDInst &inst,
- unsigned int opIndex,
- unsigned int &mcOpIndex);
- ~EDOperand();
-
- /// evaluate - Returns the numeric value of an operand to the extent possible,
- /// returning 0 on success or -1 if there was some problem (such as a
- /// register not being readable)
- ///
- /// @arg result - A reference whose target is filled in with the value of
- /// the operand (the address if it is a memory operand)
- /// @arg callback - A function to call to obtain register values
- /// @arg arg - An opaque argument to pass to callback
- int evaluate(uint64_t &result,
- EDRegisterReaderCallback callback,
- void *arg);
-
- /// isRegister - Returns 1 if the operand is a register or 0 otherwise
- int isRegister();
- /// regVal - Returns the register value.
- unsigned regVal();
-
- /// isImmediate - Returns 1 if the operand is an immediate or 0 otherwise
- int isImmediate();
- /// immediateVal - Returns the immediate value.
- uint64_t immediateVal();
-
- /// isMemory - Returns 1 if the operand is a memory location or 0 otherwise
- int isMemory();
-
-#ifdef __BLOCKS__
- /// evaluate - Like evaluate for a callback, but uses a block instead
- int evaluate(uint64_t &result,
- EDRegisterBlock_t regBlock);
-#endif
-};
-
-#endif
Removed: llvm/branches/wendling/eh/tools/edis/EDToken.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDToken.cpp?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDToken.cpp (original)
+++ llvm/branches/wendling/eh/tools/edis/EDToken.cpp (removed)
@@ -1,208 +0,0 @@
-//===-EDToken.cpp - LLVM Enhanced Disassembler ----------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the Enhanced Disassembler library's token class. The
-// token is responsible for vending information about the token, such as its
-// type and logical value.
-//
-//===----------------------------------------------------------------------===//
-
-#include "EDDisassembler.h"
-#include "EDToken.h"
-
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-
-using namespace llvm;
-
-EDToken::EDToken(StringRef str,
- enum tokenType type,
- uint64_t localType,
- EDDisassembler &disassembler) :
- Disassembler(disassembler),
- Str(str),
- Type(type),
- LocalType(localType),
- OperandID(-1) {
-}
-
-EDToken::~EDToken() {
-}
-
-void EDToken::makeLiteral(bool sign, uint64_t absoluteValue) {
- Type = kTokenLiteral;
- LiteralSign = sign;
- LiteralAbsoluteValue = absoluteValue;
-}
-
-void EDToken::makeRegister(unsigned registerID) {
- Type = kTokenRegister;
- RegisterID = registerID;
-}
-
-void EDToken::setOperandID(int operandID) {
- OperandID = operandID;
-}
-
-enum EDToken::tokenType EDToken::type() const {
- return Type;
-}
-
-uint64_t EDToken::localType() const {
- return LocalType;
-}
-
-StringRef EDToken::string() const {
- return Str;
-}
-
-int EDToken::operandID() const {
- return OperandID;
-}
-
-int EDToken::literalSign() const {
- if (Type != kTokenLiteral)
- return -1;
- return (LiteralSign ? 1 : 0);
-}
-
-int EDToken::literalAbsoluteValue(uint64_t &value) const {
- if (Type != kTokenLiteral)
- return -1;
- value = LiteralAbsoluteValue;
- return 0;
-}
-
-int EDToken::registerID(unsigned ®isterID) const {
- if (Type != kTokenRegister)
- return -1;
- registerID = RegisterID;
- return 0;
-}
-
-int EDToken::tokenize(std::vector<EDToken*> &tokens,
- std::string &str,
- const char *operandOrder,
- EDDisassembler &disassembler) {
- SmallVector<MCParsedAsmOperand*, 5> parsedOperands;
- SmallVector<AsmToken, 10> asmTokens;
-
- if (disassembler.parseInst(parsedOperands, asmTokens, str))
- return -1;
-
- SmallVectorImpl<MCParsedAsmOperand*>::iterator operandIterator;
- unsigned int operandIndex;
- SmallVectorImpl<AsmToken>::iterator tokenIterator;
-
- operandIterator = parsedOperands.begin();
- operandIndex = 0;
-
- bool readOpcode = false;
-
- const char *wsPointer = asmTokens.begin()->getLoc().getPointer();
-
- for (tokenIterator = asmTokens.begin();
- tokenIterator != asmTokens.end();
- ++tokenIterator) {
- SMLoc tokenLoc = tokenIterator->getLoc();
-
- const char *tokenPointer = tokenLoc.getPointer();
-
- if (tokenPointer > wsPointer) {
- unsigned long wsLength = tokenPointer - wsPointer;
-
- EDToken *whitespaceToken = new EDToken(StringRef(wsPointer, wsLength),
- EDToken::kTokenWhitespace,
- 0,
- disassembler);
-
- tokens.push_back(whitespaceToken);
- }
-
- wsPointer = tokenPointer + tokenIterator->getString().size();
-
- while (operandIterator != parsedOperands.end() &&
- tokenLoc.getPointer() >
- (*operandIterator)->getEndLoc().getPointer()) {
- ++operandIterator;
- ++operandIndex;
- }
-
- EDToken *token;
-
- switch (tokenIterator->getKind()) {
- case AsmToken::Identifier:
- if (!readOpcode) {
- token = new EDToken(tokenIterator->getString(),
- EDToken::kTokenOpcode,
- (uint64_t)tokenIterator->getKind(),
- disassembler);
- readOpcode = true;
- break;
- }
- // any identifier that isn't an opcode is mere punctuation; so we fall
- // through
- default:
- token = new EDToken(tokenIterator->getString(),
- EDToken::kTokenPunctuation,
- (uint64_t)tokenIterator->getKind(),
- disassembler);
- break;
- case AsmToken::Integer:
- {
- token = new EDToken(tokenIterator->getString(),
- EDToken::kTokenLiteral,
- (uint64_t)tokenIterator->getKind(),
- disassembler);
-
- int64_t intVal = tokenIterator->getIntVal();
-
- if (intVal < 0)
- token->makeLiteral(true, -intVal);
- else
- token->makeLiteral(false, intVal);
- break;
- }
- case AsmToken::Register:
- {
- token = new EDToken(tokenIterator->getString(),
- EDToken::kTokenLiteral,
- (uint64_t)tokenIterator->getKind(),
- disassembler);
-
- token->makeRegister((unsigned)tokenIterator->getRegVal());
- break;
- }
- }
-
- if (operandIterator != parsedOperands.end() &&
- tokenLoc.getPointer() >=
- (*operandIterator)->getStartLoc().getPointer()) {
- /// operandIndex == 0 means the operand is the instruction (which the
- /// AsmParser treats as an operand but edis does not). We therefore skip
- /// operandIndex == 0 and subtract 1 from all other operand indices.
-
- if (operandIndex > 0)
- token->setOperandID(operandOrder[operandIndex - 1]);
- }
-
- tokens.push_back(token);
- }
-
- return 0;
-}
-
-int EDToken::getString(const char*& buf) {
- if (PermStr.length() == 0) {
- PermStr = Str.str();
- }
- buf = PermStr.c_str();
- return 0;
-}
Removed: llvm/branches/wendling/eh/tools/edis/EDToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/EDToken.h?rev=109962&view=auto
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/EDToken.h (original)
+++ llvm/branches/wendling/eh/tools/edis/EDToken.h (removed)
@@ -1,135 +0,0 @@
-//===-EDToken.h - LLVM Enhanced Disassembler --------------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interface for the Enhanced Disassembly library's token
-// class. The token is responsible for vending information about the token,
-// such as its type and logical value.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef EDToken_
-#define EDToken_
-
-#include "llvm-c/EnhancedDisassembly.h"
-#include "llvm/ADT/StringRef.h"
-
-#include <string>
-#include <vector>
-
-/// EDToken - Encapsulates a single token, which can provide a string
-/// representation of itself or interpret itself in various ways, depending
-/// on the token type.
-struct EDToken {
- enum tokenType {
- kTokenWhitespace,
- kTokenOpcode,
- kTokenLiteral,
- kTokenRegister,
- kTokenPunctuation
- };
-
- /// The parent disassembler
- EDDisassembler &Disassembler;
-
- /// The token's string representation
- llvm::StringRef Str;
- /// The token's string representation, but in a form suitable for export
- std::string PermStr;
- /// The type of the token, as exposed through the external API
- enum tokenType Type;
- /// The type of the token, as recorded by the syntax-specific tokenizer
- uint64_t LocalType;
- /// The operand corresponding to the token, or (unsigned int)-1 if not
- /// part of an operand.
- int OperandID;
-
- /// The sign if the token is a literal (1 if negative, 0 otherwise)
- bool LiteralSign;
- /// The absolute value if the token is a literal
- uint64_t LiteralAbsoluteValue;
- /// The LLVM register ID if the token is a register name
- unsigned RegisterID;
-
- /// Constructor - Initializes an EDToken with the information common to all
- /// tokens
- ///
- /// @arg str - The string corresponding to the token
- /// @arg type - The token's type as exposed through the public API
- /// @arg localType - The token's type as recorded by the tokenizer
- /// @arg disassembler - The disassembler responsible for the token
- EDToken(llvm::StringRef str,
- enum tokenType type,
- uint64_t localType,
- EDDisassembler &disassembler);
-
- /// makeLiteral - Adds the information specific to a literal
- /// @arg sign - The sign of the literal (1 if negative, 0
- /// otherwise)
- ///
- /// @arg absoluteValue - The absolute value of the literal
- void makeLiteral(bool sign, uint64_t absoluteValue);
- /// makeRegister - Adds the information specific to a register
- ///
- /// @arg registerID - The LLVM register ID
- void makeRegister(unsigned registerID);
-
- /// setOperandID - Links the token to a numbered operand
- ///
- /// @arg operandID - The operand ID to link to
- void setOperandID(int operandID);
-
- ~EDToken();
-
- /// type - Returns the public type of the token
- enum tokenType type() const;
- /// localType - Returns the tokenizer-specific type of the token
- uint64_t localType() const;
- /// string - Returns the string representation of the token
- llvm::StringRef string() const;
- /// operandID - Returns the operand ID of the token
- int operandID() const;
-
- /// literalSign - Returns the sign of the token
- /// (1 if negative, 0 if positive or unsigned, -1 if it is not a literal)
- int literalSign() const;
- /// literalAbsoluteValue - Retrieves the absolute value of the token, and
- /// returns -1 if the token is not a literal
- /// @arg value - A reference to a value that is filled in with the absolute
- /// value, if it is valid
- int literalAbsoluteValue(uint64_t &value) const;
- /// registerID - Retrieves the register ID of the token, and returns -1 if the
- /// token is not a register
- ///
- /// @arg registerID - A reference to a value that is filled in with the
- /// register ID, if it is valid
- int registerID(unsigned ®isterID) const;
-
- /// tokenize - Tokenizes a string using the platform- and syntax-specific
- /// tokenizer, and returns 0 on success (-1 on failure)
- ///
- /// @arg tokens - A vector that will be filled in with pointers to
- /// allocated tokens
- /// @arg str - The string, as outputted by the AsmPrinter
- /// @arg operandOrder - The order of the operands from the operandFlags array
- /// as they appear in str
- /// @arg disassembler - The disassembler for the desired target and
- // assembly syntax
- static int tokenize(std::vector<EDToken*> &tokens,
- std::string &str,
- const char *operandOrder,
- EDDisassembler &disassembler);
-
- /// getString - Directs a character pointer to the string, returning 0 on
- /// success (-1 on failure)
- /// @arg buf - A reference to a pointer that is set to point to the string.
- /// The string is still owned by the token.
- int getString(const char*& buf);
-};
-
-#endif
Modified: llvm/branches/wendling/eh/tools/edis/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/edis/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/edis/Makefile (original)
+++ llvm/branches/wendling/eh/tools/edis/Makefile Sat Jul 31 19:59:02 2010
@@ -9,8 +9,8 @@
LEVEL = ../..
LIBRARYNAME = EnhancedDisassembly
-
-BUILT_SOURCES = EDInfo.inc
+LINK_LIBS_IN_SHARED = 1
+SHARED_LIBRARY = 1
EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/EnhancedDisassembly.exports
@@ -19,23 +19,23 @@
# early so we can set up LINK_COMPONENTS before including Makefile.rules
include $(LEVEL)/Makefile.config
-ifeq ($(ENABLE_PIC),1)
- ifneq ($(DISABLE_EDIS),1)
- ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW))
- LINK_LIBS_IN_SHARED = 1
- SHARED_LIBRARY = 1
- endif
- endif
+LINK_COMPONENTS := mcdisassembler
+
+# If the X86 target is enabled, link in the asmprinter and disassembler.
+ifneq ($(filter $(TARGETS_TO_BUILD), X86),)
+LINK_COMPONENTS += x86asmprinter x86disassembler
endif
-LINK_COMPONENTS := $(TARGETS_TO_BUILD) x86asmprinter x86disassembler
+# If the X86 target is enabled, link in the asmprinter and disassembler.
+ifneq ($(filter $(TARGETS_TO_BUILD), ARM),)
+LINK_COMPONENTS += armasmprinter armdisassembler
+endif
include $(LEVEL)/Makefile.common
ifeq ($(HOST_OS),Darwin)
# extra options to override libtool defaults
LLVMLibsOptions := $(LLVMLibsOptions) \
- -avoid-version \
-Wl,-dead_strip
ifdef EDIS_VERSION
@@ -47,14 +47,8 @@
DARWIN_VERS := $(shell echo $(TARGET_TRIPLE) | sed 's/.*darwin\([0-9]*\).*/\1/')
ifneq ($(DARWIN_VERS),8)
LLVMLibsOptions := $(LLVMLibsOptions) \
- -no-undefined -Wl,-install_name \
+ -Wl,-install_name \
-Wl,"@rpath/lib$(LIBRARYNAME)$(SHLIBEXT)"
endif
endif
-EDInfo.inc: $(TBLGEN)
- $(Echo) "Building semantic information header"
- $(Verb) $(TableGen) -o $(call SYSPATH, $@) -gen-enhanced-disassembly-header /dev/null
-
-clean::
- -$(Verb) $(RM) -f EDInfo.inc
Modified: llvm/branches/wendling/eh/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llc/llc.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llc/llc.cpp (original)
+++ llvm/branches/wendling/eh/tools/llc/llc.cpp Sat Jul 31 19:59:02 2010
@@ -76,6 +76,9 @@
cl::desc("Target specific attributes (-mattr=help for details)"),
cl::value_desc("a1,+a2,-a3,..."));
+static cl::opt<bool>
+RelaxAll("mc-relax-all", cl::desc("Relax all fixups"));
+
cl::opt<TargetMachine::CodeGenFileType>
FileType("filetype", cl::init(TargetMachine::CGFT_AssemblyFile),
cl::desc("Choose a file type (not all types are supported by all targets):"),
@@ -329,6 +332,14 @@
// Override default to generate verbose assembly.
Target.setAsmVerbosityDefault(true);
+ if (RelaxAll) {
+ if (FileType != TargetMachine::CGFT_ObjectFile)
+ errs() << argv[0]
+ << ": warning: ignoring -mc-relax-all because filetype != obj";
+ else
+ Target.setMCRelaxAll(true);
+ }
+
// Ask the target to add backend passes as necessary.
if (Target.addPassesToEmitFile(PM, *Out, FileType, OLvl,
DisableVerify)) {
Modified: llvm/branches/wendling/eh/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original)
+++ llvm/branches/wendling/eh/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Sat Jul 31 19:59:02 2010
@@ -259,11 +259,11 @@
case bitc::METADATA_BLOCK_ID:
switch(CodeID) {
default:return 0;
- case bitc::METADATA_STRING: return "MDSTRING";
- case bitc::METADATA_NODE: return "MDNODE";
- case bitc::METADATA_FN_NODE: return "FN_MDNODE";
+ case bitc::METADATA_STRING: return "METADATA_STRING";
+ case bitc::METADATA_NODE: return "METADATA_NODE";
+ case bitc::METADATA_FN_NODE: return "METADATA_FN_NODE";
case bitc::METADATA_NAME: return "METADATA_NAME";
- case bitc::METADATA_NAMED_NODE: return "NAMEDMDNODE";
+ case bitc::METADATA_NAMED_NODE: return "METADATA_NAMED_NODE";
case bitc::METADATA_KIND: return "METADATA_KIND";
case bitc::METADATA_ATTACHMENT: return "METADATA_ATTACHMENT";
}
Propchange: llvm/branches/wendling/eh/tools/llvm-diff/
------------------------------------------------------------------------------
--- svn:ignore (added)
+++ svn:ignore Sat Jul 31 19:59:02 2010
@@ -0,0 +1,10 @@
+Debug
+Debug+Checks
+Debug+Coverage
+Debug+Coverage-Asserts
+Release
+Release-Asserts
+Release+Coverage
+Debug+Asserts
+Release+Asserts
+
Modified: llvm/branches/wendling/eh/tools/llvm-mc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-mc/CMakeLists.txt?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-mc/CMakeLists.txt (original)
+++ llvm/branches/wendling/eh/tools/llvm-mc/CMakeLists.txt Sat Jul 31 19:59:02 2010
@@ -1,5 +1,4 @@
-set( LLVM_USED_LIBS EnhancedDisassembly)
-set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} support MC MCParser)
+set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} support MC MCParser MCDisassembler)
add_llvm_tool(llvm-mc
llvm-mc.cpp
Modified: llvm/branches/wendling/eh/tools/llvm-mc/Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-mc/Disassembler.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-mc/Disassembler.cpp (original)
+++ llvm/branches/wendling/eh/tools/llvm-mc/Disassembler.cpp Sat Jul 31 19:59:02 2010
@@ -13,21 +13,21 @@
//===----------------------------------------------------------------------===//
#include "Disassembler.h"
-
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/Triple.h"
+#include "../../lib/MC/MCDisassembler/EDDisassembler.h"
+#include "../../lib/MC/MCDisassembler/EDInst.h"
+#include "../../lib/MC/MCDisassembler/EDOperand.h"
+#include "../../lib/MC/MCDisassembler/EDToken.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/Target/TargetRegistry.h"
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/Triple.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/SourceMgr.h"
-
-#include "llvm-c/EnhancedDisassembly.h"
-
using namespace llvm;
typedef std::vector<std::pair<unsigned char, const char*> > ByteArrayTy;
@@ -179,21 +179,17 @@
}
static int verboseEvaluator(uint64_t *V, unsigned R, void *Arg) {
- EDDisassemblerRef &disassembler = *((EDDisassemblerRef*)Arg);
-
- const char *regName;
+ EDDisassembler &disassembler = *((EDDisassembler *)Arg);
- if (!EDGetRegisterName(®Name,
- disassembler,
- R))
+ if (const char *regName = disassembler.nameWithRegisterID(R))
outs() << "[" << regName << "/" << R << "]";
- if (EDRegisterIsStackPointer(disassembler, R))
+
+ if (disassembler.registerIsStackPointer(R))
outs() << "(sp)";
- if (EDRegisterIsProgramCounter(disassembler, R))
+ if (disassembler.registerIsProgramCounter(R))
outs() << "(pc)";
*V = 0;
-
return 0;
}
@@ -209,10 +205,8 @@
return -1;
}
- EDDisassemblerRef disassembler;
-
Triple T(TS);
- EDAssemblySyntax_t AS;
+ EDDisassembler::AssemblySyntax AS;
switch (T.getArch()) {
default:
@@ -220,90 +214,82 @@
return -1;
case Triple::arm:
case Triple::thumb:
- AS = kEDAssemblySyntaxARMUAL;
+ AS = EDDisassembler::kEDAssemblySyntaxARMUAL;
break;
case Triple::x86:
case Triple::x86_64:
- AS = kEDAssemblySyntaxX86ATT;
+ AS = EDDisassembler::kEDAssemblySyntaxX86ATT;
break;
}
- if (EDGetDisassembler(&disassembler,
- TS.c_str(),
- AS)) {
- errs() << "error: couldn't get disassembler for " << TS.c_str() << "\n";
+ EDDisassembler::initialize();
+ EDDisassembler *disassembler =
+ EDDisassembler::getDisassembler(TS.c_str(), AS);
+
+ if (disassembler == 0) {
+ errs() << "error: couldn't get disassembler for " << TS << '\n';
return -1;
}
- EDInstRef inst;
-
- if (EDCreateInsts(&inst, 1, disassembler, byteArrayReader, 0,&ByteArray)
- != 1) {
+ EDInst *inst =
+ disassembler->createInst(byteArrayReader, 0, &ByteArray);
+
+ if (inst == 0) {
errs() << "error: Didn't get an instruction\n";
return -1;
}
- int numTokens = EDNumTokens(inst);
-
- if (numTokens < 0) {
- errs() << "error: Couldn't count the instruction's tokens\n";
+ unsigned numTokens = inst->numTokens();
+ if ((int)numTokens < 0) {
+ errs() << "error: couldn't count the instruction's tokens\n";
return -1;
}
- int tokenIndex;
-
- for (tokenIndex = 0; tokenIndex < numTokens; ++tokenIndex) {
- EDTokenRef token;
+ for (unsigned tokenIndex = 0; tokenIndex != numTokens; ++tokenIndex) {
+ EDToken *token;
- if (EDGetToken(&token, inst, tokenIndex)) {
+ if (inst->getToken(token, tokenIndex)) {
errs() << "error: Couldn't get token\n";
return -1;
}
const char *buf;
-
- if (EDGetTokenString(&buf, token)) {
+ if (token->getString(buf)) {
errs() << "error: Couldn't get string for token\n";
return -1;
}
- outs() << "[";
-
- int operandIndex = EDOperandIndexForToken(token);
+ outs() << '[';
+ int operandIndex = token->operandID();
if (operandIndex >= 0)
outs() << operandIndex << "-";
- if (EDTokenIsWhitespace(token)) {
- outs() << "w";
- } else if (EDTokenIsPunctuation(token)) {
- outs() << "p";
- } else if (EDTokenIsOpcode(token)) {
- outs() << "o";
- } else if (EDTokenIsLiteral(token)) {
- outs() << "l";
- } else if (EDTokenIsRegister(token)) {
- outs() << "r";
- } else {
- outs() << "?";
+ switch (token->type()) {
+ default: outs() << "?"; break;
+ case EDToken::kTokenWhitespace: outs() << "w"; break;
+ case EDToken::kTokenPunctuation: outs() << "p"; break;
+ case EDToken::kTokenOpcode: outs() << "o"; break;
+ case EDToken::kTokenLiteral: outs() << "l"; break;
+ case EDToken::kTokenRegister: outs() << "r"; break;
}
outs() << ":" << buf;
- if (EDTokenIsLiteral(token)) {
+ if (token->type() == EDToken::kTokenLiteral) {
outs() << "=";
- if (EDTokenIsNegativeLiteral(token))
+ if (token->literalSign())
outs() << "-";
uint64_t absoluteValue;
- if (EDLiteralTokenAbsoluteValue(&absoluteValue, token)) {
+ if (token->literalAbsoluteValue(absoluteValue)) {
errs() << "error: Couldn't get the value of a literal token\n";
return -1;
}
outs() << absoluteValue;
- } else if (EDTokenIsRegister(token)) {
+ } else if (token->type() == EDToken::kTokenRegister) {
outs() << "=";
unsigned regID;
- if (EDRegisterTokenValue(®ID, token)) {
+ if (token->registerID(regID)) {
errs() << "error: Couldn't get the ID of a register token\n";
return -1;
}
@@ -315,45 +301,34 @@
outs() << " ";
- if (EDInstIsBranch(inst))
+ if (inst->isBranch())
outs() << "<br> ";
- if (EDInstIsMove(inst))
+ if (inst->isMove())
outs() << "<mov> ";
- int numOperands = EDNumOperands(inst);
+ unsigned numOperands = inst->numOperands();
- if (numOperands < 0) {
+ if ((int)numOperands < 0) {
errs() << "error: Couldn't count operands\n";
return -1;
}
- int operandIndex;
-
- for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
+ for (unsigned operandIndex = 0; operandIndex != numOperands; ++operandIndex) {
outs() << operandIndex << ":";
- EDOperandRef operand;
-
- if (EDGetOperand(&operand,
- inst,
- operandIndex)) {
- errs() << "error: Couldn't get operand\n";
+ EDOperand *operand;
+ if (inst->getOperand(operand, operandIndex)) {
+ errs() << "error: couldn't get operand\n";
return -1;
}
uint64_t evaluatedResult;
-
- EDEvaluateOperand(&evaluatedResult,
- operand,
- verboseEvaluator,
- &disassembler);
-
- outs() << "=" << evaluatedResult;
-
- outs() << " ";
+ evaluatedResult = operand->evaluate(evaluatedResult, verboseEvaluator,
+ disassembler);
+ outs() << "=" << evaluatedResult << " ";
}
- outs() << "\n";
+ outs() << '\n';
return 0;
}
Modified: llvm/branches/wendling/eh/tools/llvm-mc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-mc/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-mc/Makefile (original)
+++ llvm/branches/wendling/eh/tools/llvm-mc/Makefile Sat Jul 31 19:59:02 2010
@@ -18,9 +18,7 @@
# early so we can set up LINK_COMPONENTS before including Makefile.rules
include $(LEVEL)/Makefile.config
-LINK_COMPONENTS := $(TARGETS_TO_BUILD) MCParser MC support
+LINK_COMPONENTS := $(TARGETS_TO_BUILD) MCDisassembler MCParser MC support
include $(LLVM_SRC_ROOT)/Makefile.rules
-# Using LIBS instead of USEDLIBS to force static linking
-LIBS += $(LLVMLibDir)/libEnhancedDisassembly.a
Modified: llvm/branches/wendling/eh/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-mc/llvm-mc.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/branches/wendling/eh/tools/llvm-mc/llvm-mc.cpp Sat Jul 31 19:59:02 2010
@@ -12,13 +12,13 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCParser/AsmParser.h"
#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetAsmParser.h"
#include "llvm/Target/TargetData.h"
@@ -165,9 +165,9 @@
assert(MAI && "Unable to create target asm info!");
AsmLexer Lexer(*MAI);
-
+ Lexer.setBuffer(SrcMgr.getMemoryBuffer(0));
+
bool Error = false;
-
while (Lexer.Lex().isNot(AsmToken::Eof)) {
switch (Lexer.getKind()) {
default:
@@ -287,42 +287,42 @@
return 1;
}
- OwningPtr<MCCodeEmitter> CE;
OwningPtr<MCStreamer> Str;
- OwningPtr<TargetAsmBackend> TAB;
if (FileType == OFT_AssemblyFile) {
MCInstPrinter *IP =
TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI);
+ MCCodeEmitter *CE = 0;
if (ShowEncoding)
- CE.reset(TheTarget->createCodeEmitter(*TM, Ctx));
+ CE = TheTarget->createCodeEmitter(*TM, Ctx);
Str.reset(createAsmStreamer(Ctx, *Out,TM->getTargetData()->isLittleEndian(),
- /*asmverbose*/true, IP, CE.get(), ShowInst));
+ /*asmverbose*/true, IP, CE, ShowInst));
} else if (FileType == OFT_Null) {
Str.reset(createNullStreamer(Ctx));
} else {
assert(FileType == OFT_ObjectFile && "Invalid file type!");
- CE.reset(TheTarget->createCodeEmitter(*TM, Ctx));
- TAB.reset(TheTarget->createAsmBackend(TripleName));
+ MCCodeEmitter *CE = TheTarget->createCodeEmitter(*TM, Ctx);
+ TargetAsmBackend *TAB = TheTarget->createAsmBackend(TripleName);
Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *TAB,
- *Out, CE.get(), RelaxAll));
+ *Out, CE, RelaxAll));
}
if (EnableLogging) {
Str.reset(createLoggingStreamer(Str.take(), errs()));
}
- AsmParser Parser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI);
- OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(Parser));
+ OwningPtr<MCAsmParser> Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
+ *Str.get(), *MAI));
+ OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(*Parser, *TM));
if (!TAP) {
errs() << ProgName
<< ": error: this target does not support assembly parsing.\n";
return 1;
}
- Parser.setTargetParser(*TAP.get());
+ Parser->setTargetParser(*TAP.get());
- int Res = Parser.Run(NoInitialTextSection);
+ int Res = Parser->Run(NoInitialTextSection);
delete Out;
// Delete output on errors.
Modified: llvm/branches/wendling/eh/tools/llvm-shlib/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvm-shlib/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvm-shlib/Makefile (original)
+++ llvm/branches/wendling/eh/tools/llvm-shlib/Makefile Sat Jul 31 19:59:02 2010
@@ -38,7 +38,6 @@
LLVMLibsOptions := $(LLVMLibsOptions) -all_load
# extra options to override libtool defaults
LLVMLibsOptions := $(LLVMLibsOptions) \
- -avoid-version \
-Wl,-dead_strip \
-Wl,-seg1addr -Wl,0xE0000000
Modified: llvm/branches/wendling/eh/tools/llvmc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvmc/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvmc/Makefile (original)
+++ llvm/branches/wendling/eh/tools/llvmc/Makefile Sat Jul 31 19:59:02 2010
@@ -11,7 +11,6 @@
export LLVMC_BASED_DRIVER_NAME = llvmc
export LLVMC_BUILTIN_PLUGINS = Base Clang
-REQUIRES_RTTI = 1
DIRS = plugins driver
Modified: llvm/branches/wendling/eh/tools/llvmc/doc/LLVMC-Reference.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvmc/doc/LLVMC-Reference.rst?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvmc/doc/LLVMC-Reference.rst (original)
+++ llvm/branches/wendling/eh/tools/llvmc/doc/LLVMC-Reference.rst Sat Jul 31 19:59:02 2010
@@ -299,7 +299,7 @@
* Possible option types:
- ``switch_option`` - a simple boolean switch without arguments, for example
- ``-O2`` or ``-time``. At most one occurrence is allowed.
+ ``-O2`` or ``-time``. At most one occurrence is allowed by default.
- ``parameter_option`` - option that takes one argument, for example
``-std=c99``. It is also allowed to use spaces instead of the equality
@@ -321,6 +321,13 @@
option types, aliases are not allowed to have any properties besides the
aliased option name. Usage example: ``(alias_option "preprocess", "E")``
+ - ``switch_list_option`` - like ``switch_option`` with the ``zero_or_more``
+ property, but remembers how many times the switch was turned on. Useful
+ mostly for forwarding. Example: when ``-foo`` is a switch option (with the
+ ``zero_or_more`` property), the command ``driver -foo -foo`` is forwarded
+ as ``some-tool -foo``, but when ``-foo`` is a switch list, the same command
+ is forwarded as ``some-tool -foo -foo``.
+
* Possible option properties:
Modified: llvm/branches/wendling/eh/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp (original)
+++ llvm/branches/wendling/eh/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Sat Jul 31 19:59:02 2010
@@ -35,7 +35,7 @@
}
std::string LowerCase;
- for (unsigned i = 0; i <= Partname.size(); i++) {
+ for (unsigned i = 0; i < Partname.size(); i++) {
LowerCase.push_back(std::tolower(Partname[i]));
}
@@ -52,7 +52,7 @@
}
std::string UpperCase;
- for (unsigned i = 0; i <= Partname.size(); i++) {
+ for (unsigned i = 0; i < Partname.size(); i++) {
UpperCase.push_back(std::toupper(Partname[i]));
}
Modified: llvm/branches/wendling/eh/tools/lto/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/lto/Makefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/lto/Makefile (original)
+++ llvm/branches/wendling/eh/tools/lto/Makefile Sat Jul 31 19:59:02 2010
@@ -25,15 +25,22 @@
include $(LEVEL)/Makefile.common
ifeq ($(HOST_OS),Darwin)
+ # Special hack to allow libLTO to have an offset version number.
+ ifdef LLVM_LTO_VERSION_OFFSET
+ LTO_LIBRARY_VERSION := $(shell expr $(LLVM_SUBMIT_VERSION) + \
+ $(LLVM_LTO_VERSION_OFFSET))
+ else
+ LTO_LIBRARY_VERSION := $(LLVM_SUBMIT_VERSION)
+ endif
+
# set dylib internal version number to llvmCore submission number
ifdef LLVM_SUBMIT_VERSION
LLVMLibsOptions := $(LLVMLibsOptions) -Wl,-current_version \
- -Wl,$(LLVM_SUBMIT_VERSION).$(LLVM_SUBMIT_SUBVERSION) \
+ -Wl,$(LTO_LIBRARY_VERSION).$(LLVM_SUBMIT_SUBVERSION) \
-Wl,-compatibility_version -Wl,1
endif
# extra options to override libtool defaults
LLVMLibsOptions := $(LLVMLibsOptions) \
- -avoid-version \
-Wl,-dead_strip \
-Wl,-seg1addr -Wl,0xE0000000
@@ -41,7 +48,7 @@
DARWIN_VERS := $(shell echo $(TARGET_TRIPLE) | sed 's/.*darwin\([0-9]*\).*/\1/')
ifneq ($(DARWIN_VERS),8)
LLVMLibsOptions := $(LLVMLibsOptions) \
- -no-undefined -Wl,-install_name \
+ -Wl,-install_name \
-Wl,"@executable_path/../lib/lib$(LIBRARYNAME)$(SHLIBEXT)"
endif
endif
Modified: llvm/branches/wendling/eh/tools/opt/AnalysisWrappers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/tools/opt/AnalysisWrappers.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/tools/opt/AnalysisWrappers.cpp (original)
+++ llvm/branches/wendling/eh/tools/opt/AnalysisWrappers.cpp Sat Jul 31 19:59:02 2010
@@ -42,8 +42,8 @@
Instruction *User = dyn_cast<Instruction>(*UI);
if (!User) continue;
- CallSite CS = CallSite::get(User);
- if (!CS.getInstruction()) continue;
+ CallSite CS(cast<Value>(User));
+ if (!CS) continue;
for (CallSite::arg_iterator AI = CS.arg_begin(),
E = CS.arg_end(); AI != E; ++AI) {
Modified: llvm/branches/wendling/eh/unittests/ADT/ValueMapTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/unittests/ADT/ValueMapTest.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/unittests/ADT/ValueMapTest.cpp (original)
+++ llvm/branches/wendling/eh/unittests/ADT/ValueMapTest.cpp Sat Jul 31 19:59:02 2010
@@ -39,6 +39,15 @@
typedef ::testing::Types<Value, Instruction, const Instruction> KeyTypes;
TYPED_TEST_CASE(ValueMapTest, KeyTypes);
+TYPED_TEST(ValueMapTest, CopyConstructor) {
+ ValueMap<TypeParam*, int> VM1;
+ VM1[this->AddV.get()] = 7;
+ ValueMap<TypeParam*, int> VM2(VM1);
+ this->AddV.reset();
+ EXPECT_TRUE(VM1.empty());
+ EXPECT_TRUE(VM2.empty());
+}
+
TYPED_TEST(ValueMapTest, Null) {
ValueMap<TypeParam*, int> VM1;
VM1[NULL] = 7;
Modified: llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/JITTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/JITTest.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/JITTest.cpp (original)
+++ llvm/branches/wendling/eh/unittests/ExecutionEngine/JIT/JITTest.cpp Sat Jul 31 19:59:02 2010
@@ -65,8 +65,6 @@
stubsAllocated = 0;
}
- void setSizeRequired(bool Required) { SizeRequired = Required; }
-
virtual void setMemoryWritable() { Base->setMemoryWritable(); }
virtual void setMemoryExecutable() { Base->setMemoryExecutable(); }
virtual void setPoisonMemory(bool poison) { Base->setPoisonMemory(poison); }
@@ -630,31 +628,6 @@
<< " not 7 from the IR version.";
}
-TEST_F(JITTest, NeedsExactSizeWithManyGlobals) {
- // PR5291: When the JMM needed the exact size of function bodies before
- // starting to emit them, the JITEmitter would modify a set while iterating
- // over it.
- TheJIT->DisableLazyCompilation(true);
- RJMM->setSizeRequired(true);
-
- LoadAssembly("@A = global i32 42 "
- "@B = global i32* @A "
- "@C = global i32** @B "
- "@D = global i32*** @C "
- "@E = global i32**** @D "
- "@F = global i32***** @E "
- "@G = global i32****** @F "
- "@H = global i32******* @G "
- "@I = global i32******** @H "
- "define i32********* @test() { "
- " ret i32********* @I "
- "}");
- Function *testIR = M->getFunction("test");
- int32_t********* (*test)() = reinterpret_cast<int32_t*********(*)()>(
- (intptr_t)TheJIT->getPointerToFunction(testIR));
- EXPECT_EQ(42, *********test());
-}
-
TEST_F(JITTest, EscapedLazyStubStillCallable) {
TheJIT->DisableLazyCompilation(false);
LoadAssembly("define internal i32 @stubbed() { "
Modified: llvm/branches/wendling/eh/unittests/VMCore/DerivedTypesTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/unittests/VMCore/DerivedTypesTest.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/unittests/VMCore/DerivedTypesTest.cpp (original)
+++ llvm/branches/wendling/eh/unittests/VMCore/DerivedTypesTest.cpp Sat Jul 31 19:59:02 2010
@@ -9,13 +9,66 @@
#include "gtest/gtest.h"
#include "../lib/VMCore/LLVMContextImpl.h"
-#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
#include "llvm/LLVMContext.h"
+#include "llvm/Constants.h"
+#include "llvm/Support/ValueHandle.h"
using namespace llvm;
namespace {
+static void PR7658() {
+ LLVMContext ctx;
+
+ WeakVH NullPtr;
+ PATypeHolder h1;
+ {
+ OpaqueType *o1 = OpaqueType::get(ctx);
+ PointerType *p1 = PointerType::get(o1, 0);
+
+ std::vector<const Type *> t1;
+ t1.push_back(IntegerType::get(ctx, 32));
+ t1.push_back(p1);
+ NullPtr = ConstantPointerNull::get(p1);
+ OpaqueType *o2 = OpaqueType::get (ctx);
+ PointerType *p2 = PointerType::get (o2, 0);
+ t1.push_back(p2);
+
+
+ StructType *s1 = StructType::get(ctx, t1);
+ h1 = s1;
+ o1->refineAbstractTypeTo(s1);
+ o2->refineAbstractTypeTo(h1.get()); // h1 = { i32, \2*, \2* }
+ }
+
+
+ OpaqueType *o3 = OpaqueType::get(ctx);
+ PointerType *p3 = PointerType::get(o3, 0); // p3 = opaque*
+
+ std::vector<const Type *> t2;
+ t2.push_back(IntegerType::get(ctx, 32));
+ t2.push_back(p3);
+
+ std::vector<Constant *> v2;
+ v2.push_back(ConstantInt::get(IntegerType::get(ctx, 32), 14));
+ v2.push_back(ConstantPointerNull::get(p3));
+
+ OpaqueType *o4 = OpaqueType::get(ctx);
+ {
+ PointerType *p4 = PointerType::get(o4, 0);
+ t2.push_back(p4);
+ v2.push_back(ConstantPointerNull::get(p4));
+ }
+
+ WeakVH CS = ConstantStruct::get(ctx, v2, false); // { i32 14, opaque* null, opaque* null}
+
+ StructType *s2 = StructType::get(ctx, t2);
+ PATypeHolder h2(s2);
+ o3->refineAbstractTypeTo(s2);
+ o4->refineAbstractTypeTo(h2.get());
+}
+
+
TEST(OpaqueTypeTest, RegisterWithContext) {
LLVMContext C;
LLVMContextImpl *pImpl = C.pImpl;
@@ -28,6 +81,8 @@
EXPECT_EQ(2u, pImpl->OpaqueTypes.size());
}
EXPECT_EQ(1u, pImpl->OpaqueTypes.size());
+
+ PR7658();
}
} // namespace
Modified: llvm/branches/wendling/eh/unittests/VMCore/MetadataTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/unittests/VMCore/MetadataTest.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/unittests/VMCore/MetadataTest.cpp (original)
+++ llvm/branches/wendling/eh/unittests/VMCore/MetadataTest.cpp Sat Jul 31 19:59:02 2010
@@ -130,11 +130,12 @@
MDNode *n = MDNode::get(Context, &V, 1);
MDNode *n2 = MDNode::get(Context, &V2, 1);
- MDNode *Nodes[2] = { n, n2 };
-
Module M("MyModule", Context);
const char *Name = "llvm.NMD1";
- NamedMDNode *NMD = NamedMDNode::Create(Context, Name, &Nodes[0], 2, &M);
+ NamedMDNode *NMD = M.getOrInsertNamedMetadata(Name);
+ NMD->addOperand(n);
+ NMD->addOperand(n2);
+
std::string Str;
raw_string_ostream oss(Str);
NMD->print(oss);
Modified: llvm/branches/wendling/eh/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/AsmMatcherEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/AsmMatcherEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -271,6 +271,8 @@
namespace {
+struct SubtargetFeatureInfo;
+
/// ClassInfo - Helper class for storing the information about a particular
/// class of operands which can be matched.
struct ClassInfo {
@@ -444,6 +446,9 @@
/// Operands - The operands that this instruction matches.
SmallVector<Operand, 4> Operands;
+ /// Predicates - The required subtarget features to match this instruction.
+ SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures;
+
/// ConversionFnKind - The enum value which is passed to the generated
/// ConvertToMCInst to convert parsed operands into an MCInst for this
/// function.
@@ -505,6 +510,19 @@
void dump();
};
+/// SubtargetFeatureInfo - Helper class for storing information on a subtarget
+/// feature which participates in instruction matching.
+struct SubtargetFeatureInfo {
+ /// \brief The predicate record for this feature.
+ Record *TheDef;
+
+ /// \brief An unique index assigned to represent this feature.
+ unsigned Index;
+
+ /// \brief The name of the enumerated constant identifying this feature.
+ std::string EnumName;
+};
+
class AsmMatcherInfo {
public:
/// The tablegen AsmParser record.
@@ -525,6 +543,9 @@
/// Map of Register records to their class information.
std::map<Record*, ClassInfo*> RegisterClasses;
+ /// Map of Predicate records to their subtarget information.
+ std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures;
+
private:
/// Map of token to class information which has already been constructed.
std::map<std::string, ClassInfo*> TokenClasses;
@@ -543,6 +564,23 @@
ClassInfo *getOperandClass(StringRef Token,
const CodeGenInstruction::OperandInfo &OI);
+ /// getSubtargetFeature - Lookup or create the subtarget feature info for the
+ /// given operand.
+ SubtargetFeatureInfo *getSubtargetFeature(Record *Def) {
+ assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
+
+ SubtargetFeatureInfo *&Entry = SubtargetFeatures[Def];
+ if (!Entry) {
+ Entry = new SubtargetFeatureInfo;
+ Entry->TheDef = Def;
+ Entry->Index = SubtargetFeatures.size() - 1;
+ Entry->EnumName = "Feature_" + Def->getName();
+ assert(Entry->Index < 32 && "Too many subtarget features!");
+ }
+
+ return Entry;
+ }
+
/// BuildRegisterClasses - Build the ClassInfo* instances for register
/// classes.
void BuildRegisterClasses(CodeGenTarget &Target,
@@ -903,7 +941,31 @@
}
}
}
-
+
+ // Compute the require features.
+ ListInit *Predicates = CGI.TheDef->getValueAsListInit("Predicates");
+ for (unsigned i = 0, e = Predicates->getSize(); i != e; ++i) {
+ if (DefInit *Pred = dynamic_cast<DefInit*>(Predicates->getElement(i))) {
+ // Ignore OptForSize and OptForSpeed, they aren't really requirements,
+ // rather they are hints to isel.
+ //
+ // FIXME: Find better way to model this.
+ if (Pred->getDef()->getName() == "OptForSize" ||
+ Pred->getDef()->getName() == "OptForSpeed")
+ continue;
+
+ // FIXME: Total hack; for now, we just limit ourselves to In32BitMode
+ // and In64BitMode, because we aren't going to have the right feature
+ // masks for SSE and friends. We need to decide what we are going to do
+ // about CPU subtypes to implement this the right way.
+ if (Pred->getDef()->getName() != "In32BitMode" &&
+ Pred->getDef()->getName() != "In64BitMode")
+ continue;
+
+ II->RequiredFeatures.push_back(getSubtargetFeature(Pred->getDef()));
+ }
+ }
+
Instructions.push_back(II.take());
}
@@ -1499,6 +1561,48 @@
OS << "}\n\n";
}
+/// EmitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
+/// definitions.
+static void EmitSubtargetFeatureFlagEnumeration(CodeGenTarget &Target,
+ AsmMatcherInfo &Info,
+ raw_ostream &OS) {
+ OS << "// Flags for subtarget features that participate in "
+ << "instruction matching.\n";
+ OS << "enum SubtargetFeatureFlag {\n";
+ for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
+ it = Info.SubtargetFeatures.begin(),
+ ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
+ SubtargetFeatureInfo &SFI = *it->second;
+ OS << " " << SFI.EnumName << " = (1 << " << SFI.Index << "),\n";
+ }
+ OS << " Feature_None = 0\n";
+ OS << "};\n\n";
+}
+
+/// EmitComputeAvailableFeatures - Emit the function to compute the list of
+/// available features given a subtarget.
+static void EmitComputeAvailableFeatures(CodeGenTarget &Target,
+ AsmMatcherInfo &Info,
+ raw_ostream &OS) {
+ std::string ClassName =
+ Info.AsmParser->getValueAsString("AsmParserClassName");
+
+ OS << "unsigned " << Target.getName() << ClassName << "::\n"
+ << "ComputeAvailableFeatures(const " << Target.getName()
+ << "Subtarget *Subtarget) const {\n";
+ OS << " unsigned Features = 0;\n";
+ for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator
+ it = Info.SubtargetFeatures.begin(),
+ ie = Info.SubtargetFeatures.end(); it != ie; ++it) {
+ SubtargetFeatureInfo &SFI = *it->second;
+ OS << " if (" << SFI.TheDef->getValueAsString("CondString")
+ << ")\n";
+ OS << " Features |= " << SFI.EnumName << ";\n";
+ }
+ OS << " return Features;\n";
+ OS << "}\n\n";
+}
+
void AsmMatcherEmitter::run(raw_ostream &OS) {
CodeGenTarget Target;
Record *AsmParser = Target.getAsmParser();
@@ -1550,6 +1654,9 @@
EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
+ // Emit the subtarget feature enumeration.
+ EmitSubtargetFeatureFlagEnumeration(Target, Info, OS);
+
// Emit the function to match a register name to number.
EmitMatchRegisterName(Target, AsmParser, OS);
@@ -1570,6 +1677,9 @@
// Emit the subclass predicate routine.
EmitIsSubclass(Target, Info.Classes, OS);
+ // Emit the available features compute function.
+ EmitComputeAvailableFeatures(Target, Info, OS);
+
// Finally, build the match function.
size_t MaxNumOperands = 0;
@@ -1600,6 +1710,7 @@
OS << " unsigned Opcode;\n";
OS << " ConversionKind ConvertFn;\n";
OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
+ OS << " unsigned RequiredFeatures;\n";
OS << " } MatchTable[" << Info.Instructions.size() << "] = {\n";
for (std::vector<InstructionInfo*>::const_iterator it =
@@ -1615,11 +1726,27 @@
if (i) OS << ", ";
OS << Op.Class->Name;
}
- OS << " } },\n";
+ OS << " }, ";
+
+ // Write the required features mask.
+ if (!II.RequiredFeatures.empty()) {
+ for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
+ if (i) OS << "|";
+ OS << II.RequiredFeatures[i]->EnumName;
+ }
+ } else
+ OS << "0";
+
+ OS << "},\n";
}
OS << " };\n\n";
+
+ // Emit code to get the available features.
+ OS << " // Get the current feature set.\n";
+ OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n";
+
// Emit code to compute the class list for this operand vector.
OS << " // Eliminate obvious mismatches.\n";
OS << " if (Operands.size() > " << MaxNumOperands << ")\n";
@@ -1645,6 +1772,13 @@
OS << " for (const MatchEntry *it = MatchTable, "
<< "*ie = MatchTable + " << Info.Instructions.size()
<< "; it != ie; ++it) {\n";
+
+ // Emit check that the required features are available.
+ OS << " if ((AvailableFeatures & it->RequiredFeatures) "
+ << "!= it->RequiredFeatures)\n";
+ OS << " continue;\n";
+
+ // Emit check that the subclasses match.
for (unsigned i = 0; i != MaxNumOperands; ++i) {
OS << " if (!IsSubclass(Classes["
<< i << "], it->Classes[" << i << "]))\n";
Modified: llvm/branches/wendling/eh/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/AsmWriterEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/AsmWriterEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -115,7 +115,7 @@
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
const AsmWriterInst *Inst = getAsmWriterInstByID(i);
- if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc.
+ if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
std::string Command;
if (Inst->Operands.empty())
Modified: llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.cpp Sat Jul 31 19:59:02 2010
@@ -102,6 +102,7 @@
isReturn = R->getValueAsBit("isReturn");
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
+ isCompare = R->getValueAsBit("isCompare");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
Modified: llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/branches/wendling/eh/utils/TableGen/CodeGenInstruction.h Sat Jul 31 19:59:02 2010
@@ -123,6 +123,7 @@
bool isReturn;
bool isBranch;
bool isIndirectBranch;
+ bool isCompare;
bool isBarrier;
bool isCall;
bool canFoldAsLoad;
Modified: llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/CodeGenTarget.cpp Sat Jul 31 19:59:02 2010
@@ -333,7 +333,7 @@
const char *const FixedInstrs[] = {
"PHI",
"INLINEASM",
- "DBG_LABEL",
+ "PROLOG_LABEL",
"EH_LABEL",
"GC_LABEL",
"KILL",
Modified: llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/EDEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -339,6 +339,7 @@
MEM("f80mem");
MEM("opaque80mem");
MEM("i128mem");
+ MEM("i256mem");
MEM("f128mem");
MEM("f256mem");
MEM("opaque512mem");
@@ -577,6 +578,7 @@
static int ARMFlagFromOpName(LiteralConstantEmitter *type,
const std::string &name) {
REG("GPR");
+ REG("rGPR");
REG("tcGPR");
REG("cc_out");
REG("s_cc_out");
@@ -895,21 +897,3 @@
o << "}\n";
}
-
-void EDEmitter::runHeader(raw_ostream &o) {
- EmitSourceFileHeader("Enhanced Disassembly Info Header", o);
-
- o << "#ifndef EDInfo_" << "\n";
- o << "#define EDInfo_" << "\n";
- o << "\n";
- o << "#define EDIS_MAX_OPERANDS " << format("%d", EDIS_MAX_OPERANDS) << "\n";
- o << "#define EDIS_MAX_SYNTAXES " << format("%d", EDIS_MAX_SYNTAXES) << "\n";
- o << "\n";
-
- unsigned int i = 0;
-
- emitCommonEnums(o, i);
-
- o << "\n";
- o << "#endif" << "\n";
-}
Modified: llvm/branches/wendling/eh/utils/TableGen/EDEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/EDEmitter.h?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/EDEmitter.h (original)
+++ llvm/branches/wendling/eh/utils/TableGen/EDEmitter.h Sat Jul 31 19:59:02 2010
@@ -27,9 +27,6 @@
// run - Output the instruction table.
void run(raw_ostream &o);
-
- // runHeader - Emit a header file that allows use of the instruction table.
- void runHeader(raw_ostream &o);
};
} // End llvm namespace
Modified: llvm/branches/wendling/eh/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/FastISelEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/FastISelEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -54,6 +54,7 @@
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
MVT::SimpleValueType VT) {
+
if (!InstPatNode->isLeaf()) {
if (InstPatNode->getOperator()->getName() == "imm") {
Operands.push_back("i");
@@ -69,6 +70,7 @@
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
+
// For now, filter out any operand with a predicate.
// For now, filter out any operand with multiple values.
if (!Op->getPredicateFns().empty() ||
@@ -105,6 +107,7 @@
RC = Target.getRegisterClassForRegister(OpLeafRec);
else
return false;
+
// For now, require the register operands' register classes to all
// be the same.
if (!RC)
@@ -208,7 +211,8 @@
typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
- typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> OperandsOpcodeTypeRetPredMap;
+ typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
+ OperandsOpcodeTypeRetPredMap;
OperandsOpcodeTypeRetPredMap SimplePatterns;
@@ -261,6 +265,15 @@
if (II.OperandList.empty())
continue;
+ // For now ignore instructions that have predicate operands.
+ bool HasPredicate = false;
+ for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) {
+ if(II.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+ HasPredicate = true;
+ }
+ if (HasPredicate)
+ continue;
+
// For now, ignore multi-instruction patterns.
bool MultiInsts = false;
for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
@@ -287,6 +300,10 @@
if (!DstRC)
continue;
} else {
+ // If this isn't a leaf, then continue since the register classes are
+ // a bit too complicated for now.
+ if (!Dst->getChild(1)->isLeaf()) continue;
+
DefInit *SR = dynamic_cast<DefInit*>(Dst->getChild(1)->getLeafValue());
if (SR)
SubRegNo = getQualifiedName(SR->getDef());
@@ -371,7 +388,8 @@
SubRegNo,
PhysRegInputs
};
- assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
+ assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT]
+ .count(PredicateCheck) &&
"Duplicate pattern!");
SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
}
Modified: llvm/branches/wendling/eh/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/InstrInfoEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/InstrInfoEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -270,6 +270,7 @@
if (Inst.isReturn) OS << "|(1<<TID::Return)";
if (Inst.isBranch) OS << "|(1<<TID::Branch)";
if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
+ if (Inst.isCompare) OS << "|(1<<TID::Compare)";
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|(1<<TID::Call)";
Modified: llvm/branches/wendling/eh/utils/TableGen/LLVMCConfigurationEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/LLVMCConfigurationEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/LLVMCConfigurationEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/LLVMCConfigurationEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -188,21 +188,25 @@
/// documentation for detailed description of differences.
namespace OptionType {
- enum OptionType { Alias, Switch, Parameter, ParameterList,
- Prefix, PrefixList};
+ enum OptionType { Alias, Switch, SwitchList,
+ Parameter, ParameterList, Prefix, PrefixList };
bool IsAlias(OptionType t) {
return (t == Alias);
}
bool IsList (OptionType t) {
- return (t == ParameterList || t == PrefixList);
+ return (t == SwitchList || t == ParameterList || t == PrefixList);
}
bool IsSwitch (OptionType t) {
return (t == Switch);
}
+ bool IsSwitchList (OptionType t) {
+ return (t == SwitchList);
+ }
+
bool IsParameter (OptionType t) {
return (t == Parameter || t == Prefix);
}
@@ -214,6 +218,8 @@
return OptionType::Alias;
else if (T == "switch_option")
return OptionType::Switch;
+ else if (T == "switch_list_option")
+ return OptionType::SwitchList;
else if (T == "parameter_option")
return OptionType::Parameter;
else if (T == "parameter_list_option")
@@ -300,12 +306,19 @@
bool isSwitch() const
{ return OptionType::IsSwitch(this->Type); }
+ bool isSwitchList() const
+ { return OptionType::IsSwitchList(this->Type); }
+
bool isParameter() const
{ return OptionType::IsParameter(this->Type); }
bool isList() const
{ return OptionType::IsList(this->Type); }
+ bool isParameterList() const
+ { return (OptionType::IsList(this->Type)
+ && !OptionType::IsSwitchList(this->Type)); }
+
};
void OptionDescription::CheckConsistency() const {
@@ -417,6 +430,8 @@
return "cl::list<std::string>";
case OptionType::Switch:
return "cl::opt<bool>";
+ case OptionType::SwitchList:
+ return "cl::list<bool>";
case OptionType::Parameter:
case OptionType::Prefix:
default:
@@ -434,6 +449,8 @@
return "AutoGeneratedList_" + EscapedName;
case OptionType::Switch:
return "AutoGeneratedSwitch_" + EscapedName;
+ case OptionType::SwitchList:
+ return "AutoGeneratedSwitchList_" + EscapedName;
case OptionType::Prefix:
case OptionType::Parameter:
default:
@@ -458,8 +475,11 @@
const OptionDescription& FindSwitch(const std::string& OptName) const;
const OptionDescription& FindParameter(const std::string& OptName) const;
const OptionDescription& FindList(const std::string& OptName) const;
+ const OptionDescription& FindParameterList(const std::string& OptName) const;
const OptionDescription&
FindListOrParameter(const std::string& OptName) const;
+ const OptionDescription&
+ FindParameterListOrParameter(const std::string& OptName) const;
/// insertDescription - Insert new OptionDescription into
/// OptionDescriptions list
@@ -497,6 +517,14 @@
}
const OptionDescription&
+OptionDescriptions::FindParameterList(const std::string& OptName) const {
+ const OptionDescription& OptDesc = this->FindOption(OptName);
+ if (!OptDesc.isList() || OptDesc.isSwitchList())
+ throw OptName + ": incorrect option type - should be a parameter list!";
+ return OptDesc;
+}
+
+const OptionDescription&
OptionDescriptions::FindParameter(const std::string& OptName) const {
const OptionDescription& OptDesc = this->FindOption(OptName);
if (!OptDesc.isParameter())
@@ -513,6 +541,16 @@
return OptDesc;
}
+const OptionDescription&
+OptionDescriptions::FindParameterListOrParameter
+(const std::string& OptName) const {
+ const OptionDescription& OptDesc = this->FindOption(OptName);
+ if ((!OptDesc.isList() && !OptDesc.isParameter()) || OptDesc.isSwitchList())
+ throw OptName
+ + ": incorrect option type - should be a parameter list or parameter!";
+ return OptDesc;
+}
+
void OptionDescriptions::InsertDescription (const OptionDescription& o) {
container_type::iterator I = Descriptions.find(o.Name);
if (I != Descriptions.end()) {
@@ -666,8 +704,8 @@
void onCommaSeparated (const DagInit& d) {
CheckNumberOfArguments(d, 0);
- if (!optDesc_.isList())
- throw "'comma_separated' is valid only on list options!";
+ if (!optDesc_.isParameterList())
+ throw "'comma_separated' is valid only on parameter list options!";
optDesc_.setCommaSeparated();
}
@@ -709,7 +747,7 @@
void onZeroOrMore (const DagInit& d) {
CheckNumberOfArguments(d, 0);
- if (OptionType::IsList(optDesc_.Type))
+ if (optDesc_.isList())
llvm::errs() << "Warning: specifying the 'zero_or_more' property "
"on a list option has no effect.\n";
@@ -720,7 +758,7 @@
void onOptional (const DagInit& d) {
CheckNumberOfArguments(d, 0);
- if (!OptionType::IsList(optDesc_.Type))
+ if (!optDesc_.isList())
llvm::errs() << "Warning: specifying the 'optional' property"
"on a non-list option has no effect.\n";
@@ -734,7 +772,7 @@
if (val < 2)
throw "Error in the 'multi_val' property: "
"the value must be greater than 1!";
- if (!OptionType::IsList(optDesc_.Type))
+ if (!optDesc_.isParameterList())
throw "The multi_val property is valid only on list options!";
optDesc_.MultiVal = val;
}
@@ -1440,7 +1478,7 @@
return true;
}
else if (TestName == "element_in_list") {
- const OptionDescription& OptDesc = OptDescs.FindList(OptName);
+ const OptionDescription& OptDesc = OptDescs.FindParameterList(OptName);
const std::string& VarName = OptDesc.GenVariableName();
O << "std::find(" << VarName << ".begin(),\n";
O.indent(IndentLevel + Indent1)
@@ -1815,6 +1853,24 @@
}
+/// EmitForEachListElementCycleHeader - Emit common code for iterating through
+/// all elements of a list. Helper function used by
+/// EmitForwardOptionPropertyHandlingCode.
+void EmitForEachListElementCycleHeader (const OptionDescription& D,
+ unsigned IndentLevel,
+ raw_ostream& O) {
+ unsigned IndentLevel1 = IndentLevel + Indent1;
+
+ O.indent(IndentLevel)
+ << "for (" << D.GenTypeDeclaration()
+ << "::iterator B = " << D.GenVariableName() << ".begin(),\n";
+ O.indent(IndentLevel)
+ << "E = " << D.GenVariableName() << ".end(); B != E;) {\n";
+ O.indent(IndentLevel1) << "unsigned pos = " << D.GenVariableName()
+ << ".getPosition(B - " << D.GenVariableName()
+ << ".begin());\n";
+}
+
/// EmitForwardOptionPropertyHandlingCode - Helper function used to
/// implement EmitActionHandler. Emits code for
/// handling the (forward) and (forward_as) option properties.
@@ -1855,14 +1911,7 @@
<< D.GenVariableName() << "));\n";
break;
case OptionType::PrefixList:
- O.indent(IndentLevel)
- << "for (" << D.GenTypeDeclaration()
- << "::iterator B = " << D.GenVariableName() << ".begin(),\n";
- O.indent(IndentLevel)
- << "E = " << D.GenVariableName() << ".end(); B != E;) {\n";
- O.indent(IndentLevel1) << "unsigned pos = " << D.GenVariableName()
- << ".getPosition(B - " << D.GenVariableName()
- << ".begin());\n";
+ EmitForEachListElementCycleHeader(D, IndentLevel, O);
O.indent(IndentLevel1) << "vec.push_back(std::make_pair(pos, \""
<< Name << "\" + " << "*B));\n";
O.indent(IndentLevel1) << "++B;\n";
@@ -1875,14 +1924,7 @@
O.indent(IndentLevel) << "}\n";
break;
case OptionType::ParameterList:
- O.indent(IndentLevel)
- << "for (" << D.GenTypeDeclaration() << "::iterator B = "
- << D.GenVariableName() << ".begin(),\n";
- O.indent(IndentLevel) << "E = " << D.GenVariableName()
- << ".end() ; B != E;) {\n";
- O.indent(IndentLevel1) << "unsigned pos = " << D.GenVariableName()
- << ".getPosition(B - " << D.GenVariableName()
- << ".begin());\n";
+ EmitForEachListElementCycleHeader(D, IndentLevel, O);
O.indent(IndentLevel1) << "vec.push_back(std::make_pair(pos, \""
<< Name << "\"));\n";
@@ -1893,6 +1935,13 @@
O.indent(IndentLevel) << "}\n";
break;
+ case OptionType::SwitchList:
+ EmitForEachListElementCycleHeader(D, IndentLevel, O);
+ O.indent(IndentLevel1) << "vec.push_back(std::make_pair(pos, \""
+ << Name << "\"));\n";
+ O.indent(IndentLevel1) << "++B;\n";
+ O.indent(IndentLevel) << "}\n";
+ break;
case OptionType::Alias:
default:
throw "Aliases are not allowed in tool option descriptions!";
@@ -1908,10 +1957,10 @@
unsigned IndentLevel, raw_ostream& O) const
{
O.indent(IndentLevel)
- << "throw std::runtime_error(\"" <<
- (d.getNumArgs() >= 1 ? InitPtrToString(d.getArg(0))
- : "Unknown error!")
+ << "PrintError(\""
+ << (d.getNumArgs() >= 1 ? InitPtrToString(d.getArg(0)) : "Unknown error!")
<< "\");\n";
+ O.indent(IndentLevel) << "return 1;\n";
}
void onWarningDag(const DagInit& d,
@@ -1997,7 +2046,12 @@
{
CheckNumberOfArguments(Dag, 1);
const std::string& Name = InitPtrToString(Dag.getArg(0));
- const OptionDescription& D = OptDescs.FindListOrParameter(Name);
+ const OptionDescription& D = OptDescs.FindParameterListOrParameter(Name);
+
+ if (D.isSwitchList()) {
+ throw std::runtime_error
+ ("forward_value is not allowed with switch_list");
+ }
if (D.isParameter()) {
O.indent(IndentLevel) << "vec.push_back(std::make_pair("
@@ -2005,8 +2059,9 @@
<< D.GenVariableName() << "));\n";
}
else {
- O.indent(IndentLevel) << "for (cl::list<std::string>::iterator B = "
- << D.GenVariableName() << ".begin(), \n";
+ O.indent(IndentLevel) << "for (" << D.GenTypeDeclaration()
+ << "::iterator B = " << D.GenVariableName()
+ << ".begin(), \n";
O.indent(IndentLevel + Indent1) << " E = " << D.GenVariableName()
<< ".end(); B != E; ++B)\n";
O.indent(IndentLevel) << "{\n";
@@ -2026,7 +2081,7 @@
CheckNumberOfArguments(Dag, 2);
const std::string& Name = InitPtrToString(Dag.getArg(0));
const std::string& Hook = InitPtrToString(Dag.getArg(1));
- const OptionDescription& D = OptDescs.FindListOrParameter(Name);
+ const OptionDescription& D = OptDescs.FindParameterListOrParameter(Name);
O.indent(IndentLevel) << "vec.push_back(std::make_pair("
<< D.GenVariableName() << ".getPosition("
@@ -2099,25 +2154,32 @@
};
void EmitGenerateActionMethodHeader(const ToolDescription& D,
- bool IsJoin, raw_ostream& O)
+ bool IsJoin, bool Naked,
+ raw_ostream& O)
{
+ O.indent(Indent1) << "int GenerateAction(Action& Out,\n";
+
if (IsJoin)
- O.indent(Indent1) << "Action GenerateAction(const PathVector& inFiles,\n";
+ O.indent(Indent2) << "const PathVector& inFiles,\n";
else
- O.indent(Indent1) << "Action GenerateAction(const sys::Path& inFile,\n";
+ O.indent(Indent2) << "const sys::Path& inFile,\n";
- O.indent(Indent2) << "bool HasChildren,\n";
+ O.indent(Indent2) << "const bool HasChildren,\n";
O.indent(Indent2) << "const llvm::sys::Path& TempDir,\n";
O.indent(Indent2) << "const InputLanguagesSet& InLangs,\n";
O.indent(Indent2) << "const LanguageMap& LangMap) const\n";
O.indent(Indent1) << "{\n";
- O.indent(Indent2) << "std::string cmd;\n";
- O.indent(Indent2) << "std::string out_file;\n";
- O.indent(Indent2) << "std::vector<std::pair<unsigned, std::string> > vec;\n";
- O.indent(Indent2) << "bool stop_compilation = !HasChildren;\n";
- O.indent(Indent2) << "bool no_out_file = false;\n";
- O.indent(Indent2) << "const char* output_suffix = \""
- << D.OutputSuffix << "\";\n";
+
+ if (!Naked) {
+ O.indent(Indent2) << "std::string cmd;\n";
+ O.indent(Indent2) << "std::string out_file;\n";
+ O.indent(Indent2)
+ << "std::vector<std::pair<unsigned, std::string> > vec;\n";
+ O.indent(Indent2) << "bool stop_compilation = !HasChildren;\n";
+ O.indent(Indent2) << "bool no_out_file = false;\n";
+ O.indent(Indent2) << "const char* output_suffix = \""
+ << D.OutputSuffix << "\";\n";
+ }
}
// EmitGenerateActionMethod - Emit either a normal or a "join" version of the
@@ -2126,7 +2188,7 @@
const OptionDescriptions& OptDescs,
bool IsJoin, raw_ostream& O) {
- EmitGenerateActionMethodHeader(D, IsJoin, O);
+ EmitGenerateActionMethodHeader(D, IsJoin, /* Naked = */ false, O);
if (!D.CmdLine)
throw "Tool " + D.Name + " has no cmd_line property!";
@@ -2190,8 +2252,9 @@
O.indent(Indent2) << "}\n";
}
- O.indent(Indent2) << "return Action(cmd, this->SortArgs(vec), "
+ O.indent(Indent2) << "Out.Construct(cmd, this->SortArgs(vec), "
<< "stop_compilation, out_file);\n";
+ O.indent(Indent2) << "return 0;\n";
O.indent(Indent1) << "}\n\n";
}
@@ -2201,14 +2264,11 @@
const OptionDescriptions& OptDescs,
raw_ostream& O) {
if (!ToolDesc.isJoin()) {
- O.indent(Indent1) << "Action GenerateAction(const PathVector& inFiles,\n";
- O.indent(Indent2) << "bool HasChildren,\n";
- O.indent(Indent2) << "const llvm::sys::Path& TempDir,\n";
- O.indent(Indent2) << "const InputLanguagesSet& InLangs,\n";
- O.indent(Indent2) << "const LanguageMap& LangMap) const\n";
- O.indent(Indent1) << "{\n";
- O.indent(Indent2) << "throw std::runtime_error(\"" << ToolDesc.Name
+ EmitGenerateActionMethodHeader(ToolDesc, /* IsJoin = */ true,
+ /* Naked = */ true, O);
+ O.indent(Indent2) << "PrintError(\"" << ToolDesc.Name
<< " is not a Join tool!\");\n";
+ O.indent(Indent2) << "return -1;\n";
O.indent(Indent1) << "}\n\n";
}
else {
@@ -2492,8 +2552,15 @@
O.indent(IndentLevel) << OptDesc.GenVariableName() << ".clear();\n";
for (ListInit::const_iterator B = List.begin(), E = List.end();
B != E; ++B) {
- O.indent(IndentLevel) << OptDesc.GenVariableName() << ".push_back(\""
- << InitPtrToString(*B) << "\");\n";
+ const Init* CurElem = *B;
+ if (OptDesc.isSwitchList())
+ CheckBooleanConstant(CurElem);
+
+ O.indent(IndentLevel)
+ << OptDesc.GenVariableName() << ".push_back(\""
+ << (OptDesc.isSwitchList() ? CurElem->getAsString()
+ : InitPtrToString(CurElem))
+ << "\");\n";
}
}
else if (OptDesc.isSwitch()) {
@@ -2565,7 +2632,7 @@
void EmitPreprocessOptions (const RecordKeeper& Records,
const OptionDescriptions& OptDecs, raw_ostream& O)
{
- O << "void PreprocessOptionsLocal() {\n";
+ O << "int PreprocessOptionsLocal() {\n";
const RecordVector& OptionPreprocessors =
Records.getAllDerivedDefinitions("OptionPreprocessor");
@@ -2578,13 +2645,15 @@
false, OptDecs, O);
}
+ O << '\n';
+ O.indent(Indent1) << "return 0;\n";
O << "}\n\n";
}
/// EmitPopulateLanguageMap - Emit the PopulateLanguageMapLocal() function.
void EmitPopulateLanguageMap (const RecordKeeper& Records, raw_ostream& O)
{
- O << "void PopulateLanguageMapLocal(LanguageMap& langMap) {\n";
+ O << "int PopulateLanguageMapLocal(LanguageMap& langMap) {\n";
// Get the relevant field out of RecordKeeper
const Record* LangMapRecord = Records.getDef("LanguageMap");
@@ -2609,6 +2678,8 @@
}
}
+ O << '\n';
+ O.indent(Indent1) << "return 0;\n";
O << "}\n\n";
}
@@ -2626,10 +2697,12 @@
O.indent(IndentLevel) << "ret -= ";
}
else if (OpName == "error") {
+ // TODO: fix this
CheckNumberOfArguments(d, 1);
- O.indent(IndentLevel) << "throw std::runtime_error(\""
+ O.indent(IndentLevel) << "PrintError(\""
<< InitPtrToString(d.getArg(0))
<< "\");\n";
+ O.indent(IndentLevel) << "return -1;\n";
return;
}
else {
@@ -2690,7 +2763,7 @@
const ToolDescriptions& ToolDescs,
raw_ostream& O)
{
- O << "void PopulateCompilationGraphLocal(CompilationGraph& G) {\n";
+ O << "int PopulateCompilationGraphLocal(CompilationGraph& G) {\n";
for (ToolDescriptions::const_iterator B = ToolDescs.begin(),
E = ToolDescs.end(); B != E; ++B)
@@ -2708,17 +2781,21 @@
const std::string& NodeB = Edge->getValueAsString("b");
DagInit& Weight = *Edge->getValueAsDag("weight");
- O.indent(Indent1) << "G.insertEdge(\"" << NodeA << "\", ";
+ O.indent(Indent1) << "if (int ret = G.insertEdge(\"" << NodeA << "\", ";
if (IsDagEmpty(Weight))
O << "new SimpleEdge(\"" << NodeB << "\")";
else
O << "new Edge" << i << "()";
- O << ");\n";
+ O << "))\n";
+ O.indent(Indent2) << "return ret;\n";
+
++i;
}
+ O << '\n';
+ O.indent(Indent1) << "return 0;\n";
O << "}\n\n";
}
@@ -2762,7 +2839,8 @@
CheckNumberOfArguments(Dag, 2);
const std::string& OptName = InitPtrToString(Dag.getArg(0));
const std::string& HookName = InitPtrToString(Dag.getArg(1));
- const OptionDescription& D = OptDescs_.FindOption(OptName);
+ const OptionDescription& D =
+ OptDescs_.FindParameterListOrParameter(OptName);
HookNames_[HookName] = HookInfo(D.isList() ? HookInfo::ListHook
: HookInfo::ArgHook);
@@ -2900,13 +2978,13 @@
O << "struct Plugin : public llvmc::BasePlugin {\n\n";
O.indent(Indent1) << "int Priority() const { return "
<< Priority << "; }\n\n";
- O.indent(Indent1) << "void PreprocessOptions() const\n";
- O.indent(Indent1) << "{ PreprocessOptionsLocal(); }\n\n";
- O.indent(Indent1) << "void PopulateLanguageMap(LanguageMap& langMap) const\n";
- O.indent(Indent1) << "{ PopulateLanguageMapLocal(langMap); }\n\n";
+ O.indent(Indent1) << "int PreprocessOptions() const\n";
+ O.indent(Indent1) << "{ return PreprocessOptionsLocal(); }\n\n";
+ O.indent(Indent1) << "int PopulateLanguageMap(LanguageMap& langMap) const\n";
+ O.indent(Indent1) << "{ return PopulateLanguageMapLocal(langMap); }\n\n";
O.indent(Indent1)
- << "void PopulateCompilationGraph(CompilationGraph& graph) const\n";
- O.indent(Indent1) << "{ PopulateCompilationGraphLocal(graph); }\n"
+ << "int PopulateCompilationGraph(CompilationGraph& graph) const\n";
+ O.indent(Indent1) << "{ return PopulateCompilationGraphLocal(graph); }\n"
<< "};\n\n"
<< "static llvmc::RegisterPlugin<Plugin> RP;\n\n";
}
@@ -2916,6 +2994,7 @@
void EmitIncludes(raw_ostream& O) {
O << "#include \"llvm/CompilerDriver/BuiltinOptions.h\"\n"
<< "#include \"llvm/CompilerDriver/CompilationGraph.h\"\n"
+ << "#include \"llvm/CompilerDriver/Error.h\"\n"
<< "#include \"llvm/CompilerDriver/ForceLinkageMacros.h\"\n"
<< "#include \"llvm/CompilerDriver/Plugin.h\"\n"
<< "#include \"llvm/CompilerDriver/Tool.h\"\n\n"
Modified: llvm/branches/wendling/eh/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/NeonEmitter.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/NeonEmitter.cpp Sat Jul 31 19:59:02 2010
@@ -1016,6 +1016,8 @@
throw "unhandled type!";
break;
}
+ assert(0 && "unreachable");
+ return 0;
}
/// runHeader - Emit a file with sections defining:
Modified: llvm/branches/wendling/eh/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/TableGen/TableGen.cpp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/TableGen/TableGen.cpp (original)
+++ llvm/branches/wendling/eh/utils/TableGen/TableGen.cpp Sat Jul 31 19:59:02 2010
@@ -67,7 +67,7 @@
GenIntrinsic,
GenTgtIntrinsic,
GenLLVMCConf,
- GenEDHeader, GenEDInfo,
+ GenEDInfo,
GenArmNeon,
GenArmNeonSema,
PrintEnums
@@ -128,8 +128,6 @@
"Generate Clang AST statement nodes"),
clEnumValN(GenLLVMCConf, "gen-llvmc",
"Generate LLVMC configuration library"),
- clEnumValN(GenEDHeader, "gen-enhanced-disassembly-header",
- "Generate enhanced disassembly info header"),
clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info",
"Generate enhanced disassembly info"),
clEnumValN(GenArmNeon, "gen-arm-neon",
@@ -301,9 +299,6 @@
case GenLLVMCConf:
LLVMCConfigurationEmitter(Records).run(Out);
break;
- case GenEDHeader:
- EDEmitter(Records).runHeader(Out);
- break;
case GenEDInfo:
EDEmitter(Records).run(Out);
break;
Modified: llvm/branches/wendling/eh/utils/buildit/GNUmakefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/buildit/GNUmakefile?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/buildit/GNUmakefile (original)
+++ llvm/branches/wendling/eh/utils/buildit/GNUmakefile Sat Jul 31 19:59:02 2010
@@ -49,8 +49,9 @@
# Default to not install libLTO.dylib.
INSTALL_LIBLTO := no
-# Default to do a native build, not a cross-build for an ARM host.
+# Default to do a native build, not a cross-build for an ARM host or simulator.
ARM_HOSTED_BUILD := no
+IOS_SIM_BUILD := no
ifndef RC_ProjectSourceVersion
RC_ProjectSourceVersion = 9999
@@ -66,12 +67,19 @@
$(SRC)/utils/buildit/build_llvm "$(RC_ARCHS)" "$(TARGETS)" \
$(SRC) $(PREFIX) $(DSTROOT) $(SYMROOT) \
$(ENABLE_ASSERTIONS) $(LLVM_OPTIMIZED) $(INSTALL_LIBLTO) \
- $(ARM_HOSTED_BUILD) \
+ $(ARM_HOSTED_BUILD) $(IOS_SIM_BUILD) \
$(RC_ProjectSourceVersion) $(RC_ProjectSourceSubversion)
EmbeddedHosted:
$(MAKE) ARM_HOSTED_BUILD=yes PREFIX=/usr install
+# When building for the iOS simulator, MACOSX_DEPLOYMENT_TARGET is not set
+# by default, but it needs to be set when building tools that run on the host
+# (e.g., tblgen), so set it here.
+EmbeddedSim:
+ export MACOSX_DEPLOYMENT_TARGET=`sw_vers -productVersion`; \
+ $(MAKE) IOS_SIM_BUILD=yes PREFIX=/usr install
+
# installhdrs does nothing, because the headers aren't useful until
# the compiler is installed.
installhdrs:
@@ -120,4 +128,4 @@
$(OBJROOT) $(SYMROOT) $(DSTROOT):
mkdir -p $@
-.PHONY: install installsrc clean EmbeddedHosted
+.PHONY: install installsrc clean EmbeddedHosted EmbeddedSim
Modified: llvm/branches/wendling/eh/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/buildit/build_llvm?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/buildit/build_llvm (original)
+++ llvm/branches/wendling/eh/utils/buildit/build_llvm Sat Jul 31 19:59:02 2010
@@ -49,11 +49,14 @@
# A yes/no parameter that controls whether to cross-build for an ARM host.
ARM_HOSTED_BUILD="${10}"
+# A yes/no parameter that controls whether to cross-build for the iOS simulator
+IOS_SIM_BUILD="${11}"
+
# The version number of the submission, e.g. 1007.
-LLVM_SUBMIT_VERSION="${11}"
+LLVM_SUBMIT_VERSION="${12}"
# The subversion number of the submission, e.g. 03.
-LLVM_SUBMIT_SUBVERSION="${12}"
+LLVM_SUBMIT_SUBVERSION="${13}"
# The current working directory is where the build will happen. It may already
# contain a partial result of an interrupted build, in which case this script
@@ -97,7 +100,7 @@
# Try to use the platform llvm-gcc. Fall back to gcc if it's not available.
for prog in gcc g++ ; do
P=$DIR/bin/arm-apple-darwin$DARWIN_VERS-${prog}
- T=`xcrun -find llvm-${prog}`
+ T=`xcrun -sdk $SDKROOT -find llvm-${prog}`
if [ "x$T" = "x" ] ; then
T=`xcrun -sdk $SDKROOT -find ${prog}`
fi
@@ -124,6 +127,10 @@
if [ "$ARM_HOSTED_BUILD" = yes ]; then
configure_opts="--enable-targets=arm --host=arm-apple-darwin10 \
--target=arm-apple-darwin10 --build=i686-apple-darwin10"
+elif [ "$IOS_SIM_BUILD" = yes ]; then
+ # Use a non-standard "darwin_sim" host triple to trigger a cross-build.
+ configure_opts="--enable-targets=x86 --host=i686-apple-darwin_sim \
+ --build=i686-apple-darwin10"
else
configure_opts="--enable-targets=arm,x86,powerpc,cbe"
fi
@@ -317,9 +324,20 @@
mkdir -p $DT_HOME/lib
mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib
+ # Save a copy of the unstripped dylib
+ mkdir -p $SYM_DIR/Developer/usr/lib
+ cp $DT_HOME/lib/libLTO.dylib $SYM_DIR/Developer/usr/lib/libLTO.dylib
+
# Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
# PPC objects!
strip -arch all -Sl $DT_HOME/lib/libLTO.dylib
+
+ if [ "x$DISABLE_USR_LINKS" == "x" ]; then
+ # Add a symlink in /usr/lib for B&I.
+ mkdir -p $DEST_DIR/usr/lib/
+ (cd $DEST_DIR/usr/lib && \
+ ln -s ../../Developer/usr/lib/libLTO.dylib ./libLTO.dylib)
+ fi
else
rm -f lib/libLTO.dylib
fi
@@ -350,15 +368,6 @@
rm -rf $DEST_DIR$DEST_ROOT/docs
################################################################################
-# symlinks so that B&I can find things
-
-if [ "$INSTALL_LIBLTO" = "yes" ]; then
- mkdir -p $DEST_DIR/usr/lib/
- cd $DEST_DIR/usr/lib && \
- ln -s ../../Developer/usr/lib/libLTO.dylib ./libLTO.dylib
-fi
-
-################################################################################
# w00t! Done!
exit 0
Modified: llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/lit.cfg?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/lit.cfg (original)
+++ llvm/branches/wendling/eh/utils/lit/lit/ExampleTests/lit.cfg Sat Jul 31 19:59:02 2010
@@ -21,3 +21,6 @@
# target_triple: Used by ShTest and TclTest formats for XFAIL checks.
config.target_triple = 'foo'
+
+# available_features: Used by ShTest and TclTest formats for REQUIRES checks.
+config.available_features = ['some-feature-name']
Modified: llvm/branches/wendling/eh/utils/lit/lit/TestRunner.py
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/lit/lit/TestRunner.py?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/lit/lit/TestRunner.py (original)
+++ llvm/branches/wendling/eh/utils/lit/lit/TestRunner.py Sat Jul 31 19:59:02 2010
@@ -422,6 +422,7 @@
script = []
xfails = []
xtargets = []
+ requires = []
for ln in open(sourcepath):
if 'RUN:' in ln:
# Isolate the command to run.
@@ -442,6 +443,9 @@
elif 'XTARGET:' in ln:
items = ln[ln.index('XTARGET:') + 8:].split(',')
xtargets.extend([s.strip() for s in items])
+ elif 'REQUIRES:' in ln:
+ items = ln[ln.index('REQUIRES:') + 9:].split(',')
+ requires.extend([s.strip() for s in items])
elif 'END.' in ln:
# Check for END. lines.
if ln[ln.index('END.'):].strip() == 'END.':
@@ -461,9 +465,18 @@
if not script:
return (Test.UNRESOLVED, "Test has no run line!")
+ # Check for unterminated run lines.
if script[-1][-1] == '\\':
return (Test.UNRESOLVED, "Test has unterminated run lines (with '\\')")
+ # Check that we have the required features:
+ missing_required_features = [f for f in requires
+ if f not in test.config.available_features]
+ if missing_required_features:
+ msg = ', '.join(missing_required_features)
+ return (Test.UNSUPPORTED,
+ "Test requires the following features: %s" % msg)
+
isXFail = isExpectedFail(xfails, xtargets, test.suite.config.target_triple)
return script,isXFail,tmpBase,execdir
Modified: llvm/branches/wendling/eh/utils/lit/lit/TestingConfig.py
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/lit/lit/TestingConfig.py?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/lit/lit/TestingConfig.py (original)
+++ llvm/branches/wendling/eh/utils/lit/lit/TestingConfig.py Sat Jul 31 19:59:02 2010
@@ -28,7 +28,8 @@
on_clone = None,
test_exec_root = None,
test_source_root = None,
- excludes = [])
+ excludes = [],
+ available_features = [])
if os.path.exists(path):
# FIXME: Improve detection and error reporting of errors in the
@@ -54,7 +55,8 @@
def __init__(self, parent, name, suffixes, test_format,
environment, substitutions, unsupported, on_clone,
- test_exec_root, test_source_root, excludes):
+ test_exec_root, test_source_root, excludes,
+ available_features):
self.parent = parent
self.name = str(name)
self.suffixes = set(suffixes)
@@ -66,6 +68,7 @@
self.test_exec_root = test_exec_root
self.test_source_root = test_source_root
self.excludes = set(excludes)
+ self.available_features = set(available_features)
def clone(self, path):
# FIXME: Chain implementations?
@@ -75,7 +78,7 @@
self.environment, self.substitutions,
self.unsupported, self.on_clone,
self.test_exec_root, self.test_source_root,
- self.excludes)
+ self.excludes, self.available_features)
if cfg.on_clone:
cfg.on_clone(self, cfg, path)
return cfg
Modified: llvm/branches/wendling/eh/utils/valgrind/i386-pc-linux-gnu.supp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/valgrind/i386-pc-linux-gnu.supp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/valgrind/i386-pc-linux-gnu.supp (original)
+++ llvm/branches/wendling/eh/utils/valgrind/i386-pc-linux-gnu.supp Sat Jul 31 19:59:02 2010
@@ -5,3 +5,31 @@
fun:_ZN83_GLOBAL_*PassRegistrar12RegisterPassERKN4llvm8PassInfoE
fun:_ZN4llvm8PassInfo12registerPassEv
}
+
+# Python false positives according to
+# http://svn.python.org/projects/python/trunk/Misc/README.valgrind
+
+{
+ ADDRESS_IN_RANGE/Invalid read of size 4
+ Memcheck:Addr4
+ obj:/usr/bin/python2.5
+}
+
+{
+ ADDRESS_IN_RANGE/Invalid read of size 4
+ Memcheck:Value4
+ obj:/usr/bin/python2.5
+}
+
+{
+ ADDRESS_IN_RANGE/Conditional jump or move depends on uninitialised value
+ Memcheck:Cond
+ obj:/usr/bin/python2.5
+}
+
+{
+ We don't care if python leaks
+ Memcheck:Leak
+ fun:malloc
+ obj:/usr/bin/python2.5
+}
Modified: llvm/branches/wendling/eh/utils/valgrind/x86_64-pc-linux-gnu.supp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/valgrind/x86_64-pc-linux-gnu.supp?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/valgrind/x86_64-pc-linux-gnu.supp (original)
+++ llvm/branches/wendling/eh/utils/valgrind/x86_64-pc-linux-gnu.supp Sat Jul 31 19:59:02 2010
@@ -5,3 +5,31 @@
fun:_ZN83_GLOBAL_*PassRegistrar12RegisterPassERKN4llvm8PassInfoE
fun:_ZN4llvm8PassInfo12registerPassEv
}
+
+# Python false positives according to
+# http://svn.python.org/projects/python/trunk/Misc/README.valgrind
+
+{
+ ADDRESS_IN_RANGE/Invalid read of size 4
+ Memcheck:Addr4
+ obj:/usr/bin/python2.5
+}
+
+{
+ ADDRESS_IN_RANGE/Invalid read of size 4
+ Memcheck:Value8
+ obj:/usr/bin/python2.5
+}
+
+{
+ ADDRESS_IN_RANGE/Conditional jump or move depends on uninitialised value
+ Memcheck:Cond
+ obj:/usr/bin/python2.5
+}
+
+{
+ We don't care if python leaks
+ Memcheck:Leak
+ fun:malloc
+ obj:/usr/bin/python2.5
+}
Modified: llvm/branches/wendling/eh/utils/vim/llvm.vim
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/wendling/eh/utils/vim/llvm.vim?rev=109963&r1=109962&r2=109963&view=diff
==============================================================================
--- llvm/branches/wendling/eh/utils/vim/llvm.vim (original)
+++ llvm/branches/wendling/eh/utils/vim/llvm.vim Sat Jul 31 19:59:02 2010
@@ -64,7 +64,7 @@
syn keyword llvmError getresult big little endian begin end
" Misc syntax.
-syn match llvmIgnore /[%@]\d\+\>/
+syn match llvmNoName /[%@]\d\+\>/
syn match llvmNumber /-\?\<\d\+\>/
syn match llvmFloat /-\?\<\d\+\.\d*\(e[+-]\d\+\)\?\>/
syn match llvmFloat /\<0x\x\+\>/
@@ -99,7 +99,7 @@
HiLink llvmKeyword Keyword
HiLink llvmBoolean Boolean
HiLink llvmFloat Float
- HiLink llvmIgnore Ignore
+ HiLink llvmNoName Identifier
HiLink llvmConstant Constant
HiLink llvmSpecialComment SpecialComment
HiLink llvmError Error
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