[llvm-branch-commits] [llvm-branch] r95937 - in /llvm/branches/Apple/Hermes: include/llvm/CodeGen/MachineBasicBlock.h include/llvm/CodeGen/MachineOperand.h lib/CodeGen/DeadMachineInstructionElim.cpp lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/MachineBasicBlock.cpp lib/CodeGen/MachineInstr.cpp lib/CodeGen/RegAllocLocal.cpp lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/TwoAddressInstructionPass.cpp
Dale Johannesen
dalej at apple.com
Thu Feb 11 15:50:05 PST 2010
Author: johannes
Date: Thu Feb 11 17:50:05 2010
New Revision: 95937
URL: http://llvm.org/viewvc/llvm-project?rev=95937&view=rev
Log:
Merge recent debug info fixes.
--- Merging r95579 into '.':
U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- Merging r95730 into '.':
U lib/CodeGen/MachineBasicBlock.cpp
U lib/CodeGen/RegAllocLocal.cpp
U lib/CodeGen/SelectionDAG/FastISel.cpp
--- Merging r95735 into '.':
U include/llvm/CodeGen/MachineOperand.h
U lib/CodeGen/MachineInstr.cpp
--- Merging r95736 into '.':
U include/llvm/CodeGen/MachineBasicBlock.h
U lib/CodeGen/DeadMachineInstructionElim.cpp
--- Merging r95632 into '.':
G include/llvm/CodeGen/MachineOperand.h
--- Merging r95739 into '.':
U lib/CodeGen/LiveIntervalAnalysis.cpp
U lib/CodeGen/SimpleRegisterCoalescing.cpp
--- Merging r95749 into '.':
G lib/CodeGen/LiveIntervalAnalysis.cpp
--- Merging r95811 into '.':
G lib/CodeGen/LiveIntervalAnalysis.cpp
--- Merging r95814 into '.':
U lib/CodeGen/TwoAddressInstructionPass.cpp
--- Merging r95818 into '.':
G include/llvm/CodeGen/MachineOperand.h
--- Merging r95819 into '.':
G lib/CodeGen/SimpleRegisterCoalescing.cpp
--- Merging r95889 into '.':
G lib/CodeGen/TwoAddressInstructionPass.cpp
--- Merging r95890 into '.':
G lib/CodeGen/DeadMachineInstructionElim.cpp
Modified:
llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineBasicBlock.h
llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineOperand.h
llvm/branches/Apple/Hermes/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/MachineBasicBlock.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/MachineInstr.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/RegAllocLocal.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/Apple/Hermes/lib/CodeGen/TwoAddressInstructionPass.cpp
Modified: llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineBasicBlock.h?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineBasicBlock.h Thu Feb 11 17:50:05 2010
@@ -338,7 +338,7 @@
bool isCond);
/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
- /// any DEBUG_VALUE instructions. Return UnknownLoc if there is none.
+ /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
DebugLoc findDebugLoc(MachineBasicBlock::iterator &MBBI);
// Debugging methods.
Modified: llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineOperand.h?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/branches/Apple/Hermes/include/llvm/CodeGen/MachineOperand.h Thu Feb 11 17:50:05 2010
@@ -220,7 +220,6 @@
bool isDebug() const {
assert(isReg() && "Wrong MachineOperand accessor");
- assert(!isDef() && "Wrong MachineOperand accessor");
return IsDebug;
}
@@ -246,11 +245,13 @@
void setIsUse(bool Val = true) {
assert(isReg() && "Wrong MachineOperand accessor");
+ assert((Val || !isDebug()) && "Marking a debug operation as def");
IsDef = !Val;
}
void setIsDef(bool Val = true) {
assert(isReg() && "Wrong MachineOperand accessor");
+ assert((!Val || !isDebug()) && "Marking a debug operation as def");
IsDef = Val;
}
@@ -261,6 +262,7 @@
void setIsKill(bool Val = true) {
assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
+ assert((!Val || !isDebug()) && "Marking a debug operation as kill");
IsKill = Val;
}
@@ -376,7 +378,7 @@
/// the setReg method should be used.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
bool isKill = false, bool isDead = false,
- bool isUndef = false);
+ bool isUndef = false, bool isDebug = false);
//===--------------------------------------------------------------------===//
// Construction methods.
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/DeadMachineInstructionElim.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/DeadMachineInstructionElim.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/DeadMachineInstructionElim.cpp Thu Feb 11 17:50:05 2010
@@ -112,15 +112,15 @@
MachineInstr *MI = &*MII;
if (MI->isDebugValue()) {
- // Don't delete the DEBUG_VALUE itself, but if its Value operand is
+ // Don't delete the DBG_VALUE itself, but if its Value operand is
// a vreg and this is the only use, substitute an undef operand;
// the former operand will then be deleted normally.
if (MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
unsigned Reg = MI->getOperand(0).getReg();
- MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
- assert(I != MRI->use_end());
- if (++I == MRI->use_end())
- // only one use, which must be this DEBUG_VALUE.
+ MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
+ if (I == MRI->use_nodbg_end())
+ // All uses are DBG_VALUEs. Nullify this one; if we find
+ // others later we will nullify them then.
MI->getOperand(0).setReg(0U);
}
}
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Feb 11 17:50:05 2010
@@ -512,6 +512,8 @@
baseIndex = baseIndex.getNextIndex();
while (++mi != MBB->end()) {
+ if (mi->isDebugValue())
+ continue;
if (getInstructionFromIndex(baseIndex) == 0)
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
@@ -527,8 +529,8 @@
end = baseIndex.getDefIndex();
} else {
// Another instruction redefines the register before it is ever read.
- // Then the register is essentially dead at the instruction that defines
- // it. Hence its interval is:
+ // Then the register is essentially dead at the instruction that
+ // defines it. Hence its interval is:
// [defSlot(def), defSlot(def)+1)
DEBUG(dbgs() << " dead");
end = start.getStoreIndex();
@@ -606,8 +608,16 @@
SlotIndex end = baseIndex;
bool SeenDefUse = false;
-
- while (mi != MBB->end()) {
+
+ MachineBasicBlock::iterator E = MBB->end();
+ while (mi != E) {
+ if (mi->isDebugValue()) {
+ ++mi;
+ if (mi != E && !mi->isDebugValue()) {
+ baseIndex = indexes_->getNextNonNullIndex(baseIndex);
+ }
+ continue;
+ }
if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " killed");
end = baseIndex.getDefIndex();
@@ -625,7 +635,7 @@
}
++mi;
- if (mi != MBB->end()) {
+ if (mi != E && !mi->isDebugValue()) {
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
}
}
@@ -1056,7 +1066,7 @@
// If this is the rematerializable definition MI itself and
// all of its uses are rematerialized, simply delete it.
if (MI == ReMatOrigDefMI && CanDelete) {
- DEBUG(dbgs() << "\t\t\t\tErasing re-materlizable def: "
+ DEBUG(dbgs() << "\t\t\t\tErasing re-materializable def: "
<< MI << '\n');
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
@@ -1299,6 +1309,12 @@
MachineInstr *MI = &*ri;
MachineOperand &O = ri.getOperand();
++ri;
+ if (MI->isDebugValue()) {
+ // Remove debug info for now.
+ O.setReg(0U);
+ DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
+ continue;
+ }
assert(!O.isImplicit() && "Spilling register that's used as implicit use?");
SlotIndex index = getInstructionIndex(MI);
if (index < start || index >= end)
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/MachineBasicBlock.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/MachineBasicBlock.cpp Thu Feb 11 17:50:05 2010
@@ -540,7 +540,7 @@
}
/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
-/// any DEBUG_VALUE instructions. Return UnknownLoc if there is none.
+/// any DBG_VALUE instructions. Return UnknownLoc if there is none.
DebugLoc
MachineBasicBlock::findDebugLoc(MachineBasicBlock::iterator &MBBI) {
DebugLoc DL;
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/MachineInstr.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/MachineInstr.cpp Thu Feb 11 17:50:05 2010
@@ -127,7 +127,8 @@
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
- bool isKill, bool isDead, bool isUndef) {
+ bool isKill, bool isDead, bool isUndef,
+ bool isDebug) {
// If this operand is already a register operand, use setReg to update the
// register's use/def lists.
if (isReg()) {
@@ -152,6 +153,7 @@
IsDead = isDead;
IsUndef = isUndef;
IsEarlyClobber = false;
+ IsDebug = isDebug;
SubReg = 0;
}
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/RegAllocLocal.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/RegAllocLocal.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/RegAllocLocal.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/RegAllocLocal.cpp Thu Feb 11 17:50:05 2010
@@ -841,8 +841,8 @@
}
}
- // If a DEBUG_VALUE says something is located in a spilled register,
- // change the DEBUG_VALUE to be undef, which prevents the register
+ // If a DBG_VALUE says something is located in a spilled register,
+ // change the DBG_VALUE to be undef, which prevents the register
// from being reloaded here. Doing that would change the generated
// code, unless another use immediately follows this instruction.
if (MI->isDebugValue() &&
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Feb 11 17:50:05 2010
@@ -345,7 +345,7 @@
if (MDNode *Dbg = DI->getMetadata("dbg"))
MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
}
- // Building the map above is target independent. Generating DEBUG_VALUE
+ // Building the map above is target independent. Generating DBG_VALUE
// inline is target dependent; do this now.
(void)TargetSelectInstruction(cast<Instruction>(I));
return true;
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Feb 11 17:50:05 2010
@@ -3777,6 +3777,8 @@
MDNode *Variable = DI.getVariable();
Value *Address = DI.getAddress();
+ if (!Address)
+ return 0;
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
Address = BCI->getOperand(0);
AllocaInst *AI = dyn_cast<AllocaInst>(Address);
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Feb 11 17:50:05 2010
@@ -375,8 +375,9 @@
// If some of the uses of IntA.reg is already coalesced away, return false.
// It's not possible to determine whether it's safe to perform the coalescing.
- for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
- UE = mri_->use_end(); UI != UE; ++UI) {
+ for (MachineRegisterInfo::use_nodbg_iterator UI =
+ mri_->use_nodbg_begin(IntA.reg),
+ UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
MachineInstr *UseMI = &*UI;
SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
@@ -430,6 +431,12 @@
++UI;
if (JoinedCopies.count(UseMI))
continue;
+ if (UseMI->isDebugValue()) {
+ // FIXME These don't have an instruction index. Not clear we have enough
+ // info to decide whether to do this replacement or not. For now do it.
+ UseMO.setReg(NewReg);
+ continue;
+ }
SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
if (ULR == IntA.end() || ULR->valno != AValNo)
@@ -1029,8 +1036,9 @@
unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
unsigned Length = li_->getApproximateInstructionCount(DstInt);
if (Length > Threshold &&
- (((float)std::distance(mri_->use_begin(DstInt.reg),
- mri_->use_end()) / Length) < (1.0 / Threshold)))
+ (((float)std::distance(mri_->use_nodbg_begin(DstInt.reg),
+ mri_->use_nodbg_end()) / Length) <
+ (1.0 / Threshold)))
return false;
// If the virtual register live interval extends into a loop, turn down
@@ -1079,15 +1087,16 @@
MachineBasicBlock *CopyMBB,
LiveInterval &DstInt,
LiveInterval &SrcInt) {
- // If the virtual register live interval is long but it has low use desity,
+ // If the virtual register live interval is long but it has low use density,
// do not join them, instead mark the physical register as its allocation
// preference.
const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
unsigned Length = li_->getApproximateInstructionCount(SrcInt);
if (Length > Threshold &&
- (((float)std::distance(mri_->use_begin(SrcInt.reg),
- mri_->use_end()) / Length) < (1.0 / Threshold)))
+ (((float)std::distance(mri_->use_nodbg_begin(SrcInt.reg),
+ mri_->use_nodbg_end()) / Length) <
+ (1.0 / Threshold)))
return false;
if (SrcInt.empty())
@@ -1140,10 +1149,10 @@
unsigned LargeSize = li_->getApproximateInstructionCount(LargeInt);
unsigned SmallSize = li_->getApproximateInstructionCount(SmallInt);
if (SmallSize > Threshold || LargeSize > Threshold)
- if ((float)std::distance(mri_->use_begin(SmallReg),
- mri_->use_end()) / SmallSize <
- (float)std::distance(mri_->use_begin(LargeReg),
- mri_->use_end()) / LargeSize)
+ if ((float)std::distance(mri_->use_nodbg_begin(SmallReg),
+ mri_->use_nodbg_end()) / SmallSize <
+ (float)std::distance(mri_->use_nodbg_begin(LargeReg),
+ mri_->use_nodbg_end()) / LargeSize)
return false;
return true;
}
@@ -1164,6 +1173,8 @@
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
E = mri_->reg_end(); I != E; ++I) {
MachineOperand &O = I.getOperand();
+ if (O.isDebug())
+ continue;
MachineInstr *MI = &*I;
if (MI == CopyMI || JoinedCopies.count(MI))
continue;
@@ -1630,8 +1641,8 @@
unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
float Ratio = 1.0 / Threshold;
if (Length > Threshold &&
- (((float)std::distance(mri_->use_begin(JoinVReg),
- mri_->use_end()) / Length) < Ratio)) {
+ (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
+ mri_->use_nodbg_end()) / Length) < Ratio)) {
mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
++numAborts;
DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
@@ -2564,8 +2575,8 @@
return !RegClassA->contains(RegB);
}
-/// lastRegisterUse - Returns the last use of the specific register between
-/// cycles Start and End or NULL if there are no uses.
+/// lastRegisterUse - Returns the last (non-debug) use of the specific register
+/// between cycles Start and End or NULL if there are no uses.
MachineOperand *
SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
SlotIndex End,
@@ -2574,8 +2585,8 @@
UseIdx = SlotIndex();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
MachineOperand *LastUse = NULL;
- for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
- E = mri_->use_end(); I != E; ++I) {
+ for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
+ E = mri_->use_nodbg_end(); I != E; ++I) {
MachineOperand &Use = I.getOperand();
MachineInstr *UseMI = Use.getParent();
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
Modified: llvm/branches/Apple/Hermes/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=95937&r1=95936&r2=95937&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Feb 11 17:50:05 2010
@@ -213,6 +213,9 @@
unsigned NumVisited = 0;
for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
MachineInstr *OtherMI = I;
+ // DBG_VALUE cannot be counted against the limit.
+ if (OtherMI->isDebugValue())
+ continue;
if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
return false;
++NumVisited;
@@ -451,11 +454,11 @@
const TargetInstrInfo *TII,
bool &IsCopy,
unsigned &DstReg, bool &IsDstPhys) {
- MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
- if (UI == MRI->use_end())
+ MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg);
+ if (UI == MRI->use_nodbg_end())
return 0;
MachineInstr &UseMI = *UI;
- if (++UI != MRI->use_end())
+ if (++UI != MRI->use_nodbg_end())
// More than one use.
return 0;
if (UseMI.getParent() != MBB)
@@ -923,6 +926,10 @@
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ) {
MachineBasicBlock::iterator nmi = llvm::next(mi);
+ if (mi->isDebugValue()) {
+ mi = nmi;
+ continue;
+ }
const TargetInstrDesc &TID = mi->getDesc();
bool FirstTied = true;
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