[llvm-branch-commits] [llvm-branch] r101617 - in /llvm/branches/Apple/Hermes: ./ lib/Target/ARM/ARMISelLowering.cpp

[Bob Wilson]

Author: bwilson
Date: Sat Apr 17 00:40:20 2010
New Revision: 101617

URL: http://llvm.org/viewvc/llvm-project?rev=101617&view=rev
Log:
--- Merging r101615 into '.':
U    lib/Target/ARM/ARMISelLowering.cpp

Modified:
    llvm/branches/Apple/Hermes/   (props changed)
    llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp

Propchange: llvm/branches/Apple/Hermes/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Apr 17 00:40:20 2010
@@ -1 +1 @@
-/llvm/trunk:96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181,101282,101303,101383
+/llvm/trunk:96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181,101282,101303,101383,101615

Modified: llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp?rev=101617&r1=101616&r2=101617&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp Sat Apr 17 00:40:20 2010
@@ -2150,18 +2150,25 @@
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
 }
 
+/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
+/// expand a bit convert where either the source or destination type is i64 to
+/// use a VMOVDRR or VMOVRRD node.  This should not be done when the non-i64
+/// operand type is illegal (e.g., v2f32 for a target that doesn't support
+/// vectors), since the legalizer won't know what to do with that.
 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  DebugLoc dl = N->getDebugLoc();
   SDValue Op = N->getOperand(0);
 
-  // Do not create a VMOVDRR or VMOVRRD node if the operand type is not
-  // legal.  The legalizer won't know what to do with that.
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  if (!TLI.isTypeLegal(Op.getValueType()))
-    return SDValue();
+  // This function is only supposed to be called for i64 types, either as the
+  // source or destination of the bit convert.
+  EVT SrcVT = Op.getValueType();
+  EVT DstVT = N->getValueType(0);
+  assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
+         "ExpandBIT_CONVERT called for non-i64 type");
 
-  DebugLoc dl = N->getDebugLoc();
-  if (N->getValueType(0) == MVT::f64) {
-    // Turn i64->f64 into VMOVDRR.
+  // Turn i64->f64 into VMOVDRR.
+  if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
     SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
                              DAG.getConstant(0, MVT::i32));
     SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
@@ -2170,11 +2177,14 @@
   }
 
   // Turn f64->i64 into VMOVRRD.
-  SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
-                            DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
+  if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
+    SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
+                              DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
+    // Merge the pieces into a single i64 value.
+    return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
+  }
 
-  // Merge the pieces into a single i64 value.
-  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
+  return SDValue();
 }
 
 /// getZeroVector - Returns a vector of specified type with all zero elements.