[llvm-branch-commits] [llvm-branch] r101616 - in /llvm/branches/Apple/Morbo: ./ lib/Target/ARM/ARMISelLowering.cpp

[Bob Wilson]

Author: bwilson
Date: Sat Apr 17 00:37:18 2010
New Revision: 101616

URL: http://llvm.org/viewvc/llvm-project?rev=101616&view=rev
Log:
--- Merging r101615 into '.':
U    lib/Target/ARM/ARMISelLowering.cpp

Modified:
    llvm/branches/Apple/Morbo/   (props changed)
    llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp

Propchange: llvm/branches/Apple/Morbo/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Apr 17 00:37:18 2010
@@ -1,2 +1,2 @@
 /llvm/branches/Apple/Hermes:96832,96835,96858,96870,96876,96879
-/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100454-100455,100457,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736,100742,100751,100768-100769,100771,100781,100797,100804,10
 0837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101303,101314-101315,101317,101331,101343,101383,101392,101420,101453,101604
+/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100454-100455,100457,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736,100742,100751,100768-100769,100771,100781,100797,100804,10
 0837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101303,101314-101315,101317,101331,101343,101383,101392,101420,101453,101604,101615

Modified: llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp?rev=101616&r1=101615&r2=101616&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp Sat Apr 17 00:37:18 2010
@@ -2215,18 +2215,25 @@
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
 }
 
+/// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
+/// expand a bit convert where either the source or destination type is i64 to
+/// use a VMOVDRR or VMOVRRD node.  This should not be done when the non-i64
+/// operand type is illegal (e.g., v2f32 for a target that doesn't support
+/// vectors), since the legalizer won't know what to do with that.
 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  DebugLoc dl = N->getDebugLoc();
   SDValue Op = N->getOperand(0);
 
-  // Do not create a VMOVDRR or VMOVRRD node if the operand type is not
-  // legal.  The legalizer won't know what to do with that.
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
-  if (!TLI.isTypeLegal(Op.getValueType()))
-    return SDValue();
+  // This function is only supposed to be called for i64 types, either as the
+  // source or destination of the bit convert.
+  EVT SrcVT = Op.getValueType();
+  EVT DstVT = N->getValueType(0);
+  assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
+         "ExpandBIT_CONVERT called for non-i64 type");
 
-  DebugLoc dl = N->getDebugLoc();
-  if (N->getValueType(0) == MVT::f64) {
-    // Turn i64->f64 into VMOVDRR.
+  // Turn i64->f64 into VMOVDRR.
+  if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
     SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
                              DAG.getConstant(0, MVT::i32));
     SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
@@ -2235,11 +2242,14 @@
   }
 
   // Turn f64->i64 into VMOVRRD.
-  SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
-                            DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
+  if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
+    SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
+                              DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
+    // Merge the pieces into a single i64 value.
+    return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
+  }
 
-  // Merge the pieces into a single i64 value.
-  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
+  return SDValue();
 }
 
 /// getZeroVector - Returns a vector of specified type with all zero elements.