[llvm-branch-commits] [llvm-branch] r83219 - in /llvm/branches/Apple/Leela: lib/CodeGen/PostRASchedulerList.cpp lib/Target/ARM/ARM.td lib/Target/ARM/ARMSubtarget.cpp test/CodeGen/ARM/2009-08-21-PostRAKill.ll test/CodeGen/ARM/2009-08-21-PostRAKill2.ll test/CodeGen/ARM/2009-08-21-PostRAKill3.ll test/CodeGen/ARM/2009-08-21-PostRAKill4.ll test/CodeGen/ARM/2009-09-01-PostRAProlog.ll test/CodeGen/X86/break-anti-dependencies.ll
Bob Wilson
bob.wilson at apple.com
Thu Oct 1 15:26:47 PDT 2009
Author: bwilson
Date: Thu Oct 1 17:26:47 2009
New Revision: 83219
URL: http://llvm.org/viewvc/llvm-project?rev=83219&view=rev
Log:
$ svn merge -c 83215 https://bwilson@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r83215 into '.':
U test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill.ll
U test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
A test/CodeGen/X86/break-anti-dependencies.ll
U lib/Target/ARM/ARMSubtarget.cpp
U lib/Target/ARM/ARM.td
U lib/CodeGen/PostRASchedulerList.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll
- copied unchanged from r83215, llvm/trunk/test/CodeGen/X86/break-anti-dependencies.ll
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARM.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PostRASchedulerList.cpp Thu Oct 1 17:26:47 2009
@@ -47,11 +47,17 @@
STATISTIC(NumNoops, "Number of noops inserted");
STATISTIC(NumStalls, "Number of pipeline stalls");
+// Post-RA scheduling is enabled with
+// TargetSubtarget.enablePostRAScheduler(). This flag can be used to
+// override the target.
+static cl::opt<bool>
+EnablePostRAScheduler("post-RA-scheduler",
+ cl::desc("Enable scheduling after register allocation"),
+ cl::init(false));
static cl::opt<bool>
EnableAntiDepBreaking("break-anti-dependencies",
cl::desc("Break post-RA scheduling anti-dependencies"),
cl::init(true), cl::Hidden);
-
static cl::opt<bool>
EnablePostRAHazardAvoidance("avoid-hazards",
cl::desc("Enable exact hazard avoidance"),
@@ -210,10 +216,16 @@
}
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
- // Check that post-RA scheduling is enabled for this function
- const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
- if (!ST.enablePostRAScheduler())
- return true;
+ // Check for explicit enable/disable of post-ra scheduling.
+ if (EnablePostRAScheduler.getPosition() > 0) {
+ if (!EnablePostRAScheduler)
+ return true;
+ } else {
+ // Check that post-RA scheduling is enabled for this function
+ const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
+ if (!ST.enablePostRAScheduler())
+ return true;
+ }
DEBUG(errs() << "PostRAScheduler\n");
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARM.td?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARM.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARM.td Thu Oct 1 17:26:47 2009
@@ -43,9 +43,6 @@
def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
"true",
"Use NEON for single-precision FP">;
-def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler",
- "true",
- "Use Post-Register-Allocation Scheduler">;
//===----------------------------------------------------------------------===//
// ARM Processors supported.
@@ -108,8 +105,7 @@
// V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries,
- [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP,
- FeaturePostRASched]>;
+ [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
//===----------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp Thu Oct 1 17:26:47 2009
@@ -93,6 +93,11 @@
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+
+ // Set CPU specific features.
+ if (CPUString == "cortex-a8") {
+ PostRAScheduler = true;
+ }
}
/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll Thu Oct 1 17:26:47 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2,+postrasched -mcpu=cortex-a8
+; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll Thu Oct 1 17:26:47 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll Thu Oct 1 17:26:47 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll Thu Oct 1 17:26:47 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll?rev=83219&r1=83218&r2=83219&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll Thu Oct 1 17:26:47 2009
@@ -1,5 +1,5 @@
; XFAIL: *
-; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched | FileCheck %s
+; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s
; ModuleID = '<stdin>'
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