[llvm-branch-commits] [llvm-branch] r88975 - in /llvm/branches/Apple/Leela: lib/CodeGen/TargetInstrInfoImpl.cpp lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
Evan Cheng
evan.cheng at apple.com
Mon Nov 16 14:00:25 PST 2009
Author: evancheng
Date: Mon Nov 16 16:00:25 2009
New Revision: 88975
URL: http://llvm.org/viewvc/llvm-project?rev=88975&view=rev
Log:
Merge 88974.
Added:
llvm/branches/Apple/Leela/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/X86/X86InstrSSE.td
Modified: llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=88975&r1=88974&r2=88975&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Nov 16 16:00:25 2009
@@ -142,8 +142,10 @@
if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
MO.setReg(DestReg);
MO.setSubReg(SubIdx);
- } else {
+ } else if (SubIdx) {
MO.setReg(TRI->getSubReg(DestReg, SubIdx));
+ } else {
+ MO.setReg(DestReg);
}
MBB.insert(I, MI);
}
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp?rev=88975&r1=88974&r2=88975&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp Mon Nov 16 16:00:25 2009
@@ -794,6 +794,7 @@
case X86::MOVSSrm:
case X86::MOVSDrm:
case X86::MOVAPSrm:
+ case X86::MOVUPSrm:
case X86::MOVAPDrm:
case X86::MOVDQArm:
case X86::MMX_MOVD64rm:
@@ -1892,8 +1893,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (RI.getStackAlignment() >= 16) ||
- RI.needsStackRealignment(MF);
+ bool isAligned = (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
@@ -1986,8 +1986,7 @@
MachineInstr::mmo_iterator MMOBegin,
MachineInstr::mmo_iterator MMOEnd,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- bool isAligned = (RI.getStackAlignment() >= 16) ||
- RI.needsStackRealignment(MF);
+ bool isAligned = (*MMOBegin)->getAlignment() >= 16;
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
@@ -2564,17 +2563,16 @@
MachineFunction &MF = DAG.getMachineFunction();
if (FoldedLoad) {
EVT VT = *RC->vt_begin();
- bool isAligned = (RI.getStackAlignment() >= 16) ||
- RI.needsStackRealignment(MF);
+ std::pair<MachineInstr::mmo_iterator,
+ MachineInstr::mmo_iterator> MMOs =
+ MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
+ cast<MachineSDNode>(N)->memoperands_end());
+ bool isAligned = (*MMOs.first)->getAlignment() >= 16;
Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
// Preserve memory reference information.
- std::pair<MachineInstr::mmo_iterator,
- MachineInstr::mmo_iterator> MMOs =
- MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
- cast<MachineSDNode>(N)->memoperands_end());
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
}
@@ -2602,8 +2600,11 @@
AddrOps.pop_back();
AddrOps.push_back(SDValue(NewNode, 0));
AddrOps.push_back(Chain);
- bool isAligned = (RI.getStackAlignment() >= 16) ||
- RI.needsStackRealignment(MF);
+ std::pair<MachineInstr::mmo_iterator,
+ MachineInstr::mmo_iterator> MMOs =
+ MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
+ cast<MachineSDNode>(N)->memoperands_end());
+ bool isAligned = (*MMOs.first)->getAlignment() >= 16;
SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
isAligned, TM),
dl, MVT::Other,
@@ -2611,10 +2612,6 @@
NewNodes.push_back(Store);
// Preserve memory reference information.
- std::pair<MachineInstr::mmo_iterator,
- MachineInstr::mmo_iterator> MMOs =
- MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
- cast<MachineSDNode>(N)->memoperands_end());
cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
}
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86InstrSSE.td?rev=88975&r1=88974&r2=88975&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86InstrSSE.td Mon Nov 16 16:00:25 2009
@@ -706,7 +706,7 @@
let neverHasSideEffects = 1 in
def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
"movups\t{$src, $dst|$dst, $src}", []>;
-let canFoldAsLoad = 1 in
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
"movups\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (loadv4f32 addr:$src))]>;
Added: llvm/branches/Apple/Leela/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll?rev=88975&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll (added)
+++ llvm/branches/Apple/Leela/test/CodeGen/PowerPC/2009-11-15-ReMatBug.ll Mon Nov 16 16:00:25 2009
@@ -0,0 +1,155 @@
+; RUN: llc < %s -mtriple=powerpc-apple-darwin8
+
+%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+%struct.__gcov_var = type { %struct.FILE*, i32, i32, i32, i32, i32, i32, [1025 x i32] }
+%struct.__sFILEX = type opaque
+%struct.__sbuf = type { i8*, i32 }
+%struct.gcov_ctr_info = type { i32, i64*, void (i64*, i32)* }
+%struct.gcov_ctr_summary = type { i32, i32, i64, i64, i64 }
+%struct.gcov_fn_info = type { i32, i32, [0 x i32] }
+%struct.gcov_info = type { i32, %struct.gcov_info*, i32, i8*, i32, %struct.gcov_fn_info*, i32, [0 x %struct.gcov_ctr_info] }
+%struct.gcov_summary = type { i32, [1 x %struct.gcov_ctr_summary] }
+
+ at __gcov_var = external global %struct.__gcov_var ; <%struct.__gcov_var*> [#uses=1]
+ at __sF = external global [0 x %struct.FILE] ; <[0 x %struct.FILE]*> [#uses=1]
+ at .str = external constant [56 x i8], align 4 ; <[56 x i8]*> [#uses=1]
+ at gcov_list = external global %struct.gcov_info* ; <%struct.gcov_info**> [#uses=1]
+ at .str7 = external constant [35 x i8], align 4 ; <[35 x i8]*> [#uses=1]
+ at .str8 = external constant [9 x i8], align 4 ; <[9 x i8]*> [#uses=1]
+ at .str9 = external constant [10 x i8], align 4 ; <[10 x i8]*> [#uses=1]
+ at .str10 = external constant [36 x i8], align 4 ; <[36 x i8]*> [#uses=1]
+
+declare i32 @"\01_fprintf$LDBL128"(%struct.FILE*, i8*, ...) nounwind
+
+define void @gcov_exit() nounwind {
+entry:
+ %gi_ptr.0357 = load %struct.gcov_info** @gcov_list, align 4 ; <%struct.gcov_info*> [#uses=1]
+ %0 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=3]
+ br i1 undef, label %return, label %bb.nph341
+
+bb.nph341: ; preds = %entry
+ %object27 = bitcast %struct.gcov_summary* undef to i8* ; <i8*> [#uses=1]
+ br label %bb25
+
+bb25: ; preds = %read_fatal, %bb.nph341
+ %gi_ptr.1329 = phi %struct.gcov_info* [ %gi_ptr.0357, %bb.nph341 ], [ undef, %read_fatal ] ; <%struct.gcov_info*> [#uses=1]
+ call void @llvm.memset.i32(i8* %object27, i8 0, i32 36, i32 8)
+ br i1 undef, label %bb49.1, label %bb48
+
+bb48: ; preds = %bb25
+ br label %bb49.1
+
+bb51: ; preds = %bb48.4, %bb49.3
+ switch i32 undef, label %bb58 [
+ i32 0, label %rewrite
+ i32 1734567009, label %bb59
+ ]
+
+bb58: ; preds = %bb51
+ %1 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([35 x i8]* @.str7, i32 0, i32 0), i8* %0) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb59: ; preds = %bb51
+ br i1 undef, label %bb60, label %bb3.i156
+
+bb3.i156: ; preds = %bb59
+ store i8 52, i8* undef, align 1
+ store i8 42, i8* undef, align 1
+ %2 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([56 x i8]* @.str, i32 0, i32 0), i8* %0, i8* undef, i8* undef) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb60: ; preds = %bb59
+ br i1 undef, label %bb78.preheader, label %rewrite
+
+bb78.preheader: ; preds = %bb60
+ br i1 undef, label %bb62, label %bb80
+
+bb62: ; preds = %bb78.preheader
+ br i1 undef, label %bb64, label %read_mismatch
+
+bb64: ; preds = %bb62
+ br i1 undef, label %bb65, label %read_mismatch
+
+bb65: ; preds = %bb64
+ br i1 undef, label %bb75, label %read_mismatch
+
+read_mismatch: ; preds = %bb98, %bb119.preheader, %bb72, %bb71, %bb65, %bb64, %bb62
+ %3 = icmp eq i32 undef, -1 ; <i1> [#uses=1]
+ %iftmp.11.0 = select i1 %3, i8* getelementptr inbounds ([10 x i8]* @.str9, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str8, i32 0, i32 0) ; <i8*> [#uses=1]
+ %4 = call i32 (%struct.FILE*, i8*, ...)* @"\01_fprintf$LDBL128"(%struct.FILE* getelementptr inbounds ([0 x %struct.FILE]* @__sF, i32 0, i32 2), i8* getelementptr inbounds ([36 x i8]* @.str10, i32 0, i32 0), i8* %0, i8* %iftmp.11.0) nounwind ; <i32> [#uses=0]
+ br label %read_fatal
+
+bb71: ; preds = %bb75
+ %5 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %6 = getelementptr inbounds %struct.gcov_info* %gi_ptr.1329, i32 0, i32 7, i32 undef, i32 2 ; <void (i64*, i32)**> [#uses=1]
+ %7 = load void (i64*, i32)** %6, align 4 ; <void (i64*, i32)*> [#uses=1]
+ %8 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1]
+ %9 = call i32 @__gcov_read_unsigned() nounwind ; <i32> [#uses=1]
+ %10 = icmp eq i32 %tmp386, %8 ; <i1> [#uses=1]
+ br i1 %10, label %bb72, label %read_mismatch
+
+bb72: ; preds = %bb71
+ %11 = icmp eq i32 undef, %9 ; <i1> [#uses=1]
+ br i1 %11, label %bb73, label %read_mismatch
+
+bb73: ; preds = %bb72
+ call void %7(i64* null, i32 %5) nounwind
+ unreachable
+
+bb74: ; preds = %bb75
+ %12 = add i32 %13, 1 ; <i32> [#uses=1]
+ br label %bb75
+
+bb75: ; preds = %bb74, %bb65
+ %13 = phi i32 [ %12, %bb74 ], [ 0, %bb65 ] ; <i32> [#uses=2]
+ %tmp386 = add i32 0, 27328512 ; <i32> [#uses=1]
+ %14 = shl i32 1, %13 ; <i32> [#uses=1]
+ %15 = load i32* undef, align 4 ; <i32> [#uses=1]
+ %16 = and i32 %15, %14 ; <i32> [#uses=1]
+ %17 = icmp eq i32 %16, 0 ; <i1> [#uses=1]
+ br i1 %17, label %bb74, label %bb71
+
+bb80: ; preds = %bb78.preheader
+ unreachable
+
+read_fatal: ; preds = %read_mismatch, %bb3.i156, %bb58
+ br i1 undef, label %return, label %bb25
+
+rewrite: ; preds = %bb60, %bb51
+ store i32 -1, i32* getelementptr inbounds (%struct.__gcov_var* @__gcov_var, i32 0, i32 6), align 4
+ br i1 undef, label %bb94, label %bb119.preheader
+
+bb94: ; preds = %rewrite
+ unreachable
+
+bb119.preheader: ; preds = %rewrite
+ br i1 undef, label %read_mismatch, label %bb98
+
+bb98: ; preds = %bb119.preheader
+ br label %read_mismatch
+
+return: ; preds = %read_fatal, %entry
+ ret void
+
+bb49.1: ; preds = %bb48, %bb25
+ br i1 undef, label %bb49.2, label %bb48.2
+
+bb49.2: ; preds = %bb48.2, %bb49.1
+ br i1 undef, label %bb49.3, label %bb48.3
+
+bb48.2: ; preds = %bb49.1
+ br label %bb49.2
+
+bb49.3: ; preds = %bb48.3, %bb49.2
+ br i1 undef, label %bb51, label %bb48.4
+
+bb48.3: ; preds = %bb49.2
+ br label %bb49.3
+
+bb48.4: ; preds = %bb49.3
+ br label %bb51
+}
+
+declare i32 @__gcov_read_unsigned() nounwind
+
+declare void @llvm.memset.i32(i8* nocapture, i8, i32, i32) nounwind
Added: llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll?rev=88975&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll (added)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll Mon Nov 16 16:00:25 2009
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7396984
+
+ at str = private constant [28 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 1
+
+define void @t(i32 %count) ssp nounwind {
+entry:
+; CHECK: t:
+; CHECK: movq ___stack_chk_guard at GOTPCREL(%rip)
+; CHECK: movups L_str(%rip), %xmm0
+ %tmp0 = alloca [60 x i8], align 1
+ %tmp1 = getelementptr inbounds [60 x i8]* %tmp0, i64 0, i64 0
+ br label %bb1
+
+bb1:
+; CHECK: LBB1_1:
+; CHECK: movaps %xmm0, (%rsp)
+ %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ]
+ call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1)
+ %tmp3 = add i32 %tmp2, 1
+ %tmp4 = icmp eq i32 %tmp3, %count
+ br i1 %tmp4, label %bb2, label %bb1
+
+bb2:
+ ret void
+}
+
+declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
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