[llvm-branch-commits] [llvm-branch] r79761 - in /llvm/branches/release_26/lib/Target/SystemZ: SystemZInstrFormats.td SystemZInstrInfo.td

[Tanya Lattner]

Author: tbrethou
Date: Sat Aug 22 15:41:28 2009
New Revision: 79761

URL: http://llvm.org/viewvc/llvm-project?rev=79761&view=rev
Log:
Merge 79741 from mainline.
Some dummy cost model for s390x:
 - Prefer short-imm instructions over ext-imm, when possible
 - Prefer Z10 instructions over Z9, when possible

This hopefully should fix some dejagnu test fails on solaris

Modified:
    llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrFormats.td
    llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrInfo.td

Modified: llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrFormats.td?rev=79761&r1=79760&r2=79761&view=diff

==============================================================================
--- llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrFormats.td Sat Aug 22 15:41:28 2009
@@ -94,19 +94,25 @@
   : I16<op, RREForm, outs, ins, asmstr, pattern>;
 
 class RXI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, RXForm, outs, ins, asmstr, pattern>;
+  : I8<op, RXForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class RXYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, RXYForm, outs, ins, asmstr, pattern>;
 
 class RSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, RSForm, outs, ins, asmstr, pattern>;
+  : I8<op, RSForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class RSYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, RSYForm, outs, ins, asmstr, pattern>;
 
 class SII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, SIForm, outs, ins, asmstr, pattern>;
+  : I8<op, SIForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class SIYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, SIYForm, outs, ins, asmstr, pattern>;

Modified: llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrInfo.td?rev=79761&r1=79760&r2=79761&view=diff

==============================================================================
--- llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/branches/release_26/lib/Target/SystemZ/SystemZInstrInfo.td Sat Aug 22 15:41:28 2009
@@ -324,6 +324,7 @@
                      "mviy\t{$dst, $src}",
                      [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 
+let AddedComplexity = 2 in {
 def MOV16mi   : SILI<0xE544,
                      (outs), (ins riaddr12:$dst, s16imm:$src),
                      "mvhhi\t{$dst, $src}",
@@ -339,6 +340,7 @@
                      "mvghi\t{$dst, $src}",
                      [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
                      Requires<[IsZ10]>;
+}
 
 // sexts
 def MOVSX32rr8  : RREI<0xB926,
@@ -856,6 +858,7 @@
                       "mghi\t{$dst, $src2}",
                       [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 
+let AddedComplexity = 2 in {
 def MUL32ri     : RILI<0xC21,
                        (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
                        "msfi\t{$dst, $src2}",
@@ -866,6 +869,7 @@
                        "msgfi\t{$dst, $src2}",
                        [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
                        Requires<[IsZ10]>;
+}
 
 def MUL32rm : RXI<0x71,
                   (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),