[llvm-branch-commits] [llvm-branch] r78903 - in /llvm/branches/Apple/Leela: include/llvm/Target/TargetSelectionDAG.td lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/NEONPreAllocPass.cpp test/CodeGen/ARM/vtbl.ll utils/TableGen/CodeGenDAGPatterns.cpp utils/TableGen/CodeGenDAGPatterns.h
Bill Wendling
isanbard at gmail.com
Thu Aug 13 01:24:33 PDT 2009
Author: void
Date: Thu Aug 13 03:24:33 2009
New Revision: 78903
URL: http://llvm.org/viewvc/llvm-project?rev=78903&view=rev
Log:
--- Merging r78835 into '.':
A test/CodeGen/ARM/vtbl.ll
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/NEONPreAllocPass.cpp
--- Merging r78849 into '.':
U include/llvm/Target/TargetSelectionDAG.td
U utils/TableGen/CodeGenDAGPatterns.h
U utils/TableGen/CodeGenDAGPatterns.cpp
--- Merging r78850 into '.':
G lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMISelLowering.cpp
--- Merging r78852 into '.':
G lib/Target/ARM/ARMInstrNEON.td
G lib/Target/ARM/ARMISelLowering.h
G lib/Target/ARM/ARMISelLowering.cpp
--- Merging r78881 into '.':
G lib/Target/ARM/ARMISelLowering.cpp
--- Merging r78884 into '.':
G lib/Target/ARM/ARMISelLowering.cpp
--- Merging r78896 into '.':
G lib/Target/ARM/ARMInstrNEON.td
G lib/Target/ARM/ARMISelLowering.h
G lib/Target/ARM/ARMISelLowering.cpp
--- Merging r78897 into '.':
G lib/Target/ARM/ARMISelLowering.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/vtbl.ll
- copied unchanged from r78835, llvm/trunk/test/CodeGen/ARM/vtbl.ll
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetSelectionDAG.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/Apple/Leela/lib/Target/ARM/NEONPreAllocPass.cpp
llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.h
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetSelectionDAG.td?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetSelectionDAG.td Thu Aug 13 03:24:33 2009
@@ -30,12 +30,15 @@
class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
-// SDTCisInt - The specified operand is has integer type.
+// SDTCisInt - The specified operand has integer type.
class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
-// SDTCisFP - The specified operand is has floating point type.
+// SDTCisFP - The specified operand has floating-point type.
class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
+// SDTCisVec - The specified operand has a vector type.
+class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
+
// SDTCisSameAs - The two specified operands have identical types.
class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
int OtherOperandNum = OtherOp;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 13 03:24:33 2009
@@ -484,6 +484,9 @@
case ARMISD::VST2D: return "ARMISD::VST2D";
case ARMISD::VST3D: return "ARMISD::VST3D";
case ARMISD::VST4D: return "ARMISD::VST4D";
+ case ARMISD::VREV64: return "ARMISD::VREV64";
+ case ARMISD::VREV32: return "ARMISD::VREV32";
+ case ARMISD::VREV16: return "ARMISD::VREV16";
}
}
@@ -2336,7 +2339,7 @@
/// isVREVMask - Check if a vector shuffle corresponds to a VREV
/// instruction with the specified blocksize. (The order of the elements
/// within each block of the vector is reversed.)
-bool ARM::isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
+static bool isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
"Only possible block sizes for VREV are: 16, 32, 64");
@@ -2359,7 +2362,7 @@
static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
// Canonicalize all-zeros and all-ones vectors.
- ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
+ ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
if (ConstVal->isNullValue())
return getZeroVector(VT, DAG, dl);
if (ConstVal->isAllOnesValue())
@@ -2396,8 +2399,7 @@
// If this is a case we can't handle, return null and let the default
// expansion code take care of it.
static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
- BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
- assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
+ BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
@@ -2432,6 +2434,23 @@
}
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
+ ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
+ DebugLoc dl = Op.getDebugLoc();
+ EVT VT = Op.getValueType();
+
+ // Convert shuffles that are directly supported on NEON to target-specific
+ // DAG nodes, instead of keeping them as shuffles and matching them again
+ // during code selection. This is more efficient and avoids the possibility
+ // of inconsistencies between legalization and selection.
+ // FIXME: floating-point vectors should be canonicalized to integer vectors
+ // of the same time so that they get CSEd properly.
+ if (isVREVMask(SVN, 64))
+ return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
+ if (isVREVMask(SVN, 32))
+ return DAG.getNode(ARMISD::VREV32, dl, VT, SVN->getOperand(0));
+ if (isVREVMask(SVN, 16))
+ return DAG.getNode(ARMISD::VREV16, dl, VT, SVN->getOperand(0));
+
return Op;
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h Thu Aug 13 03:24:33 2009
@@ -124,7 +124,12 @@
VLD4D,
VST2D,
VST3D,
- VST4D
+ VST4D,
+
+ // Vector shuffles:
+ VREV64, // reverse elements within 64-bit doublewords
+ VREV32, // reverse elements within 32-bit words
+ VREV16 // reverse elements within 16-bit halfwords
};
}
@@ -135,11 +140,6 @@
/// return the constant being splatted. The ByteSize field indicates the
/// number of bytes of each element [1248].
SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
-
- /// isVREVMask - Check if a vector shuffle corresponds to a VREV
- /// instruction with the specified blocksize. (The order of the elements
- /// within each block of the vector is reversed.)
- bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize);
}
//===--------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td Thu Aug 13 03:24:33 2009
@@ -95,6 +95,11 @@
def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
[SDNPHasChain, SDNPMayStore]>;
+def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
+def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
+def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
+def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
+
//===----------------------------------------------------------------------===//
// NEON operand definitions
//===----------------------------------------------------------------------===//
@@ -1881,25 +1886,7 @@
def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
-// VREV : Vector Reverse
-
-def vrev64_shuffle : PatFrag<(ops node:$in),
- (vector_shuffle node:$in, undef), [{
- ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return ARM::isVREVMask(SVOp, 64);
-}]>;
-
-def vrev32_shuffle : PatFrag<(ops node:$in),
- (vector_shuffle node:$in, undef), [{
- ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return ARM::isVREVMask(SVOp, 32);
-}]>;
-
-def vrev16_shuffle : PatFrag<(ops node:$in),
- (vector_shuffle node:$in, undef), [{
- ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
- return ARM::isVREVMask(SVOp, 16);
-}]>;
+// Vector Reverse.
// VREV64 : Vector Reverse elements within 64-bit doublewords
@@ -1907,12 +1894,12 @@
: N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
(ins DPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
+ [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
(ins QPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
+ [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
@@ -1930,12 +1917,12 @@
: N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
(ins DPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
+ [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
(ins QPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
+ [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
@@ -1949,12 +1936,12 @@
: N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
(ins DPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
+ [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
: N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
(ins QPR:$src), NoItinerary,
!strconcat(OpcodeStr, "\t$dst, $src"), "",
- [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
+ [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
@@ -1989,6 +1976,59 @@
def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
+// Vector Table Lookup and Table Extension.
+
+// VTBL : Vector Table Lookup
+def VTBL1
+ : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
+ (ins DPR:$tbl1, DPR:$src), NoItinerary,
+ "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
+def VTBL2
+ : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
+ "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
+ DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
+def VTBL3
+ : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
+ "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
+ DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
+def VTBL4
+ : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
+ (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
+ "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
+ DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+
+// VTBX : Vector Table Extension
+def VTBX1
+ : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
+ (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
+ "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
+ DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
+def VTBX2
+ : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
+ (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
+ "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
+ DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
+def VTBX3
+ : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
+ (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
+ "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
+ DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
+def VTBX4
+ : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
+ DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
+ "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
+ [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
+ DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
+
//===----------------------------------------------------------------------===//
// NEON instructions for single-precision FP math
//===----------------------------------------------------------------------===//
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/NEONPreAllocPass.cpp?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/NEONPreAllocPass.cpp Thu Aug 13 03:24:33 2009
@@ -83,6 +83,36 @@
FirstOpnd = 3;
NumRegs = 4;
return true;
+
+ case ARM::VTBL2:
+ FirstOpnd = 1;
+ NumRegs = 2;
+ return true;
+
+ case ARM::VTBL3:
+ FirstOpnd = 1;
+ NumRegs = 3;
+ return true;
+
+ case ARM::VTBL4:
+ FirstOpnd = 1;
+ NumRegs = 4;
+ return true;
+
+ case ARM::VTBX2:
+ FirstOpnd = 2;
+ NumRegs = 2;
+ return true;
+
+ case ARM::VTBX3:
+ FirstOpnd = 2;
+ NumRegs = 3;
+ return true;
+
+ case ARM::VTBX4:
+ FirstOpnd = 2;
+ NumRegs = 4;
+ return true;
}
return false;
Modified: llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.cpp?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.cpp Thu Aug 13 03:24:33 2009
@@ -95,7 +95,7 @@
/// vector contains a vector value type.
bool isExtVectorInVTs(const std::vector<unsigned char> &EVTs) {
assert(!EVTs.empty() && "Cannot check for vector in empty ExtVT list!");
- return !(FilterEVTs(EVTs, isVector).empty());
+ return EVTs[0] == isVec || !(FilterEVTs(EVTs, isVector).empty());
}
} // end namespace EEVT.
} // end namespace llvm.
@@ -190,6 +190,8 @@
ConstraintType = SDTCisInt;
} else if (R->isSubClassOf("SDTCisFP")) {
ConstraintType = SDTCisFP;
+ } else if (R->isSubClassOf("SDTCisVec")) {
+ ConstraintType = SDTCisVec;
} else if (R->isSubClassOf("SDTCisSameAs")) {
ConstraintType = SDTCisSameAs;
x.SDTCisSameAs_Info.OtherOperandNum = R->getValueAsInt("OtherOperandNum");
@@ -283,6 +285,16 @@
return NodeToApply->UpdateNodeType(FPVTs[0], TP);
return NodeToApply->UpdateNodeType(EEVT::isFP, TP);
}
+ case SDTCisVec: {
+ // If there is only one vector type supported, this must be it.
+ std::vector<MVT::SimpleValueType> VecVTs =
+ FilterVTs(CGT.getLegalValueTypes(), isVector);
+
+ // If we found exactly one supported vector type, apply it.
+ if (VecVTs.size() == 1)
+ return NodeToApply->UpdateNodeType(VecVTs[0], TP);
+ return NodeToApply->UpdateNodeType(EEVT::isVec, TP);
+ }
case SDTCisSameAs: {
TreePatternNode *OtherNode =
getOperandNum(x.SDTCisSameAs_Info.OtherOperandNum, N, NumResults);
@@ -502,7 +514,8 @@
setTypes(FVTs);
return true;
}
- if (ExtVTs[0] == MVT::vAny && EEVT::isExtVectorInVTs(getExtTypes())) {
+ if ((ExtVTs[0] == EEVT::isVec || ExtVTs[0] == MVT::vAny) &&
+ EEVT::isExtVectorInVTs(getExtTypes())) {
assert(hasTypeSet() && "should be handled above!");
std::vector<unsigned char> FVTs = FilterEVTs(getExtTypes(), isVector);
if (getExtTypes() == FVTs)
@@ -511,16 +524,16 @@
return true;
}
- // If we know this is an int or fp type, and we are told it is a specific one,
- // take the advice.
+ // If we know this is an int, FP, or vector type, and we are told it is a
+ // specific one, take the advice.
//
// Similarly, we should probably set the type here to the intersection of
- // {isInt|isFP} and ExtVTs
+ // {isInt|isFP|isVec} and ExtVTs
if (((getExtTypeNum(0) == EEVT::isInt || getExtTypeNum(0) == MVT::iAny) &&
EEVT::isExtIntegerInVTs(ExtVTs)) ||
((getExtTypeNum(0) == EEVT::isFP || getExtTypeNum(0) == MVT::fAny) &&
EEVT::isExtFloatingPointInVTs(ExtVTs)) ||
- (getExtTypeNum(0) == MVT::vAny &&
+ ((getExtTypeNum(0) == EEVT::isVec || getExtTypeNum(0) == MVT::vAny) &&
EEVT::isExtVectorInVTs(ExtVTs))) {
setTypes(ExtVTs);
return true;
@@ -556,6 +569,7 @@
case MVT::Other: OS << ":Other"; break;
case EEVT::isInt: OS << ":isInt"; break;
case EEVT::isFP : OS << ":isFP"; break;
+ case EEVT::isVec: OS << ":isVec"; break;
case EEVT::isUnknown: ; /*OS << ":?";*/ break;
case MVT::iPTR: OS << ":iPTR"; break;
case MVT::iPTRAny: OS << ":iPTRAny"; break;
Modified: llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.h?rev=78903&r1=78902&r2=78903&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.h (original)
+++ llvm/branches/Apple/Leela/utils/TableGen/CodeGenDAGPatterns.h Thu Aug 13 03:24:33 2009
@@ -39,16 +39,21 @@
enum DAGISelGenValueType {
isFP = MVT::LAST_VALUETYPE,
isInt,
+ isVec,
isUnknown
};
- /// isExtIntegerVT - Return true if the specified extended value type vector
- /// contains isInt or an integer value type.
+ /// isExtIntegerInVTs - Return true if the specified extended value type
+ /// vector contains isInt or an integer value type.
bool isExtIntegerInVTs(const std::vector<unsigned char> &EVTs);
- /// isExtFloatingPointVT - Return true if the specified extended value type
- /// vector contains isFP or a FP value type.
+ /// isExtFloatingPointInVTs - Return true if the specified extended value
+ /// type vector contains isFP or a FP value type.
bool isExtFloatingPointInVTs(const std::vector<unsigned char> &EVTs);
+
+ /// isExtVectorinVTs - Return true if the specified extended value type
+ /// vector contains isVec or a vector value type.
+ bool isExtVectorInVTs(const std::vector<unsigned char> &EVTs);
}
/// Set type used to track multiply used variables in patterns
@@ -61,7 +66,7 @@
unsigned OperandNo; // The operand # this constraint applies to.
enum {
- SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs,
+ SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisVec, SDTCisSameAs,
SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisEltOfVec
} ConstraintType;
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