[llvm-branch-commits] [llvm-branch] r78174 - /llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Tue Aug 4 23:37:52 PDT 2009
Author: void
Date: Wed Aug 5 01:37:50 2009
New Revision: 78174
URL: http://llvm.org/viewvc/llvm-project?rev=78174&view=rev
Log:
Specify names with proper namespace.
Modified:
llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp?rev=78174&r1=78173&r2=78174&view=diff
==============================================================================
--- llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Bender-SWB/lib/Target/X86/X86ISelLowering.cpp Wed Aug 5 01:37:50 2009
@@ -7707,7 +7707,7 @@
dyn_cast<ConstantSDNode>(In[Idx0/2].getOperand(2));
if (InsertVecIdx &&
InsertVecIdx->getZExtValue() == (unsigned)(Idx0 % 2) &&
- isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
+ X86::isZeroNode(In[Idx1/2].getOperand(Idx1 % 2))) {
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
In[Idx0/2].getOperand(1),
In[Idx1/2].getOperand(Idx1 % 2));
@@ -7756,7 +7756,7 @@
// This must be an insertion into a zero vector.
SDValue HighElt = N->getOperand(1);
- if (!isZeroNode(HighElt))
+ if (!X86::isZeroNode(HighElt))
return SDValue();
// Value must be a load.
@@ -7807,9 +7807,9 @@
SDValue N2 = N->getOperand(2);
SDValue N3 = N->getOperand(3);
- if (!isZeroNode(N2) && N2.getOpcode() != ISD::UNDEF)
+ if (!X86::isZeroNode(N2) && N2.getOpcode() != ISD::UNDEF)
return SDValue();
- if (!isZeroNode(N3) && N3.getOpcode() != ISD::UNDEF)
+ if (!X86::isZeroNode(N3) && N3.getOpcode() != ISD::UNDEF)
return SDValue();
SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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