[Lldb-commits] [lldb] 274d89a - [lldb][RISCV] Update CSRI patch set for 'Xqci' (#229165)
via lldb-commits
lldb-commits at lists.llvm.org
Thu Oct 15 03:00:24 PDT 2026
Author: Ayush Sahay
Date: 2026-10-15T15:30:17+05:30
New Revision: 274d89af93480a42565f74a54498c188cf7a900e
URL: https://github.com/llvm/llvm-project/commit/274d89af93480a42565f74a54498c188cf7a900e
DIFF: https://github.com/llvm/llvm-project/commit/274d89af93480a42565f74a54498c188cf7a900e.diff
LOG: [lldb][RISCV] Update CSRI patch set for 'Xqci' (#229165)
Update the control and status register information patch set for 'Xqci'
to align with 'Xqci v0.13' –
- Add 'mcause'
- Remove 'mscratch0', 'mscratch1', 'mnepc', and 'mncause'
- Correct the identification of 'mclicilvl0[0-9]'
Added:
Modified:
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
lldb/source/Utility/RISCV_DWARF_Registers.h
lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
Removed:
################################################################################
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
index d7c266e064cca6..673e3d42fd491f 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
@@ -151,7 +151,6 @@ void RegisterInfoPOSIXDynamic_riscv32::ConfigureCSRegInfos(
static const llvm::StringMap<llvm::ArrayRef<lldb_private::RegisterInfo>>
g_register_infos_riscv32_csr_patches = {
{"default", llvm::ArrayRef(g_register_infos_riscv32_csr_patch)},
- {"xqci", llvm::ArrayRef(g_register_infos_riscv32_csr_xqci_patch)},
{"xqciint",
llvm::ArrayRef(g_register_infos_riscv32_csr_xqciint_patch)}};
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index 8ceec7fa234dce..d01d55cfa8ee54 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -689,60 +689,22 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_csr_patch[] = {
DEFINE_CSR32_ALT(mconfigptr, csr_0xf15, LLDB_INVALID_REGNUM),
};
-static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqci_patch[] = {
- DEFINE_QC_CSR32_ALT(mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mscratch0, csr_0x7c6, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mscratch1, csr_0x7c7, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl0, csr_0xbc0, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl1, csr_0xbc1, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl2, csr_0xbc2, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl3, csr_0xbc3, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl4, csr_0xbc4, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl5, csr_0xbc5, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl6, csr_0xbc6, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl7, csr_0xbc7, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl8, csr_0xbc8, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl9, csr_0xbc9, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
-};
-
static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqciint_patch[] =
{
- DEFINE_QC_CSR32_ALT(mnepc, csr_0x7c1, LLDB_INVALID_REGNUM),
- DEFINE_QC_CSR32_ALT(mncause, csr_0x7c2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mcause, csr_0x7c9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
DEFINE_QC_CSR32_ALT(mclicip0, csr_0x7f0, LLDB_INVALID_REGNUM),
DEFINE_QC_CSR32_ALT(mclicip1, csr_0x7f1, LLDB_INVALID_REGNUM),
DEFINE_QC_CSR32_ALT(mclicip2, csr_0x7f2, LLDB_INVALID_REGNUM),
@@ -759,6 +721,38 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqciint_patch[] =
DEFINE_QC_CSR32_ALT(mclicie5, csr_0x7fd, LLDB_INVALID_REGNUM),
DEFINE_QC_CSR32_ALT(mclicie6, csr_0x7fe, LLDB_INVALID_REGNUM),
DEFINE_QC_CSR32_ALT(mclicie7, csr_0x7ff, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl00, csr_0xbc0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl01, csr_0xbc1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl02, csr_0xbc2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl03, csr_0xbc3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl04, csr_0xbc4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl05, csr_0xbc5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl06, csr_0xbc6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl07, csr_0xbc7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl08, csr_0xbc8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl09, csr_0xbc9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
};
#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
index 1d3a7189583303..2ac64f118b7fa2 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
+++ b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
@@ -4662,14 +4662,11 @@ enum {
// Custom CSRs specified by 'Xqci' and its sub-extensions.
csr_qc_mmcr_riscv = csr_1984_riscv,
- csr_qc_mnepc_riscv = csr_1985_riscv,
- csr_qc_mncause_riscv = csr_1986_riscv,
csr_qc_mntvec_riscv = csr_1987_riscv,
csr_qc_mstktopaddr_riscv = csr_1988_riscv,
csr_qc_mstkbottomaddr_riscv = csr_1989_riscv,
- csr_qc_mscratch0_riscv = csr_1990_riscv,
- csr_qc_mscratch1_riscv = csr_1991_riscv,
csr_qc_mthreadptr_riscv = csr_1992_riscv,
+ csr_qc_mcause_riscv = csr_1993_riscv,
csr_qc_mwpstartaddr0_riscv = csr_2000_riscv,
csr_qc_mwpstartaddr1_riscv = csr_2001_riscv,
csr_qc_mwpstartaddr2_riscv = csr_2002_riscv,
@@ -4694,16 +4691,16 @@ enum {
csr_qc_mclicie5_riscv = csr_2045_riscv,
csr_qc_mclicie6_riscv = csr_2046_riscv,
csr_qc_mclicie7_riscv = csr_2047_riscv,
- csr_qc_mclicilvl0_riscv = csr_3008_riscv,
- csr_qc_mclicilvl1_riscv = csr_3009_riscv,
- csr_qc_mclicilvl2_riscv = csr_3010_riscv,
- csr_qc_mclicilvl3_riscv = csr_3011_riscv,
- csr_qc_mclicilvl4_riscv = csr_3012_riscv,
- csr_qc_mclicilvl5_riscv = csr_3013_riscv,
- csr_qc_mclicilvl6_riscv = csr_3014_riscv,
- csr_qc_mclicilvl7_riscv = csr_3015_riscv,
- csr_qc_mclicilvl8_riscv = csr_3016_riscv,
- csr_qc_mclicilvl9_riscv = csr_3017_riscv,
+ csr_qc_mclicilvl00_riscv = csr_3008_riscv,
+ csr_qc_mclicilvl01_riscv = csr_3009_riscv,
+ csr_qc_mclicilvl02_riscv = csr_3010_riscv,
+ csr_qc_mclicilvl03_riscv = csr_3011_riscv,
+ csr_qc_mclicilvl04_riscv = csr_3012_riscv,
+ csr_qc_mclicilvl05_riscv = csr_3013_riscv,
+ csr_qc_mclicilvl06_riscv = csr_3014_riscv,
+ csr_qc_mclicilvl07_riscv = csr_3015_riscv,
+ csr_qc_mclicilvl08_riscv = csr_3016_riscv,
+ csr_qc_mclicilvl09_riscv = csr_3017_riscv,
csr_qc_mclicilvl10_riscv = csr_3018_riscv,
csr_qc_mclicilvl11_riscv = csr_3019_riscv,
csr_qc_mclicilvl12_riscv = csr_3020_riscv,
diff --git a/lldb/source/Utility/RISCV_DWARF_Registers.h b/lldb/source/Utility/RISCV_DWARF_Registers.h
index e3ec252d1bf604..f941913e24da1a 100644
--- a/lldb/source/Utility/RISCV_DWARF_Registers.h
+++ b/lldb/source/Utility/RISCV_DWARF_Registers.h
@@ -4674,14 +4674,11 @@ enum {
// Custom CSRs specified by 'Xqci' and its sub-extensions.
dwarf_csr_qc_mmcr = dwarf_csr_1984,
- dwarf_csr_qc_mnepc = dwarf_csr_1985,
- dwarf_csr_qc_mncause = dwarf_csr_1986,
dwarf_csr_qc_mntvec = dwarf_csr_1987,
dwarf_csr_qc_mstktopaddr = dwarf_csr_1988,
dwarf_csr_qc_mstkbottomaddr = dwarf_csr_1989,
- dwarf_csr_qc_mscratch0 = dwarf_csr_1990,
- dwarf_csr_qc_mscratch1 = dwarf_csr_1991,
dwarf_csr_qc_mthreadptr = dwarf_csr_1992,
+ dwarf_csr_qc_mcause = dwarf_csr_1993,
dwarf_csr_qc_mwpstartaddr0 = dwarf_csr_2000,
dwarf_csr_qc_mwpstartaddr1 = dwarf_csr_2001,
dwarf_csr_qc_mwpstartaddr2 = dwarf_csr_2002,
@@ -4706,16 +4703,16 @@ enum {
dwarf_csr_qc_mclicie5 = dwarf_csr_2045,
dwarf_csr_qc_mclicie6 = dwarf_csr_2046,
dwarf_csr_qc_mclicie7 = dwarf_csr_2047,
- dwarf_csr_qc_mclicilvl0 = dwarf_csr_3008,
- dwarf_csr_qc_mclicilvl1 = dwarf_csr_3009,
- dwarf_csr_qc_mclicilvl2 = dwarf_csr_3010,
- dwarf_csr_qc_mclicilvl3 = dwarf_csr_3011,
- dwarf_csr_qc_mclicilvl4 = dwarf_csr_3012,
- dwarf_csr_qc_mclicilvl5 = dwarf_csr_3013,
- dwarf_csr_qc_mclicilvl6 = dwarf_csr_3014,
- dwarf_csr_qc_mclicilvl7 = dwarf_csr_3015,
- dwarf_csr_qc_mclicilvl8 = dwarf_csr_3016,
- dwarf_csr_qc_mclicilvl9 = dwarf_csr_3017,
+ dwarf_csr_qc_mclicilvl00 = dwarf_csr_3008,
+ dwarf_csr_qc_mclicilvl01 = dwarf_csr_3009,
+ dwarf_csr_qc_mclicilvl02 = dwarf_csr_3010,
+ dwarf_csr_qc_mclicilvl03 = dwarf_csr_3011,
+ dwarf_csr_qc_mclicilvl04 = dwarf_csr_3012,
+ dwarf_csr_qc_mclicilvl05 = dwarf_csr_3013,
+ dwarf_csr_qc_mclicilvl06 = dwarf_csr_3014,
+ dwarf_csr_qc_mclicilvl07 = dwarf_csr_3015,
+ dwarf_csr_qc_mclicilvl08 = dwarf_csr_3016,
+ dwarf_csr_qc_mclicilvl09 = dwarf_csr_3017,
dwarf_csr_qc_mclicilvl10 = dwarf_csr_3018,
dwarf_csr_qc_mclicilvl11 = dwarf_csr_3019,
dwarf_csr_qc_mclicilvl12 = dwarf_csr_3020,
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 76d5115d60a72a..0a1c5e2f8c3a4e 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -1044,16 +1044,16 @@ def test_riscv32_regs_gpr_csr(self):
"qc.mclicie5": ("0x00000000", "csr_0x7fd"),
"qc.mclicie6": ("0x00000000", "csr_0x7fe"),
"qc.mclicie7": ("0x00000000", "csr_0x7ff"),
- "qc.mclicilvl0": ("0x00000000", "csr_0xbc0"),
- "qc.mclicilvl1": ("0x00000000", "csr_0xbc1"),
- "qc.mclicilvl2": ("0x00000000", "csr_0xbc2"),
- "qc.mclicilvl3": ("0x00000000", "csr_0xbc3"),
- "qc.mclicilvl4": ("0x00000000", "csr_0xbc4"),
- "qc.mclicilvl5": ("0x00000000", "csr_0xbc5"),
- "qc.mclicilvl6": ("0x00000000", "csr_0xbc6"),
- "qc.mclicilvl7": ("0x00000000", "csr_0xbc7"),
- "qc.mclicilvl8": ("0x00000000", "csr_0xbc8"),
- "qc.mclicilvl9": ("0x00000000", "csr_0xbc9"),
+ "qc.mclicilvl00": ("0x00000000", "csr_0xbc0"),
+ "qc.mclicilvl01": ("0x00000000", "csr_0xbc1"),
+ "qc.mclicilvl02": ("0x00000000", "csr_0xbc2"),
+ "qc.mclicilvl03": ("0x00000000", "csr_0xbc3"),
+ "qc.mclicilvl04": ("0x00000000", "csr_0xbc4"),
+ "qc.mclicilvl05": ("0x00000000", "csr_0xbc5"),
+ "qc.mclicilvl06": ("0x00000000", "csr_0xbc6"),
+ "qc.mclicilvl07": ("0x00000000", "csr_0xbc7"),
+ "qc.mclicilvl08": ("0x00000000", "csr_0xbc8"),
+ "qc.mclicilvl09": ("0x00000000", "csr_0xbc9"),
"qc.mclicilvl10": ("0x00000000", "csr_0xbca"),
"qc.mclicilvl11": ("0x00000000", "csr_0xbcb"),
"qc.mclicilvl12": ("0x00000000", "csr_0xbcc"),
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