[Lldb-commits] [lldb] [lldb][RISCV] fix LR/SC atomic sequence handling in lldb-server (PR #127505)

[via lldb-commits]

dlav-sc wrote:

> It matches only one of many possible lr.[wd]/sc.[wd] sequences.

I was confused too when I saw this for the first time. I expected to see a processing a sequence of integer instructions between lr and sc. This patch was enough to fix my issue, so I decided to bring it here as is. However, I'm now thinking I could try to do something more comprehensive and support any possible sequence of instructions.

> Why isn't there a a call to m_emu.WriteMem in the implementation?

>From what I understand, it's not a real simulator. This is used in lldb for software stepping to determine where to set a breakpoint. lldb needs to emulate the instruction to obtain next PC.

https://github.com/llvm/llvm-project/pull/127505