[Lldb-commits] [lldb] [llvm] [lldb][LoongArch] Complete register alias name in `AugmentRegisterInfo` (PR #124059)
via lldb-commits
lldb-commits at lists.llvm.org
Thu Feb 20 17:11:04 PST 2025
https://github.com/wangleiat updated https://github.com/llvm/llvm-project/pull/124059
>From f4777704df6b2ac7b7ab33e3baadd3830154904a Mon Sep 17 00:00:00 2001
From: Ray Wang <wangray1021 at gmail.com>
Date: Thu, 23 Jan 2025 12:13:32 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.5-bogner
---
.../ABI/LoongArch/ABISysV_loongarch.cpp | 38 +++++++------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
index dc7e9bba00067..272c6a6be529f 100644
--- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
+++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
@@ -644,32 +644,22 @@ void ABISysV_loongarch::AugmentRegisterInfo(
std::vector<lldb_private::DynamicRegisterInfo::Register> ®s) {
lldb_private::RegInfoBasedABI::AugmentRegisterInfo(regs);
+ static const std::unordered_map<std::string, std::string> reg_aliases = {
+ {"r0", "zero"}, {"r1", "ra"}, {"r2", "tp"}, {"r3", "sp"},
+ {"r4", "a0"}, {"r5", "a1"}, {"r6", "a2"}, {"r7", "a3"},
+ {"r8", "a4"}, {"r9", "a5"}, {"r10", "a6"}, {"r11", "a7"},
+ {"r12", "t0"}, {"r13", "t1"}, {"r14", "t2"}, {"r15", "t3"},
+ {"r16", "t4"}, {"r17", "t5"}, {"r18", "t6"}, {"r19", "t7"},
+ {"r20", "t8"}, {"r22", "fp"}, {"r23", "s0"}, {"r24", "s1"},
+ {"r25", "s2"}, {"r26", "s3"}, {"r27", "s4"}, {"r28", "s5"},
+ {"r29", "s6"}, {"r30", "s7"}, {"r31", "s8"}};
+
for (auto it : llvm::enumerate(regs)) {
// Set alt name for certain registers for convenience
- if (it.value().name == "r0")
- it.value().alt_name.SetCString("zero");
- else if (it.value().name == "r1")
- it.value().alt_name.SetCString("ra");
- else if (it.value().name == "r3")
- it.value().alt_name.SetCString("sp");
- else if (it.value().name == "r22")
- it.value().alt_name.SetCString("fp");
- else if (it.value().name == "r4")
- it.value().alt_name.SetCString("a0");
- else if (it.value().name == "r5")
- it.value().alt_name.SetCString("a1");
- else if (it.value().name == "r6")
- it.value().alt_name.SetCString("a2");
- else if (it.value().name == "r7")
- it.value().alt_name.SetCString("a3");
- else if (it.value().name == "r8")
- it.value().alt_name.SetCString("a4");
- else if (it.value().name == "r9")
- it.value().alt_name.SetCString("a5");
- else if (it.value().name == "r10")
- it.value().alt_name.SetCString("a6");
- else if (it.value().name == "r11")
- it.value().alt_name.SetCString("a7");
+ std::string reg_name = it.value().name.GetStringRef().str();
+ if (auto alias = reg_aliases.find(reg_name); alias != reg_aliases.end()) {
+ it.value().alt_name.SetCString(alias->second.c_str());
+ }
// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
>From d03f4f2b191c09d6492249aa5e0d50fc62a5a434 Mon Sep 17 00:00:00 2001
From: Ray Wang <wangray1021 at gmail.com>
Date: Wed, 5 Feb 2025 17:58:09 +0800
Subject: [PATCH 2/3] add test
Created using spr 1.3.5-bogner
---
.../postmortem/elf-core/TestLinuxCore.py | 82 ++++++++++---------
1 file changed, 44 insertions(+), 38 deletions(-)
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 376d6492d83b6..adabac106f3e3 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -642,8 +642,7 @@ def test_aarch64_sve_regs_full(self):
)
# RMode should have enumerator descriptions.
self.expect(
- "register info fpcr",
- substrs=["RMode: 0 = RN, 1 = RP, 2 = RM, 3 = RZ"],
+ "register info fpcr", substrs=["RMode: 0 = RN, 1 = RP, 2 = RM, 3 = RZ"]
)
@skipIfLLVMTargetMissing("AArch64")
@@ -852,41 +851,42 @@ def test_loongarch64_regs(self):
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("linux-loongarch64.core")
- values = {}
- values["r0"] = "0x0000000000000000"
- values["r1"] = "0x000000012000016c"
- values["r2"] = "0x0000000000000000"
- values["r3"] = "0x00007ffffb8249e0"
- values["r4"] = "0x0000000000000000"
- values["r5"] = "0x000000012000010c"
- values["r6"] = "0x0000000000000000"
- values["r7"] = "0x0000000000000000"
- values["r8"] = "0x0000000000000000"
- values["r9"] = "0x0000000000000000"
- values["r10"] = "0x0000000000000000"
- values["r11"] = "0x00000000000000dd"
- values["r12"] = "0x0000000000000000"
- values["r13"] = "0x000000000000002f"
- values["r14"] = "0x0000000000000000"
- values["r15"] = "0x0000000000000000"
- values["r16"] = "0x0000000000000000"
- values["r17"] = "0x0000000000000000"
- values["r18"] = "0x0000000000000000"
- values["r19"] = "0x0000000000000000"
- values["r20"] = "0x0000000000000000"
- values["r21"] = "0x0000000000000000"
- values["r22"] = "0x00007ffffb824a10"
- values["r23"] = "0x0000000000000000"
- values["r24"] = "0x0000000000000000"
- values["r25"] = "0x0000000000000000"
- values["r26"] = "0x0000000000000000"
- values["r27"] = "0x0000000000000000"
- values["r28"] = "0x0000000000000000"
- values["r29"] = "0x0000000000000000"
- values["r30"] = "0x0000000000000000"
- values["r31"] = "0x0000000000000000"
- values["orig_a0"] = "0x0000555556b62d50"
- values["pc"] = "0x000000012000012c"
+ values = {
+ "r0": ("0x0000000000000000", "zero"),
+ "r1": ("0x000000012000016c", "ra"),
+ "r2": ("0x0000000000000000", "tp"),
+ "r3": ("0x00007ffffb8249e0", "sp"),
+ "r4": ("0x0000000000000000", "a0"),
+ "r5": ("0x000000012000010c", "a1"),
+ "r6": ("0x0000000000000000", "a2"),
+ "r7": ("0x0000000000000000", "a3"),
+ "r8": ("0x0000000000000000", "a4"),
+ "r9": ("0x0000000000000000", "a5"),
+ "r10": ("0x0000000000000000", "a6"),
+ "r11": ("0x00000000000000dd", "a7"),
+ "r12": ("0x0000000000000000", "t0"),
+ "r13": ("0x000000000000002f", "t1"),
+ "r14": ("0x0000000000000000", "t2"),
+ "r15": ("0x0000000000000000", "t3"),
+ "r16": ("0x0000000000000000", "t4"),
+ "r17": ("0x0000000000000000", "t5"),
+ "r18": ("0x0000000000000000", "t6"),
+ "r19": ("0x0000000000000000", "t7"),
+ "r20": ("0x0000000000000000", "t8"),
+ "r21": ("0x0000000000000000", None),
+ "r22": ("0x00007ffffb824a10", "fp"),
+ "r23": ("0x0000000000000000", "s0"),
+ "r24": ("0x0000000000000000", "s1"),
+ "r25": ("0x0000000000000000", "s2"),
+ "r26": ("0x0000000000000000", "s3"),
+ "r27": ("0x0000000000000000", "s4"),
+ "r28": ("0x0000000000000000", "s5"),
+ "r29": ("0x0000000000000000", "s6"),
+ "r30": ("0x0000000000000000", "s7"),
+ "r31": ("0x0000000000000000", "s8"),
+ "orig_a0": ("0x0000555556b62d50", None),
+ "pc": ("0x000000012000012c", None),
+ }
fpr_values = {}
fpr_values["f0"] = "0x00000000ffffff05"
@@ -931,11 +931,17 @@ def test_loongarch64_regs(self):
fpr_values["fcc7"] = "0x01"
fpr_values["fcsr"] = "0x00000000"
- for regname, value in values.items():
+ for regname in values:
+ value, alias = values[regname]
self.expect(
"register read {}".format(regname),
substrs=["{} = {}".format(regname, value)],
)
+ if alias:
+ self.expect(
+ "register read {}".format(alias),
+ substrs=["{} = {}".format(regname, value)],
+ )
for regname, value in fpr_values.items():
self.expect(
>From b77caf23b9cd46f2f69a49a83c130cc3fb65d736 Mon Sep 17 00:00:00 2001
From: wanglei <wanglei at loongson.cn>
Date: Thu, 20 Feb 2025 20:52:30 +0800
Subject: [PATCH 3/3] add test
Created using spr 1.3.5-bogner
---
.../Register/Inputs/loongarch64-gp-read.cpp | 35 +++++++++++++++++
.../Shell/Register/loongarch64-gp-read.test | 39 +++++++++++++++++++
llvm/utils/lit/lit/llvm/config.py | 2 +
3 files changed, 76 insertions(+)
create mode 100644 lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp
create mode 100644 lldb/test/Shell/Register/loongarch64-gp-read.test
diff --git a/lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp b/lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp
new file mode 100644
index 0000000000000..e229d2001d942
--- /dev/null
+++ b/lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp
@@ -0,0 +1,35 @@
+int main() {
+ asm volatile("li.w $r1, 1\n\t"
+ "li.w $r2, 2\n\t"
+ "li.w $r3, 3\n\t"
+ "li.w $r4, 4\n\t"
+ "li.w $r5, 5\n\t"
+ "li.w $r6, 6\n\t"
+ "li.w $r7, 7\n\t"
+ "li.w $r8, 8\n\t"
+ "li.w $r9, 9\n\t"
+ "li.w $r10, 10\n\t"
+ "li.w $r11, 11\n\t"
+ "li.w $r12, 12\n\t"
+ "li.w $r13, 13\n\t"
+ "li.w $r14, 14\n\t"
+ "li.w $r15, 15\n\t"
+ "li.w $r16, 16\n\t"
+ "li.w $r17, 17\n\t"
+ "li.w $r18, 18\n\t"
+ "li.w $r19, 19\n\t"
+ "li.w $r20, 20\n\t"
+ "li.w $r21, 21\n\t"
+ "li.w $r22, 22\n\t"
+ "li.w $r23, 23\n\t"
+ "li.w $r24, 24\n\t"
+ "li.w $r25, 25\n\t"
+ "li.w $r26, 26\n\t"
+ "li.w $r27, 27\n\t"
+ "li.w $r28, 28\n\t"
+ "li.w $r29, 29\n\t"
+ "li.w $r30, 30\n\t"
+ "li.w $r31, 31\n\t"
+ "break 5\n\t");
+ return 0;
+}
diff --git a/lldb/test/Shell/Register/loongarch64-gp-read.test b/lldb/test/Shell/Register/loongarch64-gp-read.test
new file mode 100644
index 0000000000000..ba10589076775
--- /dev/null
+++ b/lldb/test/Shell/Register/loongarch64-gp-read.test
@@ -0,0 +1,39 @@
+# REQUIRES: native && target-loongarch64
+# RUN: %clangxx_host %p/Inputs/loongarch64-gp-read.cpp -o %t
+# RUN: %lldb -b -s %s %t | FileCheck %s
+process launch
+
+## read alias name
+register read zero ra tp sp a0 a1 a2 a3 a4 a5 a6 a7 t0 t1 t2 t3 t4 t5 t6 t7 t8 r21 fp s0 s1 s2 s3 s4 s5 s6 s7 s8
+# CHECK-DAG: r0 = 0x0000000000000000
+# CHECK-DAG: r1 = 0x0000000000000001
+# CHECK-DAG: r2 = 0x0000000000000002
+# CHECK-DAG: r3 = 0x0000000000000003
+# CHECK-DAG: r4 = 0x0000000000000004
+# CHECK-DAG: r5 = 0x0000000000000005
+# CHECK-DAG: r6 = 0x0000000000000006
+# CHECK-DAG: r7 = 0x0000000000000007
+# CHECK-DAG: r8 = 0x0000000000000008
+# CHECK-DAG: r9 = 0x0000000000000009
+# CHECK-DAG: r10 = 0x000000000000000a
+# CHECK-DAG: r11 = 0x000000000000000b
+# CHECK-DAG: r12 = 0x000000000000000c
+# CHECK-DAG: r13 = 0x000000000000000d
+# CHECK-DAG: r14 = 0x000000000000000e
+# CHECK-DAG: r15 = 0x000000000000000f
+# CHECK-DAG: r16 = 0x0000000000000010
+# CHECK-DAG: r17 = 0x0000000000000011
+# CHECK-DAG: r18 = 0x0000000000000012
+# CHECK-DAG: r19 = 0x0000000000000013
+# CHECK-DAG: r20 = 0x0000000000000014
+# CHECK-DAG: r21 = 0x0000000000000015
+# CHECK-DAG: r22 = 0x0000000000000016
+# CHECK-DAG: r23 = 0x0000000000000017
+# CHECK-DAG: r24 = 0x0000000000000018
+# CHECK-DAG: r25 = 0x0000000000000019
+# CHECK-DAG: r26 = 0x000000000000001a
+# CHECK-DAG: r27 = 0x000000000000001b
+# CHECK-DAG: r28 = 0x000000000000001c
+# CHECK-DAG: r29 = 0x000000000000001d
+# CHECK-DAG: r30 = 0x000000000000001e
+# CHECK-DAG: r31 = 0x000000000000001f
diff --git a/llvm/utils/lit/lit/llvm/config.py b/llvm/utils/lit/lit/llvm/config.py
index 5f762ec7f3514..d44fb02f3acd8 100644
--- a/llvm/utils/lit/lit/llvm/config.py
+++ b/llvm/utils/lit/lit/llvm/config.py
@@ -169,6 +169,8 @@ def __init__(self, lit_config, config):
features.add("target-aarch64")
elif re.match(r"^arm.*", target_triple):
features.add("target-arm")
+ elif re.match(r"^loongarch64.*", target_triple):
+ features.add("target-loongarch64")
if re.match(r'^ppc64le.*-linux', target_triple):
features.add('target=powerpc64le-linux')
More information about the lldb-commits
mailing list