[Lldb-commits] [lldb] [lldb] Support overriding the disassembly CPU & features (PR #115382)

[David Spickett via lldb-commits]

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@@ -157,6 +157,12 @@ let Definition = "target" in {
     DefaultEnumValue<"eX86DisFlavorDefault">,
     EnumValues<"OptionEnumValues(g_x86_dis_flavor_value_types)">,
     Desc<"The default disassembly flavor to use for x86 or x86-64 targets.">;
+  def DisassemblyCPU: Property<"disassembly-cpu", "String">,
+    DefaultStringValue<"">,
+    Desc<"Override the CPU for disassembling. Takes the same values as the -mcpu compiler flag.">;
+  def DisassemblyFeatures: Property<"disassembly-features", "String">,
+    DefaultStringValue<"">,
+    Desc<"Specify additional CPU features for disassembling.">;
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DavidSpickett wrote:

If I were a risc-v clang user I'd probably reference this:
```
$ ./bin/clang -target riscv64-linux-gnu --print-supported-extensions
clang version 20.0.0git (https://github.com/llvm/llvm-project.git 5f342816efe1854333f2be41a03fdd25fa0db433)
Target: riscv64-unknown-linux-gnu
Thread model: posix
InstalledDir: /home/david.spickett/build-llvm-aarch64/bin
Build config: +assertions
All available -march extensions for RISC-V

    Name                 Version   Description
    i                    2.1       'I' (Base Integer Instruction Set)
    e                    2.0       Implements RV{32,64}E (provides 16 rather than 32 GPRs)
```
Assuming I knew to add the `+` on. This works for AArch64 as well.

For AArch64 I know some of the MC names are slightly different (because we made mistakes, e.g. `memtag` and `mte`) so that could be interesting for a user here.

If the CPU option takes `-mcpu` I'd expect this to take `-march` names. I see `+all` though so I assume this actually takes `llvm-mc -mattr=` names.

It would be nice to use the frontend names but doing so is probably more hassle than it's worth given that the users of this setting probably know how to figure it out anyway for the few cases where the name is different.

https://github.com/llvm/llvm-project/pull/115382