[Lldb-commits] [lldb] [lldb] add RISCV target specific info in API tests (PR #99039)

[David Spickett via lldb-commits]

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@@ -34,6 +34,8 @@ def check_first_register_readable(test_case):
         test_case.expect("register read r0", substrs=["r0 = 0x"])
     elif arch in ["powerpc64le"]:
         test_case.expect("register read r0", substrs=["r0 = 0x"])
+    elif arch in ["rv64gc"]:
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DavidSpickett wrote:

To be honest I was asking more for understanding than anything else. Good to know it would be easy to extend.

I would leave this as is on the grounds that you only know for sure that rv64 works here, and anyone working on anything else will have the ability to validate the test themselves. So leave it to future them (maybe future you) to update the name here.

Just update the PR title and commit message to be clear that you're doing this for rv64 only.

https://github.com/llvm/llvm-project/pull/99039