[Lldb-commits] [lldb] [lldb] add RISCV target specific info in API tests (PR #99039)

[via lldb-commits]

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@@ -34,6 +34,8 @@ def check_first_register_readable(test_case):
         test_case.expect("register read r0", substrs=["r0 = 0x"])
     elif arch in ["powerpc64le"]:
         test_case.expect("register read r0", substrs=["r0 = 0x"])
+    elif arch in ["rv64gc"]:
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dlav-sc wrote:

Yes, you are right. `rv64gc` is just my configuration (now `getArchitecture()` returns what I pass to `--arch` option running  `dotest.py`).

Maybe I can make more generic solution by adding a regexp or just simple `if arch.startswith("rv"): arch = "riscv"` in `getArchitecture()`. I think it would be enough for now, because `rv32` and `rv64` have the same register set and as you have noticed `zero = 0x` would be fine for any target, so there is no reasons to distinguish a bitness or configurations.

https://github.com/llvm/llvm-project/pull/99039