[Lldb-commits] [lldb] 0ef58c6 - [LLDB][RISCV] Add RVDC instruction support for EmulateInstructionRISCV

[via lldb-commits]

Author: Emmmer
Date: 2023-01-13T20:52:34+08:00
New Revision: 0ef58c66c6e4652ff3582bf0972673708afb912e

URL: https://github.com/llvm/llvm-project/commit/0ef58c66c6e4652ff3582bf0972673708afb912e
DIFF: https://github.com/llvm/llvm-project/commit/0ef58c66c6e4652ff3582bf0972673708afb912e.diff

LOG: [LLDB][RISCV] Add RVDC instruction support for EmulateInstructionRISCV

RVC is the RISC-V standard compressed instruction-set extension, named "C", which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations, and RVCD is the compressed "D extension".

And "D extension" is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D140961

Added: 
    

Modified: 
    lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
    lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
    lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp

Removed: 
    


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diff  --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 4fe025ad5d1af..06772aaa6e17c 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -541,6 +541,11 @@ static const InstrPattern PATTERNS[] = {
     {"FSW", 0xE003, 0xE000, DecodeC_FSW, RV32},
     {"FLWSP", 0xE003, 0x6002, DecodeC_FLWSP, RV32},
     {"FSWSP", 0xE003, 0xE002, DecodeC_FSWSP, RV32},
+    // RVDC //
+    {"FLDSP", 0xE003, 0x2002, DecodeC_FLDSP, RV32 | RV64},
+    {"FSDSP", 0xE003, 0xA002, DecodeC_FSDSP, RV32 | RV64},
+    {"FLD", 0xE003, 0x2000, DecodeC_FLD, RV32 | RV64},
+    {"FSD", 0xE003, 0xA000, DecodeC_FSD, RV32 | RV64},
 
     // RV32F (Extension for Single-Precision Floating-Point) //
     {"FLW", 0x707F, 0x2007, DecodeIType<FLW>},

diff  --git a/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h b/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
index 1f1d2853ab36d..867f067f24b38 100644
--- a/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
+++ b/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
@@ -327,5 +327,31 @@ RISCVInst DecodeC_FSWSP(uint32_t inst) {
   return FSW{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
 }
 
+RISCVInst DecodeC_FLDSP(uint32_t inst) {
+  auto rd = DecodeCI_RD(inst);
+  uint16_t offset = ((inst << 4) & 0x1c0)   // offset[8:6]
+                    | ((inst >> 7) & 0x20)  // offset[5]
+                    | ((inst >> 2) & 0x18); // offset[4:3]
+  return FLD{rd, Rs{gpr_sp_riscv}, uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FSDSP(uint32_t inst) {
+  uint16_t offset = ((inst >> 1) & 0x1c0)   // offset[8:6]
+                    | ((inst >> 7) & 0x38); // offset[5:3]
+  return FSD{Rs{gpr_sp_riscv}, DecodeCSS_RS2(inst), uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FLD(uint32_t inst) {
+  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
+                    | ((inst >> 7) & 0x38); // imm[5:3]
+  return FLD{DecodeCL_RD(inst), DecodeCL_RS1(inst), uint32_t(offset)};
+}
+
+RISCVInst DecodeC_FSD(uint32_t inst) {
+  uint16_t offset = ((inst << 1) & 0xc0)    // imm[7:6]
+                    | ((inst >> 7) & 0x38); // imm[5:3]
+  return FSD{DecodeCS_RS1(inst), DecodeCS_RS2(inst), uint32_t(offset)};
+}
+
 } // namespace lldb_private
 #endif // LLDB_SOURCE_PLUGINS_INSTRUCTION_RISCV_RISCVCINSTRUCTION_H

diff  --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index 406c0ae8f4b56..90d5a7c4f3b97 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -287,8 +287,10 @@ TEST_F(RISCVEmulatorTester, TestCDecode) {
       {0x0010, RESERVED{0x0010}},
       // ADDI4SPN here, decode as ADDI
       {0x0024, ADDI{Rd{9}, Rs{2}, 8}},
+      {0x2084, FLD{Rd{9}, Rs{9}, 0}},
       {0x4488, LW{Rd{10}, Rs{9}, 8}},
       {0x6488, LD{Rd{10}, Rs{9}, 8}},
+      {0xA084, FSD{Rs{9}, Rs{9}, 0}},
       {0xC488, SW{Rs{9}, Rs{10}, 8}},
       {0xE488, SD{Rs{9}, Rs{10}, 8}},
       {0x1001, NOP{0x1001}},
@@ -315,6 +317,8 @@ TEST_F(RISCVEmulatorTester, TestCDecode) {
       {0x1002, HINT{0x1002}},
       // SLLI64 here, decoded as HINT if not in RV128
       {0x0082, HINT{0x0082}},
+      // FLDSP here, decoded as FLD
+      {0x2082, FLD{Rd{1}, Rs{2}, 0}},
       // LWSP here, decoded as LW
       {0x4082, LW{Rd{1}, Rs{2}, 0}},
       // LDSP here, decoded as LD
@@ -326,6 +330,8 @@ TEST_F(RISCVEmulatorTester, TestCDecode) {
       {0x9002, EBREAK{0x9002}},
       {0x9082, JALR{Rd{1}, Rs{1}, 0}},
       {0x9086, ADD{Rd{1}, Rs{1}, Rs{1}}},
+      // C.FSDSP here, decoded as FSD
+      {0xA006, FSD{Rs{2}, Rs{1}, 0}},
       // C.SWSP here, decoded as SW
       {0xC006, SW{Rs{2}, Rs{1}, 0}},
       // C.SDSP here, decoded as SD
@@ -350,6 +356,11 @@ TEST_F(RISCVEmulatorTester32, TestCDecodeRV32) {
       {0xE006, FSW{Rs{2}, Rs{1}, 0}},
       {0x6000, FLW{Rd{8}, Rs{8}, 0}},
       {0xE000, FSW{Rs{8}, Rs{8}, 0}},
+
+      {0x2084, FLD{Rd{9}, Rs{9}, 0}},
+      {0xA084, FSD{Rs{9}, Rs{9}, 0}},
+      {0x2082, FLD{Rd{1}, Rs{2}, 0}},
+      {0xA006, FSD{Rs{2}, Rs{1}, 0}},
   };
 
   for (auto i : tests) {