[Lldb-commits] [PATCH] D130342: [LLDB][RISCV] Add register stuff and make breakpoint work

[Tiancheng Zhang via Phabricator via lldb-commits]

tzb99 added a comment.

In D130342#3709772 <https://reviews.llvm.org/D130342#3709772>, @Emmmer wrote:

> What is implemented:
>
> - Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
> - Take RISC-V `ebreak` instruction as breakpoint trap code, so our breakpoint works as expected now.
> - Refactor some duplicate code.
>
> Further work:
>
> - RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
> - Add support for RVC extension (the trap code, etc.).

Thank you so much for the contribution! I have few more questions. What is your qemu spec? Is it operated in the user mode or the system mode? In addition, did your cross compilation build using in-tree build or build lldb separately?


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