[Lldb-commits] [PATCH] D130342: [LLDB][RISCV] Add register stuff and make breakpoint work

[Emmmer S via Phabricator via lldb-commits]

Emmmer updated this revision to Diff 451140.
Emmmer retitled this revision from "[LLDB][RISCV] Add Register Info and Context" to "[LLDB][RISCV] Add register stuff and make breakpoint work".
Emmmer edited the summary of this revision.
Emmmer added a subscriber: tzb99.
Emmmer added a comment.

What is implemented:

- Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
- Take RISC-V `ebreak` instruction as breakpoint trap code, so our breakpoint works as expected now.
- Refactor some duplicate code.

Further work:

- RISC-V does not support hardware single stepping yet. A software implementation may come in future PR.
- Add support for RVC extension (the trap code, etc.).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130342/new/

https://reviews.llvm.org/D130342

Files:
  lldb/source/Host/common/HostInfoBase.cpp
  lldb/source/Host/common/NativeProcessProtocol.cpp
  lldb/source/Plugins/Process/Linux/CMakeLists.txt
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
  lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
  lldb/source/Plugins/Process/Utility/CMakeLists.txt
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
  lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
  lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
  lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
  lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
  lldb/source/Target/Platform.cpp

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