[Lldb-commits] [lldb] c604207 - lldb/ObjectFile, Disassembler: read some state from the executable

[Pavel Labath via lldb-commits]

No test case?

On 10/03/2022 22:42, Saleem Abdulrasool via lldb-commits wrote:
> 
> Author: Saleem Abdulrasool
> Date: 2022-03-10T21:42:06Z
> New Revision: c6042076081025bc8060637b05fbeb24dbb82538
> 
> URL: https://github.com/llvm/llvm-project/commit/c6042076081025bc8060637b05fbeb24dbb82538
> DIFF: https://github.com/llvm/llvm-project/commit/c6042076081025bc8060637b05fbeb24dbb82538.diff
> 
> LOG: lldb/ObjectFile,Disassembler: read some state from the executable
> 
> Add support to inspect the ELF headers for RISCV targets to determine if
> RVC or RVE are enabled and the floating point support to enable.  As per
> the RISCV specification, d implies f, q implies d implies f, which gives
> us the cascading effect that is used to enable the features when setting
> up the disassembler.  With this change, it is now possible to attach the
> debugger to a remote process and be able to disassemble the instruction
> stream.
> 
> ~~~
> $ bin/lldb tmp/reduced
> (lldb) target create "reduced"
> Current executable set to '/tmp/reduced' (riscv64).
> (lldb) gdb-remote localhost:1234
> (lldb) Process 5737 stopped
> * thread #1, name = 'reduced', stop reason = signal SIGTRAP
>      frame #0: 0x0000003ff7fe1b20
> ->  0x3ff7fe1b20: mv     a0, sp
>      0x3ff7fe1b22: jal    1936
>      0x3ff7fe1b26: mv     s0, a0
>      0x3ff7fe1b28: auipc  a0, 27
> ~~~
> 
> Added:
>      
> 
> Modified:
>      lldb/include/lldb/Utility/ArchSpec.h
>      lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
>      lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
> 
> Removed:
>      
> 
> 
> ################################################################################
> diff  --git a/lldb/include/lldb/Utility/ArchSpec.h b/lldb/include/lldb/Utility/ArchSpec.h
> index fdfe6aceb033c..f67acedf11c2e 100644
> --- a/lldb/include/lldb/Utility/ArchSpec.h
> +++ b/lldb/include/lldb/Utility/ArchSpec.h
> @@ -92,6 +92,17 @@ class ArchSpec {
>       eARM_abi_hard_float = 0x00000400
>     };
>   
> +  enum RISCVeflags {
> +    eRISCV_rvc              = 0x00000001, /// RVC, +c
> +    eRISCV_float_abi_soft   = 0x00000000, /// soft float
> +    eRISCV_float_abi_single = 0x00000002, /// single precision floating point, +f
> +    eRISCV_float_abi_double = 0x00000004, /// double precision floating point, +d
> +    eRISCV_float_abi_quad   = 0x00000006, /// quad precision floating point, +q
> +    eRISCV_float_abi_mask   = 0x00000006,
> +    eRISCV_rve              = 0x00000008, /// RVE, +e
> +    eRISCV_tso              = 0x00000010, /// RVTSO (total store ordering)
> +  };
> +
>     enum RISCVSubType {
>       eRISCVSubType_unknown,
>       eRISCVSubType_riscv32,
> 
> diff  --git a/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
> index e1ad5ac838c72..ee6ae3ffe3db9 100644
> --- a/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
> +++ b/lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
> @@ -1187,6 +1187,24 @@ DisassemblerLLVMC::DisassemblerLLVMC(const ArchSpec &arch,
>         cpu = "apple-latest";
>     }
>   
> +  if (triple.isRISCV()) {
> +    uint32_t arch_flags = arch.GetFlags();
> +    if (arch_flags & ArchSpec::eRISCV_rvc)
> +      features_str += "+c,";
> +    if (arch_flags & ArchSpec::eRISCV_rve)
> +      features_str += "+e,";
> +    if ((arch_flags & ArchSpec::eRISCV_float_abi_single) ==
> +        ArchSpec::eRISCV_float_abi_single)
> +      features_str += "+f,";
> +    if ((arch_flags & ArchSpec::eRISCV_float_abi_double) ==
> +        ArchSpec::eRISCV_float_abi_double)
> +      features_str += "+f,+d,";
> +    if ((arch_flags & ArchSpec::eRISCV_float_abi_quad) ==
> +        ArchSpec::eRISCV_float_abi_quad)
> +      features_str += "+f,+d,+q,";
> +    // FIXME: how do we detect features such as `+a`, `+m`?
> +  }
> +
>     // We use m_disasm_up.get() to tell whether we are valid or not, so if this
>     // isn't good for some reason, we won't be valid and FindPlugin will fail and
>     // we won't get used.
> 
> diff  --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
> index 77d126684e662..0c79bc57e64a7 100644
> --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
> +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
> @@ -1364,6 +1364,28 @@ size_t ObjectFileELF::GetSectionHeaderInfo(SectionHeaderColl &section_headers,
>         arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
>     }
>   
> +  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
> +      arch_spec.GetMachine() == llvm::Triple::riscv64) {
> +    uint32_t flags = arch_spec.GetFlags();
> +
> +    if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
> +      flags |= ArchSpec::eRISCV_rvc;
> +    if (header.e_flags & llvm::ELF::EF_RISCV_RVE)
> +      flags |= ArchSpec::eRISCV_rve;
> +
> +    if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE) ==
> +        llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
> +      flags |= ArchSpec::eRISCV_float_abi_single;
> +    else if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE) ==
> +             llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
> +      flags |= ArchSpec::eRISCV_float_abi_double;
> +    else if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI_QUAD) ==
> +             llvm::ELF::EF_RISCV_FLOAT_ABI_QUAD)
> +      flags |= ArchSpec::eRISCV_float_abi_quad;
> +
> +    arch_spec.SetFlags(flags);
> +  }
> +
>     // If there are no section headers we are done.
>     if (header.e_shnum == 0)
>       return 0;
> 
> 
>          
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