[Lldb-commits] [lldb] f583029 - [lldb] Correct "else if" to "elif" in TestRegisters

[David Spickett via lldb-commits]

Author: David Spickett
Date: 2021-06-14T09:36:00Z
New Revision: f583029da3d6dbabe82f48b160227eb0120abd33

URL: https://github.com/llvm/llvm-project/commit/f583029da3d6dbabe82f48b160227eb0120abd33
DIFF: https://github.com/llvm/llvm-project/commit/f583029da3d6dbabe82f48b160227eb0120abd33.diff

LOG: [lldb] Correct "else if" to "elif" in TestRegisters

Added: 
    

Modified: 
    lldb/test/API/commands/register/register/register_command/TestRegisters.py

Removed: 
    


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diff  --git a/lldb/test/API/commands/register/register/register_command/TestRegisters.py b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
index 96e6c8065e82..cd0cb6d46fc2 100644
--- a/lldb/test/API/commands/register/register/register_command/TestRegisters.py
+++ b/lldb/test/API/commands/register/register/register_command/TestRegisters.py
@@ -406,7 +406,7 @@ def fp_register_write(self):
                 if 'advanced vector extensions' in set_name:
                     has_avx = True
                 # Darwin reports AVX registers as part of "Floating Point Registers"
-                else if self.platformIsDarwin() and 'floating point registers' in set_name:
+                elif self.platformIsDarwin() and 'floating point registers' in set_name:
                     has_avx = registerSet.GetFirstValueByName('ymm0').IsValid()
 
                 # FreeBSD/NetBSD reports missing register sets 
diff erently