[Lldb-commits] [PATCH] D86292: [LLDB][RISCV] Distinguish between riscv32 and riscv64 based on ELF class

Luís Marques via Phabricator via lldb-commits lldb-commits at lists.llvm.org
Thu Aug 20 07:57:34 PDT 2020


luismarques created this revision.
luismarques added reviewers: asb, lenary, clayborg, jasonmolenda, simoncook.
Herald added subscribers: lldb-commits, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, johnrusso, rbar, arichardson, sdardis, emaste.
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LLDB was detecting riscv64 ELF files as riscv32. This patch fixes that issue.

The patch follows the implementation approach previously used for MIPS. It defines RISC-V architecture subtypes and inspects the ELF header, namely the ELF class, to detect the right subtype. At the moment this is slightly silly, as the subtypes coincide with the architecture types (rv32 vs rv64), but given how the existing code was structured this seemed like a straightforward and future-proof solution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86292

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Utility/ArchSpec.cpp
  lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml


Index: lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
===================================================================
--- /dev/null
+++ lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj %s > %t
+# RUN: lldb-test object-file %t | FileCheck %s
+
+# CHECK: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_EXEC
+  Machine:         EM_RISCV
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -457,10 +457,10 @@
      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
     {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
      0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
-    {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
-     0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
-    {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
-     0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
+    {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+     ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
+    {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+     ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===================================================================
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -296,9 +296,23 @@
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+    return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+    return ArchSpec::eRISCVSubType_riscv64;
+  default:
+    return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
     return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+    return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
Index: lldb/include/lldb/Utility/ArchSpec.h
===================================================================
--- lldb/include/lldb/Utility/ArchSpec.h
+++ lldb/include/lldb/Utility/ArchSpec.h
@@ -99,6 +99,12 @@
     eRISCV_abi_d = 0x00000020
   };
 
+  enum RISCVSubType {
+    eRISCVSubType_unknown,
+    eRISCVSubType_riscv32,
+    eRISCVSubType_riscv64,
+  };
+
   enum Core {
     eCore_arm_generic,
     eCore_arm_armv4,


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