[Lldb-commits] [PATCH] D27088: [LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

[Nitesh Jain via lldb-commits]

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath, zturner.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.

In case of MIPS, the floating point register size is based on FR bit of status register(SR) (https://reviews.llvm.org/rL277343). In this patch, we update reg_info["bitsize"] based on SR.FR bit.


https://reviews.llvm.org/D27088

Files:
  packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py


Index: packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
===================================================================
--- packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
@@ -12,6 +12,7 @@
 
 from __future__ import print_function
 
+import struct
 
 import unittest2
 import gdbremote_testcase
@@ -565,6 +566,26 @@
             # Verify the response length.
             p_response = context.get("p_response")
             self.assertIsNotNone(p_response)
+            triple = lldb.DBG.GetSelectedPlatform().GetTriple()
+
+            if re.match("^mips",triple):
+                if reg_info["name"] == "sr":
+                    split_triple = triple.split("--",1)
+                    if split_triple[0] == "mips64el" or split_triple == "mipsel":
+                        # In case of little endian
+                        # first decode the HEX ASCII bytes and then reverse it
+                        # to get actual value of SR register  
+                        p_response = "".join(reversed([p_response[i:i+2] for i in range(0,
+                                             len(p_response),2)]))
+                    # Check for SR.FR bit
+                    # if SR.FR(26) == 0 && reg_info["format"] == "float"
+                    # then reg_info["bitsize"] = 32
+                    sr_value = int(p_response,16)
+                    flag = 1
+                    flag = (sr_value >> 26) & flag
+
+                if reg_info["format"] == "float" and (flag != 1):
+                    reg_info["bitsize"] = 32
             self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
 
             # Increment loop


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