[Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi,

@tberghammer : For both mips32 and mips64 big endian 'T' packet response contains the register values in target byte order only. But for mips32 big endian when we set the value of the register in RegisterValue using RegisterValue::SetUInt() the upper half of the container in RegisterValue contains zero value and the lower half contains the actual value. And when we fetch a pointer to the container in RegisterValue using RegisterValue::GetBytes() we get the start address of upper half of the container. Therefore while constructing 'T' packet response the function AppendHexValue() in GDBRemoteCommunicationServerLLGS.cpp called from WriteRegisterValueInHexFixedWidth() will read only the next 4 bytes it sees which are all zero. Therefore we get zero values for all registers at the client side:

> <   5> send packet: $?#3f

> < 680> read packet:

> $T17thread:774d;name:step_32eb.elf;threads:774d;jstopinfo:5b7b226e616d65223a22737465705f333265622e656c66222c22726561736f6e223a227369676e616c222c227369676e616c223a32332c22746964223a33303534317d5d;

> 00:00000000;01:00000000;02:00000000;03:00000000;04:00000000;05:00000000;06:00000000;07:00000000;08:00000000;09:00000000;

> 0a:00000000;0b:00000000;0c:00000000;0d:00000000;0e:00000000;0f:00000000;10:00000000;11:00000000;12:00000000;13:00000000;

> 14:00000000;15:00000000;16:00000000;17:00000000;18:00000000;19:00000000;1a:00000000;1b:00000000;1c:00000000;1d:00000000;

> 1e:00000000;1f:00000000;20:00000000;21:00000000;22:00000000;23:00000000;24:00000000;25:00000000;26:00000000;reason:signal;#47


@clayborg: After this change will submit a separate patch to read all GPRs in a single call for once and then extract the register value as needed in the MIPS register context.

Regards,
Sagar


Repository:
  rL LLVM

http://reviews.llvm.org/D14633