[Lldb-commits] [PATCH] D12079: [MIPS] microMIPS breakpoints, disassembly and compressed addresses

[Jaydeep Patil via lldb-commits]

jaydeep updated this revision to Diff 34199.
jaydeep added a comment.

In this patch:

The bit #0 has been cleared from addresses in the line tables. However we are relying upon ArchSpec instead of Target while clearing this bit in ParseDWARFLineTableCallback because SymbolContext may not have a valid target to call Address::GetOpcodeLoadAddress().

Bare-iron targets (like YAMON, IASim, Qemu) return compressed address (bit #0 set) when process is stopped in microMIPS address space. For example: bit #0 of PC is set when a breakpoint is hit. This bit has been cleared while reading the PC in RegisterContext::GetPC(). This would help us find breakpoints set using GetOpcodeLoadAddress (bit #0 clear),

DisassemblerLLVMC::DisassemblerLLVMC has been modified to create m_alternate_disasm_ap for microMIPS. This would display disassembly in either compressed (bit #0 set) or uncompressed (bit #0 clear) address space based on ISA mode.


Repository:
  rL LLVM

http://reviews.llvm.org/D12079

Files:
  source/Core/FormatEntity.cpp
  source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
  source/Target/RegisterContext.cpp
  source/Target/Target.cpp

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