[libcxx-commits] [PATCH] D134216: [SystemZ][z/OS] add code for hardware_concurrency()
Muiez Ahmed via Phabricator via libcxx-commits
libcxx-commits at lists.llvm.org
Tue Oct 25 12:25:09 PDT 2022
muiez updated this revision to Diff 470595.
muiez added a comment.
Move z/OS hardware_concurrency implementation to `support/ibm` directory.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134216/new/
https://reviews.llvm.org/D134216
Files:
libcxx/src/CMakeLists.txt
libcxx/src/support/ibm/hardware_concurrency_zos.cpp
libcxx/src/thread.cpp
Index: libcxx/src/thread.cpp
===================================================================
--- libcxx/src/thread.cpp
+++ libcxx/src/thread.cpp
@@ -70,6 +70,7 @@
__throw_system_error(ec, "thread::detach failed");
}
+#ifndef __MVS__
unsigned
thread::hardware_concurrency() noexcept
{
@@ -97,6 +98,7 @@
return 0; // Means not computable [thread.thread.static]
#endif // defined(CTL_HW) && defined(HW_NCPU)
}
+#endif // __MVS__
namespace this_thread
{
Index: libcxx/src/support/ibm/hardware_concurrency_zos.cpp
===================================================================
--- /dev/null
+++ libcxx/src/support/ibm/hardware_concurrency_zos.cpp
@@ -0,0 +1,43 @@
+//===------------------------- hardware_concurrency_zos.cpp----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <__config>
+
+#ifndef _LIBCPP_HAS_NO_THREADS
+#include <thread>
+
+_LIBCPP_BEGIN_NAMESPACE_STD
+
+// The following offsets are from the MVS Data Areas Volumes 1 & 3:
+// Volume 1: https://www-01.ibm.com/servers/resourcelink/svc00100.nsf/pages/
+// zosv2r3ga320935/$file/iead100_v2r3.pdf
+// Volume 3: https://www-01.ibm.com/servers/resourcelink/svc00100.nsf/pages/
+// zosv2r3ga320938/$file/iead300_v2r3.pdf
+//
+// In Vol 1, CSD_NUMBER_ONLINE_CPUS is at decimal offset 212 in CSD Mapping
+// (also Vol 1), which is pointed to by CVTCSD.
+//
+// CVTCSD is at decimal offset 660 in CVT Mapping (Vol 1), which is pointed
+// to by FLCCVT field of the PSA data area.
+//
+// FLCCVT is at decimal offset 16 in PSA Mapping (Vol 3), and PSA is at
+// address 0.
+//
+// So, with the 32-bit pointer casts, CSD_NUMBER_ONLINE_CPUS is at
+// 0[16/4][660/4][212/4] which is 0[4][165][53].
+//
+// Note: z/OS is always upward compatible, so these offsets won't change.
+
+unsigned
+thread::hardware_concurrency() noexcept {
+ return ((((int* __ptr32* __ptr32* __ptr32)0)[4])[165])[53];
+}
+
+_LIBCPP_END_NAMESPACE_STD
+
+#endif // !_LIBCPP_HAS_NO_THREADS
Index: libcxx/src/CMakeLists.txt
===================================================================
--- libcxx/src/CMakeLists.txt
+++ libcxx/src/CMakeLists.txt
@@ -112,6 +112,7 @@
support/ibm/mbsnrtowcs.cpp
support/ibm/wcsnrtombs.cpp
support/ibm/xlocale_zos.cpp
+ support/ibm/hardware_concurrency_zos.cpp
)
endif()
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