[libcxx-commits] [PATCH] D136264: [libunwind][RISCV] Support reading of VLENB CSR register

[Fangrui Song via Phabricator via libcxx-commits]

MaskRay added a comment.

In D136264#3939352 <https://reviews.llvm.org/D136264#3939352>, @craig.topper wrote:

> In D136264#3939348 <https://reviews.llvm.org/D136264#3939348>, @MaskRay wrote:
>
>>> Support read of VLENB (vector byte length) control register (CSR number: 0xC22, DWARF register number: 0x1C22 according to RISC-V DWARF specification: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc). This support is needed for correct unwinding of RVV objects on stack.
>>
>> I don't find 0x1C22 on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc
>>
>> No, please don't share false information.
>
> The DWARF spec generically says CSRs are assigned their CSR address plus 4096.

This information helps but is still unsatisfactory.

  The RISC-V specification defines a total of 4096 CSRs (see <<riscv-priv>>).
  Each CSR is assigned a DWARF register number corresponding to its specified CSR
  number plus 4096.
  
  [bibliography]
  == References
  
  * [[[riscv-priv]]] "The RISC-V Instruction Set Manual, Volume II: Privileged
  Architecture, Document", Editors Andrew Waterman, Krste Asanovi´c, and
  John Hauser, RISC-V International.

I don't think `[[riscv-priv]` assigns 0xc22 to VLENB. Referencing `v-spec.adoc` in riscv-elf-psabi-doc will probably help.


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